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1 | US2020118947A1 |
Solder Ball Protection in Packages
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Publication/Patent Number: US2020118947A1 | Publication Date: 2020-04-16 | Application Number: 16/713,870 | Filing Date: 2019-12-13 | Inventor： Miao chia chun Liang, Shih-wei Wu, Kai-chiang | Assignee: Taiwan Semiconductor Manufacturing Company, Ltd. | IPC: H01L23/00 | Abstract: An integrated circuit structure includes a substrate, a metal pad over the substrate, a passivation layer having a portion over the metal pad, and a polymer layer over the passivation layer. A Post-Passivation Interconnect (PPI) has a portion over the polymer layer, wherein the PPI is electrically coupled to the metal pad. The integrated circuit structure further includes a first solder region over and electrically coupled to a portion of the PPI, a second solder region neighboring the first solder region, a first coating material on a surface of the first solder region, and a second coating material on a surface of the second solder region. The first coating material and the second coating material encircle the first solder region and the second solder region, respectively. The first coating material is spaced apart from the second coating material. | |||
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2 | US2020279880A1 |
FLIP-CHIP SAMPLE IMAGING DEVICES WITH SELF-ALIGNING LID
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Publication/Patent Number: US2020279880A1 | Publication Date: 2020-09-03 | Application Number: 16/290,832 | Filing Date: 2019-03-01 | Inventor： Zhang, Ming Qian, Yin Miao chia chun Tai, Dyson H. | Assignee: OmniVision Technologies, Inc. | IPC: H01L27/146 | Abstract: A flip-chip sample imaging device with self-aligning lid includes an image sensor chip, a fan-out substrate, and a lid. The image sensor chip includes (a) a pixel array sensitive to light incident on a first side of the image sensor chip and (b) first electrical contacts disposed on the first side and electrically connected to the pixel array. The fan-out substrate is disposed on the first side, is electrically connected to the first electrical contacts, forms an aperture over the pixel array to partly define a sample chamber over the pixel array, and forms a first surface facing away from the first side. The lid is disposed on the first surface of the fan-out substrate, facing away from the first side, to further define the chamber. The lid includes an inner portion protruding into the aperture to align the lid relative to the fan-out substrate. | |||
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3 | US10720495B2 |
Semiconductor device and manufacturing method thereof
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Publication/Patent Number: US10720495B2 | Publication Date: 2020-07-21 | Application Number: 14/302,739 | Filing Date: 2014-06-12 | Inventor： Yu, Tsung-yuan Tsai, Hao-yi Shih, Chao-wen Kuo, Hung-yi Miao chia chun | Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. | IPC: H01L21/78 | Abstract: A semiconductor device includes a substrate and a bump. The substrate includes a first surface and a second surface. A notch is at the second surface and at a sidewall of the substrate. A depth of the notch is smaller than about half the thickness of the substrate. The bump is disposed on the first surface of the substrate. | |||
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4 | US10761385B2 |
Liquid crystal on silicon panel having less diffraction
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Publication/Patent Number: US10761385B2 | Publication Date: 2020-09-01 | Application Number: 15/852,313 | Filing Date: 2017-12-22 | Inventor： Zhang, Ming Weng, Libo Zhao, Cheng Qian, Yin Miao chia chun Lin, Zhiqiang Tai, Dyson H. | Assignee: OmniVision Technologies, Inc. | IPC: G02F1/1362 | Abstract: A liquid crystal on silicon (LCOS) panel comprises: a silicon substrate having silicon circuit within the silicon substrate; a plurality of metal electrodes disposed on the silicon substrate, where the plurality of metal electrodes are periodically formed on the silicon substrate; a dielectric material disposed in and filling gaps between adjacent metal electrodes; and an oxide layer disposed on the plurality of metal electrodes and the dielectric material in the gaps between adjacent metal electrodes; where the refractive index of the dielectric material is higher than the refractive index of the oxide layer. | |||
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5 | US10867957B2 |
Mechanisms for forming hybrid bonding structures with elongated bumps
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Publication/Patent Number: US10867957B2 | Publication Date: 2020-12-15 | Application Number: 16/223,274 | Filing Date: 2018-12-18 | Inventor： Lu, Chun-lin Wu, Kai-chiang Liu, Ming-kai Wang, Yen-ping Liang, Shih-wei Yang, Ching-feng Miao chia chun Lin, Hung-jen | Assignee: Taiwan Semiconductor Manufacturing Co., Ltd. | IPC: H01L23/00 | Abstract: Embodiments of mechanisms for forming a package structure are provided. The package structure includes a semiconductor die and a substrate. The package structure includes a pillar bump and an elongated solder bump bonded to the semiconductor die and the substrate. A height of the elongated solder bump is substantially equal to a height of the pillar bump. The elongated solder bump has a first width, at a first horizontal plane passing through an upper end of a sidewall surface of the elongated solder bump, and a second width, at a second horizontal plane passing through a midpoint of the sidewall surface. A ratio of the second width to the first width is in a range from about 0.5 to about 1.1. | |||
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6 | US10347563B2 |
Barrier structures between external electrical connectors
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Publication/Patent Number: US10347563B2 | Publication Date: 2019-07-09 | Application Number: 15/601,702 | Filing Date: 2017-05-22 | Inventor： Miao chia chun Wu, Kai-chiang Liang, Shih-wei | Assignee: Taiwan Semiconductor Manufacturing Company, Ltd. | IPC: H01L23/48 | Abstract: A structure includes a die substrate; a passivation layer on the die substrate; first and second interconnect structures on the passivation layer; and a barrier on the passivation layer, at least one of the first or second interconnect structures, or a combination thereof. The first and second interconnect structures comprise first and second via portions through the passivation layer to first and second conductive features of the die substrate, respectively. The first and second interconnect structures further comprise first and second pads, respectively, and first and second transition elements on a surface of the passivation layer between the first and second via portion and the first and second pad, respectively. The barrier is disposed between the first pad and the second pad. The barrier does not fully encircle at least one of the first pad or the second pad. | |||
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7 | US2019333841A1 |
Barrier Structures Between External Electrical Connectors
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Publication/Patent Number: US2019333841A1 | Publication Date: 2019-10-31 | Application Number: 16/504,807 | Filing Date: 2019-07-08 | Inventor： Miao chia chun Liang, Shih-wei Wu, Kai-chiang | Assignee: Taiwan Semiconductor Manufacturing Company, Ltd. | IPC: H01L23/48 | Abstract: A structure includes a die substrate; a passivation layer on the die substrate; first and second interconnect structures on the passivation layer; and a barrier on the passivation layer, at least one of the first or second interconnect structures, or a combination thereof. The first and second interconnect structures comprise first and second via portions through the passivation layer to first and second conductive features of the die substrate, respectively. The first and second interconnect structures further comprise first and second pads, respectively, and first and second transition elements on a surface of the passivation layer between the first and second via portion and the first and second pad, respectively. The barrier is disposed between the first pad and the second pad. The barrier does not fully encircle at least one of the first pad or the second pad. | |||
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8 | US10510689B2 |
Solder ball protection in packages
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Publication/Patent Number: US10510689B2 | Publication Date: 2019-12-17 | Application Number: 16/050,117 | Filing Date: 2018-07-31 | Inventor： Miao chia chun Liang, Shih-wei Wu, Kai-chiang | Assignee: Taiwan Semiconductor Manufacturing Company, Ltd. | IPC: H01L23/00 | Abstract: An integrated circuit structure includes a substrate, a metal pad over the substrate, a passivation layer having a portion over the metal pad, and a polymer layer over the passivation layer. A Post-Passivation Interconnect (PPI) has a portion over the polymer layer, wherein the PPI is electrically coupled to the metal pad. The integrated circuit structure further includes a first solder region over and electrically coupled to a portion of the PPI, a second solder region neighboring the first solder region, a first coating material on a surface of the first solder region, and a second coating material on a surface of the second solder region. The first coating material and the second coating material encircle the first solder region and the second solder region, respectively. The first coating material is spaced apart from the second coating material. | |||
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9 | US2019305027A1 |
INTERCONNECT LAYER CONTACT AND METHOD FOR IMPROVED PACKAGED INTEGRATED CIRCUIT RELIABILITY
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Publication/Patent Number: US2019305027A1 | Publication Date: 2019-10-03 | Application Number: 15/937,742 | Filing Date: 2018-03-27 | Inventor： Qian, Yin Miao chia chun Zhang, Ming Tai, Dyson H. | Assignee: OmniVision Technologies, Inc. | IPC: H01L27/146 | Abstract: Packaged photosensor ICs are made by fabricating an integrated circuit (IC) with multiple bondpads; forming vias from IC backside through semiconductor to expose a first layer metal; depositing conductive metal plugs in the vias; depositing interconnect metal; depositing solder-mask dielectric over the interconnect metal and openings therethrough; forming solder bumps on interconnect metal at the openings in the solder-mask dielectric; and bonding the solder bumps to conductors of a package. The photosensor IC has a substrate; multiple metal layers separated by dielectric layers formed on a first surface of the substrate into which transistors are formed; multiple bondpad structures formed of at least a first metal layer of the metal layers; vias with metal plugs formed through a dielectric over a second surface of the semiconductor substrate, interconnect metal on the dielectric forming connection shapes, and shapes of the interconnect layer coupled to each conductive plug and to solder bumps. | |||
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10 | TW201943049A |
Method of forming a packaged array and a photosensor integrated circuit
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Publication/Patent Number: TW201943049A | Publication Date: 2019-11-01 | Application Number: 108103353 | Filing Date: 2019-01-29 | Inventor： Zhang, Ming Qian, Yin Miao chia chun Tai, Dyson H. | Assignee: OMNIVISION TECHNOLOGIES, INC. | IPC: H01L21/56 | Abstract: Packaged photosensor ICs are made by fabricating an integrated circuit (IC) with multiple bondpads; forming vias from IC backside through semiconductor to expose a first layer metal; depositing conductive metal plugs in the vias; depositing interconnect metal; depositing solder-mask dielectric over the interconnect metal and openings therethrough; forming solder bumps on interconnect metal at the openings in the solder-mask dielectric; and bonding the solder bumps to conductors of a package. The photosensor IC has a substrate; multiple metal layers separated by dielectric layers formed on a first surface of the substrate into which transistors are formed; multiple bondpad structures formed of at least a first metal layer of the metal layers; vias with metal plugs formed through a dielectric over a second surface of the semiconductor substrate, interconnect metal on the dielectric forming connection shapes, and shapes of the interconnect layer coupled to each conductive plug and to solder bumps. | |||
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11 | TWI677085B |
Chip scale packaging for an image sensor
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Publication/Patent Number: TWI677085B | Publication Date: 2019-11-11 | Application Number: 107129985 | Filing Date: 2018-08-28 | Inventor： Li, Jin Zhang, Ming Qian, Yin Lu, Chen-wei Miao chia chun Tai, Dyson H. | Assignee: OMNIVISION TECHNOLOGIES, INC. | IPC: H01L27/146 | Abstract: A chip scale package (CSP) structure for an image sensor comprises an image sensor chip, wherein the image sensor chip comprises a semiconductor substrate having a top surface to receive light, a plurality of color filters disposed over the top surface, and a plurality of micro lenses disposed on the plurality of color filters. A low refractive index material is disposed over the image sensor chip, wherein the low refractive index material covers the plurality of micro lenses, and wherein a refractive index of the low refractive index material is lower than a refractive index of the plurality of micro lenses. A cover glass is disposed directly on the low refractive index material, wherein no air gap is between the cover glass and the low refractive index material, and between the low refractive index material and the image sensor chip. Therefore, the cover glass is fully supported by the low refractive index material without any dams. | |||
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12 | US10297627B1 |
Chip scale package for an image sensor
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Publication/Patent Number: US10297627B1 | Publication Date: 2019-05-21 | Application Number: 15/806,522 | Filing Date: 2017-11-08 | Inventor： Qian, Yin Lu, Chen-wei Li, Jin Miao chia chun Zhang, Ming Tai, Dyson | Assignee: OmniVision Technologies, Inc. | IPC: H01L27/146 | Abstract: A chip scale package (CSP) structure for an image sensor comprises an image sensor chip, wherein the image sensor chip comprises a semiconductor substrate having a top surface to receive light, a plurality of color filters disposed over the top surface, and a plurality of micro lenses disposed on the plurality of color filters. A low refractive index material is disposed over the image sensor chip, wherein the low refractive index material covers the plurality of micro lenses, and wherein a refractive index of the low refractive index material is lower than a refractive index of the plurality of micro lenses. A cover glass is disposed directly on the low refractive index material, wherein no air gap is between the cover glass and the low refractive index material, and between the low refractive index material and the image sensor chip. Therefore, the cover glass is fully supported by the low refractive index material without any dams. | |||
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13 | US2019140005A1 |
Chip Scale Package for An Image Sensor
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Publication/Patent Number: US2019140005A1 | Publication Date: 2019-05-09 | Application Number: 15/806,522 | Filing Date: 2017-11-08 | Inventor： Qian, Yin Lu, Chen-wei Li, Jin Miao chia chun Zhang, Ming Tai, Dyson | Assignee: OmniVision Technologies, Inc. | IPC: H01L27/146 | Abstract: A chip scale package (CSP) structure for an image sensor comprises an image sensor chip, wherein the image sensor chip comprises a semiconductor substrate having a top surface to receive light, a plurality of color filters disposed over the top surface, and a plurality of micro lenses disposed on the plurality of color filters. A low refractive index material is disposed over the image sensor chip, wherein the low refractive index material covers the plurality of micro lenses, and wherein a refractive index of the low refractive index material is lower than a refractive index of the plurality of micro lenses. A cover glass is disposed directly on the low refractive index material, wherein no air gap is between the cover glass and the low refractive index material, and between the low refractive index material and the image sensor chip. Therefore, the cover glass is fully supported by the low refractive index material without any dams. | |||
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14 | TW201931581A |
Chip scale packaging for an image sensor
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Publication/Patent Number: TW201931581A | Publication Date: 2019-08-01 | Application Number: 107129985 | Filing Date: 2018-08-28 | Inventor： Li, Jin Zhang, Ming Qian, Yin Lu, Chen-wei Miao chia chun Tai, Dyson H. | Assignee: OMNIVISION TECHNOLOGIES, INC. | IPC: H01L27/146 | Abstract: A chip scale package (CSP) structure for an image sensor comprises an image sensor chip, wherein the image sensor chip comprises a semiconductor substrate having a top surface to receive light, a plurality of color filters disposed over the top surface, and a plurality of micro lenses disposed on the plurality of color filters. A low refractive index material is disposed over the image sensor chip, wherein the low refractive index material covers the plurality of micro lenses, and wherein a refractive index of the low refractive index material is lower than a refractive index of the plurality of micro lenses. A cover glass is disposed directly on the low refractive index material, wherein no air gap is between the cover glass and the low refractive index material, and between the low refractive index material and the image sensor chip. Therefore, the cover glass is fully supported by the low refractive index material without any dams. | |||
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15 | US10418408B1 |
Curved image sensor using thermal plastic substrate material
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Publication/Patent Number: US10418408B1 | Publication Date: 2019-09-17 | Application Number: 16/016,057 | Filing Date: 2018-06-22 | Inventor： Zheng, Yuanwei Miao chia chun Chen, Gang Qian, Yin Mao, Duli Tai, Dyson H. Grant, Lindsay | Assignee: OmniVision Technologies, Inc. | IPC: H01L27/146 | Abstract: An image sensor includes a plurality of photodiodes arranged in an array and disposed in a semiconductor material to receive light through a first surface of the semiconductor material. At least part of the semiconductor material is curved. A carrier wafer is attached to a second surface, opposite the first surface, of the semiconductor material, and a polymer layer is attached to the carrier wafer, so that the carrier wafer is disposed between the polymer layer and the semiconductor material. | |||
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16 | US2019123017A1 |
Mechanisms for Forming Hybrid Bonding Structures with Elongated Bumps
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Publication/Patent Number: US2019123017A1 | Publication Date: 2019-04-25 | Application Number: 16/223,274 | Filing Date: 2018-12-18 | Inventor： Lu, Chun-lin Wu, Kai-chiang Liu, Ming-kai Wang, Yen-ping Liang, Shih-wei Yang, Ching-feng Miao chia chun Lin, Hung-jen | Assignee: Taiwan Semiconductor Manufacturing Co., Ltd. | IPC: H01L23/00 | Abstract: Embodiments of mechanisms for forming a package structure are provided. The package structure includes a semiconductor die and a substrate. The package structure includes a pillar bump and an elongated solder bump bonded to the semiconductor die and the substrate. A height of the elongated solder bump is substantially equal to a height of the pillar bump. The elongated solder bump has a first width, at a first horizontal plane passing through an upper end of a sidewall surface of the elongated solder bump, and a second width, at a second horizontal plane passing through a midpoint of the sidewall surface. A ratio of the second width to the first width is in a range from about 0.5 to about 1.1. | |||
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17 | US10269588B2 |
Integrated circuit underfill scheme
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Publication/Patent Number: US10269588B2 | Publication Date: 2019-04-23 | Application Number: 15/152,308 | Filing Date: 2016-05-11 | Inventor： Liang, Shih-wei Lu, Chun-lin Wu, Kai-chiang Yang, Ching-feng Liu, Ming-kai Miao chia chun Wang, Yen-ping | Assignee: Taiwan Semiconductor Manufacturing Company, Ltd. | IPC: H01L21/56 | Abstract: An integrated circuit includes a substrate having at least one depression on a top surface. At least one solder bump is disposed over the substrate. A die is disposed over the at least one solder bump and electrically connected with the substrate through the at least one solder bump. An underfill surrounds the at least one solder bump and is formed between the substrate and the die. The at least one depression is disposed around the underfill to keep any spillover from the underfill in the at least one depression. | |||
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18 | US10211243B2 |
Edge reflection reduction
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Publication/Patent Number: US10211243B2 | Publication Date: 2019-02-19 | Application Number: 15/945,541 | Filing Date: 2018-04-04 | Inventor： Miao chia chun Qian, Yin Lin, Chao-hung Lu, Chen-wei Tai, Dyson H. Zhang, Ming Li, Jin | Assignee: OmniVision Technologies, Inc. | IPC: H01L31/0203 | Abstract: A method of image sensor package fabrication includes providing an image sensor, including a pixel array disposed in a semiconductor material, and a first transparent shield adhered to the semiconductor material. The pixel array is disposed between the semiconductor material and the first transparent shield. A light blocking layer is deposited and disposed between lateral edges of the pixel array and lateral edges of the first transparent shield, and a second transparent shield is placed on the image sensor package, where the light blocking layer is disposed between the first transparent shield and the second transparent shield. | |||
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19 | US2019196284A1 |
LIQUID CRYSTAL ON SILICON PANEL HAVING LESS DIFFRACTION
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Publication/Patent Number: US2019196284A1 | Publication Date: 2019-06-27 | Application Number: 15/852,313 | Filing Date: 2017-12-22 | Inventor： Zhang, Ming Weng, Libo Zhao, Cheng Qian, Yin Miao chia chun Lin, Zhiqiang Tai, Dyson H. | Assignee: OmniVision Technologies, Inc. | IPC: G02F1/1362 | Abstract: A liquid crystal on silicon (LCOS) panel comprises: a silicon substrate having silicon circuit within the silicon substrate; a plurality of metal electrodes disposed on the silicon substrate, where the plurality of metal electrodes are periodically formed on the silicon substrate; a dielectric material disposed in and filling gaps between adjacent metal electrodes; and an oxide layer disposed on the plurality of metal electrodes and the dielectric material in the gaps between adjacent metal electrodes; where the refractive index of the dielectric material is higher than the refractive index of the oxide layer. | |||
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20 | US10049990B2 |
Solder ball protection in packages
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Publication/Patent Number: US10049990B2 | Publication Date: 2018-08-14 | Application Number: 14/201,253 | Filing Date: 2014-03-07 | Inventor： Wu, Kai-chiang Liang, Shih-wei Miao chia chun | Assignee: Taiwan Semiconductor Manufacturing Company, Ltd. | IPC: H01L23/16 | Abstract: An integrated circuit structure includes a substrate, a metal pad over the substrate, a passivation layer having a portion over the metal pad, and a polymer layer over the passivation layer. A Post-Passivation Interconnect (PPI) has a portion over the polymer layer, wherein the PPI is electrically coupled to the metal pad. The integrated circuit structure further includes a first solder region over and electrically coupled to a portion of the PPI, a second solder region neighboring the first solder region, a first coating material on a surface of the first solder region, and a second coating material on a surface of the second solder region. The first coating material and the second coating material encircle the first solder region and the second solder region, respectively. The first coating material is spaced apart from the second coating material. |
3.Current Quota