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1 | US2020256731A1 |
SPECTROMETERS WITH SELF-COMPENSATION OF MISALIGNMENT
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Publication/Patent Number: US2020256731A1 | Publication Date: 2020-08-13 | Application Number: 16/859,941 | Filing Date: 2020-04-27 | Inventor： Lee, Jae Hyung Kim, Youngsik Na yeul Kang, Juhyung | Assignee: Stratio | IPC: G01J3/14 | Abstract: An apparatus for analyzing light includes an input aperture for receiving light; a first set of one or more lenses configured to relay light from the input aperture; and a prism assembly configured to disperse light from the first set of one or more lenses. The prism assembly includes a plurality of prisms that includes a first prism, a second prism that is distinct from the first prism, and a third prism that is distinct from the first prism and the second prism. The first prism is mechanically coupled with the second prism and the second prism is mechanically coupled with the third prism. The apparatus also includes a second set of one or more lenses configured to focus the dispersed light from the prism assembly; and an array detector configured for converting the light from the second set of one or more lenses to electrical signals. | |||
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2 | EP3701217A1 |
SPECTROMETERS WITH SELF-COMPENSATION OF MISALIGNMENT
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Publication/Patent Number: EP3701217A1 | Publication Date: 2020-09-02 | Application Number: 18870058.7 | Filing Date: 2018-10-29 | Inventor： Lee, Jae Hyung Kim, Youngsik Na yeul Kang, Juhyung | Assignee: Stratio | IPC: G01B9/00 | ||||
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3 | EP3528288B1 |
GATE-CONTROLLED CHARGE MODULATED DEVICE FOR CMOS IMAGE SENSORS
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Publication/Patent Number: EP3528288B1 | Publication Date: 2020-08-26 | Application Number: 18214935.1 | Filing Date: 2014-06-20 | Inventor： Lee, Jae Hyung Na yeul Kim, Youngsik Jung, Woo-shik | Assignee: Stratio, Inc. | IPC: H01L27/146 | ||||
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4 | EP3608944A1 |
METHODS FOR REMOVING NUCLEI FORMED DURING EPITAXIAL GROWTH
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Publication/Patent Number: EP3608944A1 | Publication Date: 2020-02-12 | Application Number: 19188206.7 | Filing Date: 2016-05-23 | Inventor： Lee, Jae Hyung Na yeul Kim, Youngsik Jung, Woo-shik | Assignee: Stratio, Inc. | IPC: H01L21/20 | Abstract: A method for removing nuclei formed during a selective epitaxial growth process includes epitaxially growing a first group of one or more semiconductor structures over a substrate with one or more mask layers. A second group of a plurality of semiconductor structures is formed on the one or more mask layers. The method also includes forming one or more protective layers over the first group of one or more semiconductor structures. At least a subset of the second group of the plurality of semiconductor structures is exposed from the one or more protective layers. The method further includes, subsequent to forming the one or more protective layers over the first group of one or more semiconductor structures, etching at least the subset of the second group of the plurality of semiconductor structures. | |||
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5 | US10600640B2 |
Reduction of surface roughness in epitaxially grown germanium by controlled thermal oxidation
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Publication/Patent Number: US10600640B2 | Publication Date: 2020-03-24 | Application Number: 15/624,603 | Filing Date: 2017-06-15 | Inventor： Jung, Woo-shik Na yeul Kim, Youngsik Lee, Jae Hyung Lee, Jin Hyung | Assignee: Stratio, Inc. | IPC: H01L21/02 | Abstract: Methods for reducing surface roughness of germanium are described herein. In some embodiments, the surface roughness is reduced by thermal oxidation of germanium. In some embodiments, the surface roughness is further reduced by controlling a rate of the thermal oxidation. In some embodiments, the surface roughness is reduced by thermal annealing. | |||
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6 | US10366884B1 |
Methods for forming a germanium island using selective epitaxial growth and a sacrificial filling layer
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Publication/Patent Number: US10366884B1 | Publication Date: 2019-07-30 | Application Number: 16/184,984 | Filing Date: 2018-11-08 | Inventor： Lee, Jaehyung Na yeul Kim, Youngsik | Assignee: STRATIO | IPC: H01L21/02 | Abstract: A method for obtaining a semiconductor island includes epitaxially growing a semiconductor structure over a substrate with a mask layer defining a region not covered by the mask layer. The semiconductor structure includes a first portion located adjacent to the mask layer and a second portion located away from the mask layer. The first portion has a first height that is less than a second height of a portion of the mask layer located adjacent to the first portion. The second portion has a third height that is equal to, or greater than, the second height. The method also includes forming a filling layer over at least the first portion; and, subsequently removing at least a portion of the semiconductor structure that is located above the second height. Devices made by this method are also disclosed. | |||
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7 | WO2019084569A1 |
SPECTROMETERS WITH SELF-COMPENSATION OF MISALIGNMENT
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Publication/Patent Number: WO2019084569A1 | Publication Date: 2019-05-02 | Application Number: 2018058059 | Filing Date: 2018-10-29 | Inventor： Lee, Jae Kim, Youngsik Kang, Juhyung Na yeul | Assignee: LEE, JAE, HYUNG STRATIO | IPC: G01J1/00 | Abstract: An apparatus for analyzing light includes an input aperture for receiving light; a first set of one or more lenses configured to relay light from the input aperture; and a prism assembly configured to disperse light from the first set of one or more lenses. The prism assembly includes a plurality of prisms that includes a first prism, a second prism that is distinct from the first prism, and a third prism that is distinct from the first prism and the second prism. The first prism is mechanically coupled with the second prism and the second prism is mechanically coupled with the third prism. The apparatus also includes a second set of one or more lenses configured to focus the dispersed light from the prism assembly; and an array detector configured for converting the light from the second set of one or more lenses to electrical signals. | |||
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8 | US2019221595A1 |
Gate-controlled Charge Modulated Device for CMOS Image Sensors
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Publication/Patent Number: US2019221595A1 | Publication Date: 2019-07-18 | Application Number: 16/167,241 | Filing Date: 2018-10-22 | Inventor： Lee, Jae Hyung Na yeul Kim, Youngsik Jung, Woo-shik | Assignee: Stratio Inc. | IPC: H01L27/146 | Abstract: A device for sensing light includes a first semiconductor region doped with a dopant of a first type and a second semiconductor region doped with a dopant of a second type. The second semiconductor region is positioned above the first semiconductor region. The device includes a gate insulation layer; a gate, a source, and a drain. The second semiconductor region has a top surface that is positioned toward the gate insulation layer and a bottom surface that is positioned opposite to the top surface of the second semiconductor region. The second semiconductor region has an upper portion that includes the top surface of the second semiconductor region and a lower portion that includes the bottom surface of the second semiconductor region and is mutually exclusive with the upper portion. The first semiconductor region is in contact with both the upper portion and the lower portion of the second semiconductor region. | |||
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9 | EP3528288A1 |
GATE-CONTROLLED CHARGE MODULATED DEVICE FOR CMOS IMAGE SENSORS
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Publication/Patent Number: EP3528288A1 | Publication Date: 2019-08-21 | Application Number: 18214935.1 | Filing Date: 2014-06-20 | Inventor： Lee, Jae Hyung Na yeul Kim, Youngsik Jung, Woo-shik | Assignee: Stratio, Inc. | IPC: H01L27/146 | Abstract: A device for sensing light includes a first semiconductor region doped with a dopant of a first type and a second semiconductor region doped with a dopant of a second type. The second semiconductor region is positioned above the first semiconductor region. The device includes a gate insulation layer; a gate, a source, and a drain. The second semiconductor region has a top surface that is positioned toward the gate insulation layer and a bottom surface that is positioned opposite to the top surface of the second semiconductor region. The second semiconductor region has an upper portion that includes the top surface of the second semiconductor region and a lower portion that includes the bottom surface of the second semiconductor region and is mutually exclusive with the upper portion. The first semiconductor region is in contact with both the upper portion and the lower portion of the second semiconductor region. | |||
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10 | US10281327B2 |
Spectrometers with self-compensation of rotational misalignment
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Publication/Patent Number: US10281327B2 | Publication Date: 2019-05-07 | Application Number: 15/821,591 | Filing Date: 2017-11-22 | Inventor： Lee, Jae Hyung Kim, Youngsik Na yeul Kang, Juhyung | Assignee: STRATIO | IPC: G01J3/14 | Abstract: An apparatus for analyzing light includes an input aperture for receiving light; a first set of one or more lenses configured to relay light from the input aperture; and a prism assembly configured to disperse light from the first set of one or more lenses. The prism assembly includes a plurality of prisms that includes a first prism, a second prism that is distinct from the first prism, and a third prism that is distinct from the first prism and the second prism. The first prism is mechanically coupled with the second prism and the second prism is mechanically coupled with the third prism. The apparatus also includes a second set of one or more lenses configured to focus the dispersed light from the prism assembly; and an array detector configured for converting the light from the second set of one or more lenses to electrical signals. | |||
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11 | US201894976A1 |
Spectrometers with Self-Compensation of Rotational Misalignment
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Publication/Patent Number: US201894976A1 | Publication Date: 2018-04-05 | Application Number: 20/171,582 | Filing Date: 2017-11-22 | Inventor： Saraswat, Krishna C Na yeul Lee, Jae Hyung Na yeul | Assignee: Stratio | IPC: G01J3/28 | Abstract: An apparatus for analyzing light includes an input aperture for receiving light; a first set of one or more lenses configured to relay light from the input aperture; and a prism assembly configured to disperse light from the first set of one or more lenses. The prism assembly includes a plurality of prisms that includes a first prism, a second prism that is distinct from the first prism, and a third prism that is distinct from the first prism and the second prism. The first prism is mechanically coupled with the second prism and the second prism is mechanically coupled with the third prism. The apparatus also includes a second set of one or more lenses configured to focus the dispersed light from the prism assembly; and an array detector configured for converting the light from the second set of one or more lenses to electrical signals. | |||
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12 | KR20180029091A |
METHODS FOR REMOVING NUCLEI FORMED DURING EPITAXIAL GROWTH
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Publication/Patent Number: KR20180029091A | Publication Date: 2018-03-19 | Application Number: 20187006394 | Filing Date: 2016-05-23 | Inventor： Lee, Jae Hyung Kim, Youngsik Na yeul Jung, Woo Shik | Assignee: STRATIO, INC. STRATIO | IPC: H01L21/02 | Abstract: 선택적 에피택셜 성장 공정 동안 형성되는 핵을 제거하는 방법은, 하나 이상의 마스크 층을 갖는 기판 위에 하나 이상의 반도체 구조의 제1 그룹을 에피택셜 성장시키는 단계를 포함한다. 복수의 반도체 구조의 제2 그룹은 하나 이상의 마스크 층 상에 형성된다. 방법은, 또한, 하나 이상의 반도체 구조의 제1 그룹 위에 하나 이상의 보호층을 형성하는 단계를 포함한다. 복수의 반도체 구조의 제2 그룹의 적어도 서브세트는 하나 이상의 보호층으로부터 노출된다. 방법은, 하나 이상의 반도체 구조의 제1 그룹 위에 하나 이상의 보호층을 형성하는 단계에 후속하여, 복수의 반도체 구조의 제2 그룹의 적어도 그 서브세트를 에칭하는 단계를 더 포함한다. | |||
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13 | JP2018129536A |
GATE CONTROL TYPE CHARGING MODULATION DEVICE FOR CMOS IMAGE SENSOR
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Publication/Patent Number: JP2018129536A | Publication Date: 2018-08-16 | Application Number: 2018078326 | Filing Date: 2018-04-16 | Inventor： Lee, Jae-hyung Kim, Youngsik Jung, Woo Shik Na yeul | Assignee: STRATIO INC | IPC: H01L31/10 | Abstract: PROBLEM TO BE SOLVED: To provide an optical sensor having a small dark current, a high quantum efficiency, and an enhancement channel modulation.SOLUTION: A device 100 for detecting a light, includes: a first semiconductor region 104 doped by using a first type dopant; and a second semiconductor region 106 doped by using a second type dopant. The second semiconductor region is arranged on an upper direction of the first semiconductor region. The device includes: a gate insulation layer 110; a gate 112; a source 114; and a drain 116. The second semiconductor region includes an upper surface arranged so as to be directed to the gate insulation layer, and a bottom surface arranged on the side opposite to the upper surface of the second semiconductor region. The second semiconductor region includes: an upper part including the upper surface of the second semiconductor region; and a lower part including the bottom surface of the second semiconductor region which is alternately excluded from an upper side part. The first semiconductor region is contacted with both sides of an upper side part and a lower side part of the second semiconductor region.SELECTED DRAWING: Figure 1A | |||
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14 | EP3011594B1 |
GATE-CONTROLLED CHARGE MODULATED DEVICE FOR CMOS IMAGE SENSORS
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Publication/Patent Number: EP3011594B1 | Publication Date: 2018-12-26 | Application Number: 14814462.9 | Filing Date: 2014-06-20 | Inventor： Lee, Jae Hyung Na yeul Kim, Youngsik Jung, Woo-shik | Assignee: Stratio, Inc. | IPC: H01L27/146 | ||||
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15 | US10109662B2 |
Gate-controlled charge modulated device for CMOS image sensors
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Publication/Patent Number: US10109662B2 | Publication Date: 2018-10-23 | Application Number: 14/967,262 | Filing Date: 2015-12-11 | Inventor： Lee, Jae Hyung Na yeul Kim, Youngsik Jung, Woo-shik | Assignee: Stratio, Inc. | IPC: H01L27/146 | Abstract: A device for sensing light includes a first semiconductor region doped with a dopant of a first type and a second semiconductor region doped with a dopant of a second type. The second semiconductor region is positioned above the first semiconductor region. The device includes a gate insulation layer; a gate, a source, and a drain. The second semiconductor region has a top surface that is positioned toward the gate insulation layer and a bottom surface that is positioned opposite to the top surface of the second semiconductor region. The second semiconductor region has an upper portion that includes the top surface of the second semiconductor region and a lower portion that includes the bottom surface of the second semiconductor region and is mutually exclusive with the upper portion. The first semiconductor region is in contact with both the upper portion and the lower portion of the second semiconductor region. | |||
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16 | US2018094976A1 |
Spectrometers with Self-Compensation of Rotational Misalignment
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Publication/Patent Number: US2018094976A1 | Publication Date: 2018-04-05 | Application Number: 15/821,591 | Filing Date: 2017-11-22 | Inventor： Kang, Juhyung Na yeul Kim, Youngsik Lee, Jae Hyung | Assignee: Stratio | IPC: G02B27/10 | Abstract: An apparatus for analyzing light includes an input aperture for receiving light; a first set of one or more lenses configured to relay light from the input aperture; and a prism assembly configured to disperse light from the first set of one or more lenses. The prism assembly includes a plurality of prisms that includes a first prism, a second prism that is distinct from the first prism, and a third prism that is distinct from the first prism and the second prism. The first prism is mechanically coupled with the second prism and the second prism is mechanically coupled with the third prism. The apparatus also includes a second set of one or more lenses configured to focus the dispersed light from the prism assembly; and an array detector configured for converting the light from the second set of one or more lenses to electrical signals. | |||
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17 | EP3011594A4 |
GATE-CONTROLLED CHARGE MODULATED DEVICE FOR CMOS IMAGE SENSORS
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Publication/Patent Number: EP3011594A4 | Publication Date: 2017-03-01 | Application Number: 14814462 | Filing Date: 2014-06-20 | Inventor： Kim, Youngsik Lee, Jae Hyung Na yeul Jung, Woo-shik | Assignee: Stratio, Inc. | IPC: H01L27/146 | ||||
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18 | EP3111466A1 |
METHODS FOR REMOVING NUCLEI FORMED DURING EPITAXIAL GROWTH
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Publication/Patent Number: EP3111466A1 | Publication Date: 2017-01-04 | Application Number: 16750355.6 | Filing Date: 2016-05-23 | Inventor： Lee, Jae Hyung Na yeul Kim, Youngsik Jung, Woo-shik | Assignee: Stratio, Inc. STRATIO | IPC: H01L21/02 | ||||
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19 | EP3111466A4 |
METHODS FOR REMOVING NUCLEI FORMED DURING EPITAXIAL GROWTH
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Publication/Patent Number: EP3111466A4 | Publication Date: 2017-03-29 | Application Number: 16750355 | Filing Date: 2016-05-23 | Inventor： Na yeul Jung, Woo-shik Kim, Youngsik Lee, Jae Hyung | Assignee: Stratio, Inc. | IPC: H01L21/20 | ||||
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20 | KR20170029638A |
METHODS FOR REMOVING NUCLEI FORMED DURING EPITAXIAL GROWTH
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Publication/Patent Number: KR20170029638A | Publication Date: 2017-03-15 | Application Number: 20177005543 | Filing Date: 2016-05-23 | Inventor： Lee, Jae Hyung Kim, Youngsik Na yeul Jung, Woo Shik | Assignee: STRATIO, INC. STRATIO | IPC: H01L21/02 | Abstract: 선택적 에피택셜 성장 공정 동안 형성되는 핵을 제거하는 방법은 |
3.Current Quota