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1
EP3832567A1
ALCOHOL INFORMATION MANAGEMENT SYSTEM AND MANAGEMENT METHOD
Publication/Patent Number: EP3832567A1 Publication Date: 2021-06-09 Application Number: 19843266.8 Filing Date: 2019-07-12 Inventor: Nakanishi, Kenichi   Assignee: Iroxori Corporation   IPC: G06Q10/08 Abstract: An integrated management server comprising: a data formatting means for receiving sales record information from a plurality of distributor terminals of a plurality of distributors which are selling products to retailers; a data matching means for updating brand master information for universally managing alcoholic beverage brands sold to the retailers across the plurality of distributors based on each of the received sales record information; and a brand Identification means for analyzing image related information received from a user terminal, identifying an alcoholic beverage brand by comparing a feature information corresponding to an alcoholic beverage brand registered in the brand master information, and sending information related to identified alcoholic beverage brand to the user terminal; and the user terminal comprising: a display means for displaying information on the sent alcoholic beverage brand.
2
US2021081136A1
MEMORY CONTROLLER, MEMORY SYSTEM, INFORMATION PROCESSING SYSTEM, AND MEMORY CONTROL METHOD
Publication/Patent Number: US2021081136A1 Publication Date: 2021-03-18 Application Number: 16/629,615 Filing Date: 2018-04-03 Inventor: Nakanishi, Kenichi   Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION   IPC: G06F3/06 Abstract: Efficient wear leveling processing is performed in a memory in which the number of times of writing may vary for each of pages that are access units. An address conversion unit performs address conversion between a logical address of a host command and a physical address of the memory for each of management units, the management units each including a plurality of access units of the memory. A write amount measurement unit measures a write amount for each of the access units in each of the management units. The averaging processing unit selects a target management unit from the management units on the basis of the write amount measured by the write amount measurement unit and changes physical address allocation in the address conversion of the target management unit. Then, the averaging processing unit performs processing of averaging write amounts of the access units in the target management unit.
3
US11016703B2
Memory controller, memory system, information system, and memory control method
Publication/Patent Number: US11016703B2 Publication Date: 2021-05-25 Application Number: 16/325,866 Filing Date: 2017-07-27 Inventor: Nakanishi, Kenichi   Assignee: SONY CORPORATION   IPC: G06F11/07 Abstract: A delay due to retry processing with regard to occurrence of a memory write error is suppressed. A sub-region command holding section holds a host command as a sub-region command divided with respect to each access target sub-region. A sub-region address conversion section converts an address of an access target sub-region to an address of a memory regarding a sub-region command. A sub-region command execution section executes a sub-region command whose address has been converted, and accesses a memory. In a case where a write error occurs in a memory regarding a sub-region command, an address conversion management section performs preparation processing of a substitute region for a sub-region command in which the write error has occurred concurrently with execution of another sub-region command in the sub-region command execution section.
4
US11023381B2
System and method for a hit-based ratio write cache operation mode in a storage controller
Publication/Patent Number: US11023381B2 Publication Date: 2021-06-01 Application Number: 16/611,532 Filing Date: 2018-02-05 Inventor: Kaneda, Teruya   Nakanishi, Kenichi   Okubo, Hideaki   Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION   IPC: G06F12/0868 Abstract: An object is to suppress a process of evicting cached data so as to improve a throughput of an entire system. A storage controller includes an access request section and an operation management section. The access request section requests access to a first storage and to a second storage that is higher in response speed than the first storage, the second storage storing part of data stored in the first storage. The operation management section manages, based on a usage state of the second storage, whether or not to transfer from the first storage to the second storage data targeted for access but not stored in the second storage.
5
US11029881B2
Memory controller, memory system, and information processing system
Publication/Patent Number: US11029881B2 Publication Date: 2021-06-08 Application Number: 16/311,100 Filing Date: 2017-04-17 Inventor: Ishii, Ken   Iwaki, Hiroyuki   Nakanishi, Kenichi   Fujinami, Yasushi   Shinbashi, Tatsuo   Assignee: SONY CORPORATION   IPC: G06F3/06 Abstract: The order of read access to a memory is appropriately determined. A memory system includes a plurality of memories and a memory controller. The memory controller includes a memory write control unit and a memory read control unit. The memory write control unit generates a write request for any one of the plurality of memories on the basis of a write command from a computer. The memory read control unit generates a read request for any one of the plurality of memories according to priority corresponding to a data processing state of write data related to the write request in the memory write control unit on the basis of a read command from the computer.
6
US10528287B2
Memory, memory controller, storage apparatus, information processing system, and control method for tracking erase count and rewrite cycles of memory pages
Publication/Patent Number: US10528287B2 Publication Date: 2020-01-07 Application Number: 15/761,590 Filing Date: 2016-07-01 Inventor: Nakanishi, Kenichi   Assignee: SONY CORPORATION   IPC: G06F3/06 Abstract: To enhance accuracy of counting the number of rewrite cycles in a non-volatile memory that is overwritable. A memory outputs erase information that is information regarding whether or not erase processing has been performed in writing of data in units of pages each including a plurality of memory cells in which data is rewritten by program processing of shifting a memory cell that stores data from an initial state to a data-storing state and erase processing of shifting the memory cell from the data-storing state to the initial state. The number of rewrite cycles is counted by updating the number of rewrite cycles on a basis of the output erase information.
7
WO2020021791A1
STORAGE CONTROL DEVICE, STORAGE DEVICE, AND INFORMATION PROCESSING SYSTEM
Publication/Patent Number: WO2020021791A1 Publication Date: 2020-01-30 Application Number: 2019016105 Filing Date: 2019-04-15 Inventor: Nakanishi, Kenichi   Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION   IPC: G06F3/06 Abstract: In the present invention, only data having a high access frequency is registered in a cache storage. The cache storage stores a portion of data that is to be stored in a main storage. A cache management unit retains an access frequency for each cache entry in the cache storage. A candidate cache management unit retains an access frequency for each candidate entry not registered in the cache storage. A cache update unit updates an access frequency in accordance with the address of an issued access command, and updates the cache entry and the candidate entry on the basis of the access frequency.
8
WO2020026763A1
ALCOHOL INFORMATION MANAGEMENT SYSTEM AND MANAGEMENT METHOD
Publication/Patent Number: WO2020026763A1 Publication Date: 2020-02-06 Application Number: 2019027660 Filing Date: 2019-07-12 Inventor: Nakanishi, Kenichi   Assignee: IROXORI CORPORATION   IPC: G06Q50/10 Abstract: An integrated management server has: a data shaping means that receives and prepares sales results information from each of a plurality of distribution company terminals of a plurality of distribution companies that sell products to a store; a data matching means that updates brand master information which is for managing, jointly for the plurality of distribution companies, brands of alcohol sold by the store, on the basis of the respectively received sales results information; and a brand determination means that, when image-related information is received from a user terminal, analyzes the image-related information and carries out a comparison with respect to characteristic information corresponding to a brand of alcohol registered in the brand master information, thereby identifying a brand of alcohol, and transmits information pertaining to the identified brand of alcohol to the user terminal. The user terminal has a display means for displaying the transmitted information pertaining to the brand of alcohol.
9
US2020364109A1
MEMORY CONTROLLER, MEMORY, MEMORY SYSTEM, INFORMATION PROCESSING SYSTEM, AND METHOD OF CONTROL THEREOF
Publication/Patent Number: US2020364109A1 Publication Date: 2020-11-19 Application Number: 16/763,469 Filing Date: 2018-08-06 Inventor: Iwaki, Hiroyuki   Nakanishi, Kenichi   Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION   IPC: G06F11/10 Abstract: A load of a data channel at the time of data writing is reduced. A memory controller includes a specific data pattern retaining unit, a comparator, and an issuance unit. The specific data pattern retaining unit retains a specific data pattern. The comparator compares write data regarding a write command from a host computer with the specific data pattern. The issuance unit issues a specific write request that requests writing of the specific data pattern without supplying the write data to a memory in a case where the write data matches the specific data pattern.
10
US10540275B2
Memory controller, information processing system, and memory extension area management method
Publication/Patent Number: US10540275B2 Publication Date: 2020-01-21 Application Number: 15/523,763 Filing Date: 2015-10-08 Inventor: Okubo, Hideaki   Nakanishi, Kenichi   Fujinami, Yasushi   Assignee: Sony Corporation   IPC: G06F12/00 Abstract: To secure flexibility of the memory extension area which is secured on the memory of the host computer and used by the memory controller. [Solution] A controller memory stores data corresponding to an area allocated to a memory in a memory controller configured to control the memory. An access control unit allocates a partial area of the controller memory to a host memory in a host computer and uses the areas as a memory extension area. The extension area managing unit performs management so that a size of the memory extension area in the host memory is changeable.
11
US2020117601A1
STORAGE CONTROLLER, STORAGE SYSTEM, STORAGE CONTROLLER CONTROLLING METHOD, AND PROGRAM
Publication/Patent Number: US2020117601A1 Publication Date: 2020-04-16 Application Number: 16/611,532 Filing Date: 2018-02-05 Inventor: Kaneda, Teruya   Nakanishi, Kenichi   Okubo, Hideaki   Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION   IPC: G06F12/0811 Abstract: An object is to suppress a process of evicting cached data so as to improve a throughput of an entire system. A storage controller includes an access request section and an operation management section. The access request section requests access to a first storage and to a second storage that is higher in response speed than the first storage, the second storage storing part of data stored in the first storage. The operation management section manages, based on a usage state of the second storage, whether or not to transfer from the first storage to the second storage data targeted for access but not stored in the second storage.
12
KR20200009140A
GLASS CLOTH
Publication/Patent Number: KR20200009140A Publication Date: 2020-01-29 Application Number: 20207001654 Filing Date: 2016-04-27 Inventor: Nakanishi, Kenichi   Tachibana, Shinichiro   Someya, Makoto   Assignee: ASAHI KASEI KABUSHIKI KAISHA   IPC: H05K1/03 Abstract: 복수개의 유리 필라멘트를 포함하는 유리실을 제직하여 이루어지는 유리 클로스이며, 상기 유리 필라멘트 중, BO조성량이 20질량% 내지 30질량%이고, SiO조성량이 50질량% 내지 60질량%이고, 상기 유리 클로스의 강열 감량값이 0.25질량% 내지 1.0질량%인 유리 클로스이다.
13
US2020301843A1
MEMORY ACCESS DEVICE, MEMORY SYSTEM, AND INFORMATION PROCESSING SYSTEM
Publication/Patent Number: US2020301843A1 Publication Date: 2020-09-24 Application Number: 16/754,680 Filing Date: 2018-07-05 Inventor: Okubo, Hideaki   Nakanishi, Kenichi   Kaneda, Teruya   Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION   IPC: G06F12/0884 Abstract: Memory devices having different parallel accessible data sizes and different access speeds are caused to work efficiently as a cache memory. A memory access device accesses first and second memory devices that respectively include a plurality of parallel accessible memories and have different parallel accessible data sizes and different access speeds. The memory access device includes a management information storage unit and an access control unit. The management information storage unit stores management information as associating each corresponding management unit of the first and second memory devices. The access control unit accesses one of the first and second memory devices on the basis of the management information.
14
WO2020031435A1
STORAGE CONTROL UNIT, STORAGE DEVICE AND STORAGE CONTROL METHOD
Publication/Patent Number: WO2020031435A1 Publication Date: 2020-02-13 Application Number: 2019016624 Filing Date: 2019-04-18 Inventor: Ishii, Ken   Okubo, Hideaki   Shibahara, Yoshiyuki   Terada, Haruhiko   Nakanishi, Kenichi   Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION   IPC: G11C16/34 Abstract: To prevent a selector malfunction caused by a drift in a memory having a cross-point structure. A memory cell array is provided with a data area and a drift reference cell. An accumulated drift amount acquisition unit acquires an accumulated drift amount of the drift reference cell. A total drift amount reading unit reads the total drift amount stored in the data area. A refresh control unit adds the accumulated drift amount to the total drift amount, thereby allowing the total drift amount to be updated as a new total drift amount. Further, when the new total drift amount exceeds a predetermined threshold, the data area of the memory cell array is refreshed.
15
US2020310681A1
MEMORY CONTROLLER, MEMORY SYSTEM, AND INFORMATION PROCESSING SYSTEM
Publication/Patent Number: US2020310681A1 Publication Date: 2020-10-01 Application Number: 16/311,100 Filing Date: 2017-04-17 Inventor: Ishii, Ken   Iwaki, Hiroyuki   Nakanishi, Kenichi   Fujinami, Yasushi   Shinbashi, Tatsuo   Assignee: SONY CORPORATION   IPC: G06F3/06 Abstract: The order of read access to a memory is appropriately determined. A memory system includes a plurality of memories and a memory controller. The memory controller includes a memory write control unit and a memory read control unit. The memory write control unit generates a write request for any one of the plurality of memories on the basis of a write command from a computer. The memory read control unit generates a read request for any one of the plurality of memories according to priority corresponding to a data processing state of write data related to the write request in the memory write control unit on the basis of a read command from the computer.
16
US10545804B2
Memory controller, memory system, and memory controller control method
Publication/Patent Number: US10545804B2 Publication Date: 2020-01-28 Application Number: 15/507,413 Filing Date: 2015-07-22 Inventor: Shinbashi, Tatsuo   Tsutsui, Keiichi   Okubo, Hideaki   Sakai, Lui   Nakanishi, Kenichi   Fujinami, Yasushi   Assignee: Sony Corporation   IPC: G06F11/00 Abstract: [Object] To sufficiently reduce frequency of error occurrence in memory cells. [Solution] A reading unit reads read data from a memory cell, the read data including an information bit and reversal information for determining whether or not the information bit has been reversed. In addition, an error detection/correction unit detects the presence or absence of an error in the information bit and corrects the error. A data reversing unit reverses the information bit that has the error corrected and the reversal information. Furthermore, a writing unit writes the reversed information bit and the reversed reversal information in the memory cell.
17
JP2019005874A
CORRECTION METHOD AND CORRECTION DEVICE OF THERMAL DISPLACEMENT OF MACHINE TOOL
Publication/Patent Number: JP2019005874A Publication Date: 2019-01-17 Application Number: 2017125247 Filing Date: 2017-06-27 Inventor: Nakanishi, Kenichi   Assignee: NAKAMURA TOME PRECISION IND CO LTD   IPC: B23Q15/18 Abstract: To provide a selection and change method of a correction coefficient in correcting thermal displacement of a machine tool, and provide a thermal displacement correction device for the same.SOLUTION: A correction device includes: a machining dimension recording part in which a machining dimension of a workpiece measured at a predetermined machining time is input and recorded; and a correction information recording part in which information necessary for correction is recorded. The correction information recording part calculates a new coefficient of a temperature correction formula from estimation of a machining dimension of the workpiece when temperature correction and wear correction are not carried out on the basis of detection value information from a temperature sensor mounted on each part of a machine, information of a temperature correction amount calculated based on the detection value, and information which is information of a wear correction amount by wear of a tool and is recorded in the machining dimension recording part and the correction information recording part during previous operation, at a start of next operation.SELECTED DRAWING: Figure 1
18
US2019102319A1
MEMORY CONTROLLER, MEMORY SYSTEM, INFORMATION PROCESSING SYSTEM, MEMORY CONTROL METHOD, AND PROGRAM
Publication/Patent Number: US2019102319A1 Publication Date: 2019-04-04 Application Number: 16/083,164 Filing Date: 2016-12-28 Inventor: Nakanishi, Kenichi   Assignee: SONY CORPORATION   IPC: G06F12/121 Abstract: To reduce a capacity of a buffer included in a memory controller for managing a replacement area of a memory. Replacement management information for managing a relationship between a predetermined data area of a memory and a replacement area corresponding to the data area is stored in the memory. A memory controller includes: a replacement management information buffer configured to hold part of the replacement management information. A replacement processing unit, in a case in which replacement has occurred in the memory for data related to an access command from a host computer to the memory, causes the replacement management information buffer to hold the replacement management information of a portion of the data for which the replacement has occurred.
19
JP2019172365A
CONTAINER HOLDER
Publication/Patent Number: JP2019172365A Publication Date: 2019-10-10 Application Number: 2018077991 Filing Date: 2018-03-29 Inventor: Nakanishi, Kenichi   Assignee: COCOAM KK   IPC: B65D25/22 Abstract: To provide means for making it possible to hold a beverage container without placing it on a desk or the like in a state where hands are occupied, for example, by holding chopsticks and dishes.SOLUTION: A container holder for erecting and holding an approximately columnar container by clamping an opening part and a bottom part thereof by an upper hooking piece A1 and a lower hooking piece A2 includes the upper hooking piece A1 hooked at a periphery of the opening part of the container, the lower hooking piece A2 hooked at an upland erected on the bottom part of the container, a coupling part A3 for arranging the upper and lower hooking pieces A1 and A2 at an approximately fixed distance so as to face them to clamp the container, a connection part A4 arranged to the coupling part A3, and a holding part A5 connected to the connection part A4 to suspend or hook the container.SELECTED DRAWING: Figure 1
20
JP2019034360A
BED STRUCTURE OF MACHINE TOOL
Publication/Patent Number: JP2019034360A Publication Date: 2019-03-07 Application Number: 2017156273 Filing Date: 2017-08-12 Inventor: Nakanishi, Kenichi   Assignee: NAKAMURA TOME PRECISION IND CO LTD   IPC: B23Q1/01 Abstract: To provide a bed structure of a machine tool, which can easily secure rigidity and which is effective for reducing thermal displacement.SOLUTION: A slant structure-type bed includes a sliding surface part where a sliding rail is horizontally arranged, and a plate-like part approximately parallel to the sliding surface part, which is provided on the downside of the sliding surface part.SELECTED DRAWING: Figure 1
Total 36 pages