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No. Publication Number Title Publication/Patent Number Publication/Patent Number Publication Date Publication Date
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1 US10528287B2
Memory, memory controller, storage apparatus, information processing system, and control method for tracking erase count and rewrite cycles of memory pages
Publication/Patent Number: US10528287B2 Publication Date: 2020-01-07 Application Number: 15/761,590 Filing Date: 2016-07-01 Inventor: Nakanishi, Kenichi   Assignee: SONY CORPORATION   IPC: G06F3/06 Abstract: To enhance accuracy of counting the number of rewrite cycles in a non-volatile memory that is overwritable. A memory outputs erase information that is information regarding whether or not erase processing has been performed in writing of data in units of pages each including a plurality of memory cells in which data is rewritten by program processing of shifting a memory cell that stores data from an initial state to a data-storing state and erase processing of shifting the memory cell from the data-storing state to the initial state. The number of rewrite cycles is counted by updating the number of rewrite cycles on a basis of the output erase information. To enhance accuracy of counting the number of rewrite cycles in a non-volatile memory that is overwritable. A memory outputs erase information that is information regarding whether or not erase processing has been performed in writing of data in units of pages each including a ...More ...Less
2 US2020117601A1
STORAGE CONTROLLER, STORAGE SYSTEM, STORAGE CONTROLLER CONTROLLING METHOD, AND PROGRAM
Publication/Patent Number: US2020117601A1 Publication Date: 2020-04-16 Application Number: 16/611,532 Filing Date: 2018-02-05 Inventor: Kaneda, Teruya   Nakanishi, Kenichi   Okubo, Hideaki   Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION   IPC: G06F12/0811 Abstract: An object is to suppress a process of evicting cached data so as to improve a throughput of an entire system. A storage controller includes an access request section and an operation management section. The access request section requests access to a first storage and to a second storage that is higher in response speed than the first storage, the second storage storing part of data stored in the first storage. The operation management section manages, based on a usage state of the second storage, whether or not to transfer from the first storage to the second storage data targeted for access but not stored in the second storage. An object is to suppress a process of evicting cached data so as to improve a throughput of an entire system. A storage controller includes an access request section and an operation management section. The access request section requests access to a first storage and to a ...More ...Less
3 US10540275B2
Memory controller, information processing system, and memory extension area management method
Publication/Patent Number: US10540275B2 Publication Date: 2020-01-21 Application Number: 15/523,763 Filing Date: 2015-10-08 Inventor: Okubo, Hideaki   Nakanishi, Kenichi   Fujinami, Yasushi   Assignee: Sony Corporation   IPC: G06F12/00 Abstract: To secure flexibility of the memory extension area which is secured on the memory of the host computer and used by the memory controller. [Solution] A controller memory stores data corresponding to an area allocated to a memory in a memory controller configured to control the memory. An access control unit allocates a partial area of the controller memory to a host memory in a host computer and uses the areas as a memory extension area. The extension area managing unit performs management so that a size of the memory extension area in the host memory is changeable. To secure flexibility of the memory extension area which is secured on the memory of the host computer and used by the memory controller. [Solution] A controller memory stores data corresponding to an area allocated to a memory in a memory controller configured to control the ...More ...Less
4 US10545804B2
Memory controller, memory system, and memory controller control method
Publication/Patent Number: US10545804B2 Publication Date: 2020-01-28 Application Number: 15/507,413 Filing Date: 2015-07-22 Inventor: Shinbashi, Tatsuo   Tsutsui, Keiichi   Okubo, Hideaki   Sakai, Lui   Nakanishi, Kenichi   Fujinami, Yasushi   Assignee: Sony Corporation   IPC: G06F11/00 Abstract: [Object] To sufficiently reduce frequency of error occurrence in memory cells. [Solution] A reading unit reads read data from a memory cell, the read data including an information bit and reversal information for determining whether or not the information bit has been reversed. In addition, an error detection/correction unit detects the presence or absence of an error in the information bit and corrects the error. A data reversing unit reverses the information bit that has the error corrected and the reversal information. Furthermore, a writing unit writes the reversed information bit and the reversed reversal information in the memory cell. [Object] To sufficiently reduce frequency of error occurrence in memory cells. [Solution] A reading unit reads read data from a memory cell, the read data including an information bit and reversal information for determining whether or not the information bit has been reversed ...More ...Less
5 US2019102319A1
MEMORY CONTROLLER, MEMORY SYSTEM, INFORMATION PROCESSING SYSTEM, MEMORY CONTROL METHOD, AND PROGRAM
Publication/Patent Number: US2019102319A1 Publication Date: 2019-04-04 Application Number: 16/083,164 Filing Date: 2016-12-28 Inventor: Nakanishi, Kenichi   Assignee: SONY CORPORATION   IPC: G06F12/121 Abstract: To reduce a capacity of a buffer included in a memory controller for managing a replacement area of a memory. Replacement management information for managing a relationship between a predetermined data area of a memory and a replacement area corresponding to the data area is stored in the memory. A memory controller includes: a replacement management information buffer configured to hold part of the replacement management information. A replacement processing unit, in a case in which replacement has occurred in the memory for data related to an access command from a host computer to the memory, causes the replacement management information buffer to hold the replacement management information of a portion of the data for which the replacement has occurred. To reduce a capacity of a buffer included in a memory controller for managing a replacement area of a memory. Replacement management information for managing a relationship between a predetermined data area of a memory and a replacement area corresponding to the data area is ...More ...Less
6 US2019205065A1
MEMORY CONTROLLER, MEMORY SYSTEM, INFORMATION SYSTEM, AND MEMORY CONTROL METHOD
Publication/Patent Number: US2019205065A1 Publication Date: 2019-07-04 Application Number: 16/325,866 Filing Date: 2017-07-27 Inventor: Nakanishi, Kenichi   Assignee: SONY CORPORATION   IPC: G06F3/06 Abstract: A delay due to retry processing with regard to occurrence of a memory write error is suppressed. A sub-region command holding section holds a host command as a sub-region command divided with respect to each access target sub-region. A sub-region address conversion section converts an address of an access target sub-region to an address of a memory regarding a sub-region command. A sub-region command execution section executes a sub-region command whose address has been converted, and accesses a memory. In a case where a write error occurs in a memory regarding a sub-region command, an address conversion management section performs preparation processing of a substitute region for a sub-region command in which the write error has occurred concurrently with execution of another sub-region command in the sub-region command execution section. A delay due to retry processing with regard to occurrence of a memory write error is suppressed. A sub-region command holding section holds a host command as a sub-region command divided with respect to each access target sub-region. A sub-region address conversion section ...More ...Less
7 US2019095136A1
MEMORY CONTROL DEVICE, STORAGE DEVICE, AND INFORMATION PROCESSING SYSTEM
Publication/Patent Number: US2019095136A1 Publication Date: 2019-03-28 Application Number: 16/086,833 Filing Date: 2016-12-28 Inventor: Okubo, Hideaki   Nakanishi, Kenichi   Assignee: SONY CORPORATION   IPC: G06F3/06 Abstract: To perform both writing and reading at a high speed by utilizing a first memory and a second memory that has a lower writing speed and a higher reading speed than the first memory. A writing unit writes writing data related to a writing command in a first memory when the writing command is executed. A transfer unit transfers the writing data from the first memory to a second memory at a predetermined timing. A reading unit performs reading of reading data from the second memory with higher priority than from the first memory when a reading command is executed. To perform both writing and reading at a high speed by utilizing a first memory and a second memory that has a lower writing speed and a higher reading speed than the first memory. A writing unit writes writing data related to a writing command in a first memory when the writing ...More ...Less