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1
US11023381B2
System and method for a hit-based ratio write cache operation mode in a storage controller
Publication/Patent Number: US11023381B2 Publication Date: 2021-06-01 Application Number: 16/611,532 Filing Date: 2018-02-05 Inventor: Kaneda, Teruya   Nakanishi, Kenichi   Okubo, Hideaki   Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION   IPC: G06F12/0868 Abstract: An object is to suppress a process of evicting cached data so as to improve a throughput of an entire system. A storage controller includes an access request section and an operation management section. The access request section requests access to a first storage and to a second storage that is higher in response speed than the first storage, the second storage storing part of data stored in the first storage. The operation management section manages, based on a usage state of the second storage, whether or not to transfer from the first storage to the second storage data targeted for access but not stored in the second storage.
2
US2021055880A1
MEMORY CONTROLLER AND MEMORY MODULE
Publication/Patent Number: US2021055880A1 Publication Date: 2021-02-25 Application Number: 16/959,511 Filing Date: 2018-10-15 Inventor: Ishii, Ken   Nakanish, Kenichi   Okubo, Hideaki   Kaneda, Teruya   Assignee: Sony Semiconductor Solutions Corporationn   IPC: G06F3/06 Abstract: Even data mapped to discrete physical addresses of a volatile memory is saved in a non-volatile memory. A memory management information registration unit registers, as an entry of memory management information, a physical address of a first memory that is volatile memory and an address of a second memory that is a non-volatile memory, in association for every management unit. A control unit saves data from the first memory into the second memory in accordance with the memory management information in response to a save request, and restores data from the second memory into the first memory in accordance with the memory management information in response to a restore request.
3
US2020301843A1
MEMORY ACCESS DEVICE, MEMORY SYSTEM, AND INFORMATION PROCESSING SYSTEM
Publication/Patent Number: US2020301843A1 Publication Date: 2020-09-24 Application Number: 16/754,680 Filing Date: 2018-07-05 Inventor: Okubo, Hideaki   Nakanishi, Kenichi   Kaneda, Teruya   Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION   IPC: G06F12/0884 Abstract: Memory devices having different parallel accessible data sizes and different access speeds are caused to work efficiently as a cache memory. A memory access device accesses first and second memory devices that respectively include a plurality of parallel accessible memories and have different parallel accessible data sizes and different access speeds. The memory access device includes a management information storage unit and an access control unit. The management information storage unit stores management information as associating each corresponding management unit of the first and second memory devices. The access control unit accesses one of the first and second memory devices on the basis of the management information.
4
US10540275B2
Memory controller, information processing system, and memory extension area management method
Publication/Patent Number: US10540275B2 Publication Date: 2020-01-21 Application Number: 15/523,763 Filing Date: 2015-10-08 Inventor: Okubo, Hideaki   Nakanishi, Kenichi   Fujinami, Yasushi   Assignee: Sony Corporation   IPC: G06F12/00 Abstract: To secure flexibility of the memory extension area which is secured on the memory of the host computer and used by the memory controller. [Solution] A controller memory stores data corresponding to an area allocated to a memory in a memory controller configured to control the memory. An access control unit allocates a partial area of the controller memory to a host memory in a host computer and uses the areas as a memory extension area. The extension area managing unit performs management so that a size of the memory extension area in the host memory is changeable.
5
US2020117601A1
STORAGE CONTROLLER, STORAGE SYSTEM, STORAGE CONTROLLER CONTROLLING METHOD, AND PROGRAM
Publication/Patent Number: US2020117601A1 Publication Date: 2020-04-16 Application Number: 16/611,532 Filing Date: 2018-02-05 Inventor: Kaneda, Teruya   Nakanishi, Kenichi   Okubo, Hideaki   Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION   IPC: G06F12/0811 Abstract: An object is to suppress a process of evicting cached data so as to improve a throughput of an entire system. A storage controller includes an access request section and an operation management section. The access request section requests access to a first storage and to a second storage that is higher in response speed than the first storage, the second storage storing part of data stored in the first storage. The operation management section manages, based on a usage state of the second storage, whether or not to transfer from the first storage to the second storage data targeted for access but not stored in the second storage.
6
WO2020031435A1
STORAGE CONTROL UNIT, STORAGE DEVICE AND STORAGE CONTROL METHOD
Publication/Patent Number: WO2020031435A1 Publication Date: 2020-02-13 Application Number: 2019016624 Filing Date: 2019-04-18 Inventor: Ishii, Ken   Okubo, Hideaki   Shibahara, Yoshiyuki   Terada, Haruhiko   Nakanishi, Kenichi   Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION   IPC: G11C16/34 Abstract: To prevent a selector malfunction caused by a drift in a memory having a cross-point structure. A memory cell array is provided with a data area and a drift reference cell. An accumulated drift amount acquisition unit acquires an accumulated drift amount of the drift reference cell. A total drift amount reading unit reads the total drift amount stored in the data area. A refresh control unit adds the accumulated drift amount to the total drift amount, thereby allowing the total drift amount to be updated as a new total drift amount. Further, when the new total drift amount exceeds a predetermined threshold, the data area of the memory cell array is refreshed.
7
US10545804B2
Memory controller, memory system, and memory controller control method
Publication/Patent Number: US10545804B2 Publication Date: 2020-01-28 Application Number: 15/507,413 Filing Date: 2015-07-22 Inventor: Shinbashi, Tatsuo   Tsutsui, Keiichi   Okubo, Hideaki   Sakai, Lui   Nakanishi, Kenichi   Fujinami, Yasushi   Assignee: Sony Corporation   IPC: G06F11/00 Abstract: [Object] To sufficiently reduce frequency of error occurrence in memory cells. [Solution] A reading unit reads read data from a memory cell, the read data including an information bit and reversal information for determining whether or not the information bit has been reversed. In addition, an error detection/correction unit detects the presence or absence of an error in the information bit and corrects the error. A data reversing unit reverses the information bit that has the error corrected and the reversal information. Furthermore, a writing unit writes the reversed information bit and the reversed reversal information in the memory cell.
8
WO2019244417A1
STORAGE CONTROL DEVICE, STORAGE DEVICE, AND STORAGE CONTROL METHOD
Publication/Patent Number: WO2019244417A1 Publication Date: 2019-12-26 Application Number: 2019008514 Filing Date: 2019-03-05 Inventor: Okubo, Hideaki   Nakanishi, Kenichi   Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION   IPC: G11C13/00 Abstract: The present invention eliminates drift that has occurred in memory cells and continuously uses the memory cells. This storage control device controls a memory cell array in which each bit has any one state among first and second states. The storage control device is provided with a detection unit and a control unit. The detection unit detects a transition bit that is a bit in the second state, which should be in the first state, in the memory cell array. The control unit controls to supply, to the transition bit, a drift refresh voltage higher than a read voltage necessary for reading from the memory cell array.
9
US2019095136A1
MEMORY CONTROL DEVICE, STORAGE DEVICE, AND INFORMATION PROCESSING SYSTEM
Publication/Patent Number: US2019095136A1 Publication Date: 2019-03-28 Application Number: 16/086,833 Filing Date: 2016-12-28 Inventor: Okubo, Hideaki   Nakanishi, Kenichi   Assignee: SONY CORPORATION   IPC: G06F3/06 Abstract: To perform both writing and reading at a high speed by utilizing a first memory and a second memory that has a lower writing speed and a higher reading speed than the first memory. A writing unit writes writing data related to a writing command in a first memory when the writing command is executed. A transfer unit transfers the writing data from the first memory to a second memory at a predetermined timing. A reading unit performs reading of reading data from the second memory with higher priority than from the first memory when a reading command is executed.
10
US201995136A1
MEMORY CONTROL DEVICE, STORAGE DEVICE, AND INFORMATION PROCESSING SYSTEM
Publication/Patent Number: US201995136A1 Publication Date: 2019-03-28 Application Number: 20/161,608 Filing Date: 2016-12-28 Inventor: Nakanishi, Kenichi   Okubo, Hideaki   Assignee: Sony Corporation   IPC: G06F13/24 Abstract: To perform both writing and reading at a high speed by utilizing a first memory and a second memory that has a lower writing speed and a higher reading speed than the first memory. A writing unit writes writing data related to a writing command in a first memory when the writing command is executed. A transfer unit transfers the writing data from the first memory to a second memory at a predetermined timing. A reading unit performs reading of reading data from the second memory with higher priority than from the first memory when a reading command is executed.
11
JP2019004012A
THERMOELECTRIC MODULE
Publication/Patent Number: JP2019004012A Publication Date: 2019-01-10 Application Number: 2017116650 Filing Date: 2017-06-14 Inventor: Okubo, Hideaki   Kushibiki, Shunsuke   Horikoshi, Masato   Assignee: KELK LTD   IPC: H02N11/00 Abstract: To provide a thermoelectric module capable of reducing stress occurring at the juncture of a thermoelectric element and an electrode due to thermal expansion of the electrode.SOLUTION: A thermoelectric module 10 includes first and second thermoelectric elements 1P, 1N, a first electrode 21 having a tabular body 211, and joined to the first end faces of the first and second thermoelectric elements 1P, 1N on the first surface of the body 211, a second electrode 22A joined to the second end face of the first thermoelectric element 1P, and a third electrode 22B joined to the second end face of the second thermoelectric element 1N. The first electrode 21 has a first notch 213A formed on the first side 211A in the width direction D, and a second notch 213B formed on the second side 211B in the width direction D. In the width direction D, at least any one of the first and second notches 213A, 213B is formed in a section between the first and second sides 211A, 211B of the first electrode 21.SELECTED DRAWING: Figure 3
12
EP1519275B1
INFORMATION STORAGE DEVICE, MEMORY ACCESS CONTROL METHOD, AND COMPUTER PROGRAM
Publication/Patent Number: EP1519275B1 Publication Date: 2019-03-27 Application Number: 03760898.1 Filing Date: 2003-06-19 Inventor: Okaue, Takumi   Nakanishi, Kenichi   Tashiro, Jun   Okubo, Hideaki   Assignee: Sony Corporation   IPC: G06F21/62
13
WO2019138624A1
MEMORY CONTROLLER AND MEMORY MODULE
Publication/Patent Number: WO2019138624A1 Publication Date: 2019-07-18 Application Number: 2018038309 Filing Date: 2018-10-15 Inventor: Ishii, Ken   Kaneda, Teruya   Okubo, Hideaki   Nakanishi, Kenichi   Assignee: SONY CORPORATION   SONY SEMICONDUCTOR SOLUTIONS CORPORATION   IPC: G06F12/06 Abstract: The purpose of the present invention is to allow even data mapped to discrete physical addresses of a volatile memory to be saved in a nonvolatile memory appropriately. A memory management information registration unit associates, for each management unit, a physical address of a first memory that is a volatile memory and an address of a second memory that is a nonvolatile memory with each other, and registers the association as an entry of memory management information. In response to a save request, a control unit saves data from the first memory to the second memory in accordance with the memory management information. In response to a restore request, the control unit restores data from the second memory to the first memory in accordance with the memory management information.
14
EP1517244B1
INFORMATION STORAGE DEVICE, MEMORY ACCESS CONTROL SYSTEM AND METHOD, AND COMPUTER PROGRAM
Publication/Patent Number: EP1517244B1 Publication Date: 2019-01-09 Application Number: 03760900.5 Filing Date: 2003-06-19 Inventor: Okubo, Hideaki   Tashiro, Jun   Nakanishi, Kenichi   Okaue, Takumi   Assignee: Sony Corporation   IPC: G06F12/14 Abstract: A device and method is provided for commonly and securely allowing, as access control on a memory card, a plurality of information processing apparatuses to lock/unlock the memory. On the basis of a lock command input from an information processing apparatus serving as a host, such as a PC, an information storage device, such as a memory card, determines whether (a) a standard lock key set serving as a key set prohibiting output or (b) an export lock key set serving as a key set permitting output is detected and stores corresponding key set information. Only when the export lock key set is detected, output is permitted provided that predetermined verification succeeds.
15
WO2019077812A1
MEMORY ACCESS DEVICE, MEMORY SYSTEM, AND INFORMATION PROCESSING SYSTEM
Publication/Patent Number: WO2019077812A1 Publication Date: 2019-04-25 Application Number: 2018025468 Filing Date: 2018-07-05 Inventor: Kaneda, Teruya   Okubo, Hideaki   Nakanishi, Kenichi   Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION   IPC: G06F12/0873 Abstract: The objective of the present invention is to cause memory devices which have different data sizes and access speeds and which are accessed in parallel to operate efficiently as cache memory. This memory access device accesses first and second memory devices which have different data sizes and access speeds, are accessed in parallel, and each include a plurality of memories that can be accessed in parallel. The memory access device is provided with a management information storage unit and an access control unit. The management information storage unit associates and stores, as management information, respective management units corresponding to the first and second memory devices. The access control unit accesses one of the first and second memory devices on the basis of the management information.
16
EP3211536B1
MEMORY CONTROLLER, MEMORY SYSTEM, AND MEMORY CONTROLLER CONTROL METHOD
Publication/Patent Number: EP3211536B1 Publication Date: 2019-09-04 Application Number: 15851846.4 Filing Date: 2015-07-22 Inventor: Shinbashi, Tatsuo   Tsutsui, Keiichi   Okubo, Hideaki   Sakai, Lui   Nakanishi, Kenichi   Fujinami, Yasushi   Assignee: Sony Corporation   IPC: G06F12/16
17
US10481971B2
Encoding device, memory controller, communication system, and encoding method
Publication/Patent Number: US10481971B2 Publication Date: 2019-11-19 Application Number: 15/736,079 Filing Date: 2016-04-15 Inventor: Shinbashi, Tatsuo   Nakanishi, Kenichi   Fujinami, Yasushi   Iwaki, Hiroyuki   Ishii, Ken   Okubo, Hideaki   Assignee: Sony Corporation   IPC: G06F11/10 Abstract: A data holding characteristic of a memory cell is improved in a memory system in which data is encoded and written to a memory cell. A first candidate parity generation unit generates, as a first candidate parity, a parity for detecting an error in an information section in which a predetermined value is assigned in a predetermined variable area. A second candidate parity generation unit generates, as a second candidate parity, a parity for detecting an error in the information section in which a value different from the predetermined value is assigned in the predetermined variable area. A selection unit selects a parity that satisfies a predetermined condition from among the first and second candidate parities as a selection parity. An output unit outputs a codeword constituted by the information section corresponding to the selection parity and the selection parity.
18
US10338984B2
Storage control apparatus, storage apparatus, and storage control method
Publication/Patent Number: US10338984B2 Publication Date: 2019-07-02 Application Number: 15/505,674 Filing Date: 2015-07-09 Inventor: Fujinami, Yasushi   Nakanishi, Kenichi   Shiimoto, Tsunenori   Yamamoto, Tetsuya   Shinbashi, Tatsuo   Okubo, Hideaki   Terada, Haruhiko   Ishii, Ken   Iwaki, Hiroyuki   Honjo, Matatoshi   Assignee: SONY CORPORATION   IPC: G06F11/00 Abstract: Detecting a defective cell in a memory in consideration of an error property difference depending on the storage state. A determination unit determines whether there is a possibility of defect for each of unit-of-storages on a memory cell formed with a non-volatile memory. The non-volatile memory undergoes either a reset operation that transitions a state from a low resistive state (LRS) to a high resistive state (HRS) or a set operation that transitions the state from the high resistive state to the low resistive state. The determination unit determines a unit-of-storage in which the number of errors in predetermined one of the reset operation and the set operation has exceeded a predetermined standard, as a unit-of-storage suspected of having a defect.
19
WO2018211749A1
STORAGE CONTROLLER, STORAGE SYSTEM, METHOD FOR CONTROLLING STORAGE CONTROLLER, AND PROGRAM
Publication/Patent Number: WO2018211749A1 Publication Date: 2018-11-22 Application Number: 2018003768 Filing Date: 2018-02-05 Inventor: Kaneda, Teruya   Okubo, Hideaki   Nakanishi, Kenichi   Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION   IPC: G06F12/12 Abstract: The present invention suppresses a cache data expulsion process and improves the throughput of a system as a whole. A storage controller, provided with an access request unit and an operation management unit. The access request unit requests access to a first storage, and to a second storage which has a response speed greater than that of the first storage and in which some of data in the first storage is stored. When there is access to data that is not stored in the second storage, an operation management unit manages, on the basis of the state of usage of the second storage, whether or not to transfer data from the first storage to the second storage.
20
US10031865B2
Memory system, storage device, and method for controlling memory system
Publication/Patent Number: US10031865B2 Publication Date: 2018-07-24 Application Number: 15/527,374 Filing Date: 2015-10-08 Inventor: Tsutsui, Keiichi   Okubo, Hideaki   Sakai, Lui   Terada, Haruhiko   Assignee: SONY CORPORATION   IPC: