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No. Publication Number Title Publication/Patent Number Publication/Patent Number Publication Date Publication Date
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1
US10879114B1
Conductive fill
Publication/Patent Number: US10879114B1 Publication Date: 2020-12-29 Application Number: 16/549,256 Filing Date: 2019-08-23 Inventor: Wu, Jung-tang   Liao, Chi-hung   Wu, Szu-hua   Ou yang liang yueh   Lee, Chin-szu   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L21/4763 Abstract: A conductive fill is provided in an opening of an interconnect layer. A seed layer is formed, a portion of which is then oxidized. The oxygen is removed in a treatment process and the surface of the de-oxidized seed layer is hydrolyzed to form a hydroxyl sublayer and moisturized. The conductive fill is formed over the hydroxyl sublayer.
2
US10867845B2
Semiconductor device and method
Publication/Patent Number: US10867845B2 Publication Date: 2020-12-15 Application Number: 16/599,940 Filing Date: 2019-10-11 Inventor: Wang, Yu-sheng   Hung, Chi-cheng   Su, Ching-hwanq   Ou yang liang yueh   Tsai, Ming-hsing   Lin, Yu-ting   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L21/768 Abstract: A method includes forming a first opening in a dielectric layer over a substrate, lining sidewalls and a bottom of the first opening with a conductive barrier layer, and depositing a seed layer over the conductive barrier layer. The method further includes treating the seed layer with a plasma process, and filling the first opening with a conductive material after the treating the seed layer.
3
US10636702B2
Conductive interconnect structures in integrated circuits
Publication/Patent Number: US10636702B2 Publication Date: 2020-04-28 Application Number: 16/178,470 Filing Date: 2018-11-01 Inventor: Wu, Jung-tang   Lien, Shao Tzu   Liao, Chi-hung   Wu, Szu-hua   Ou yang liang yueh   Lee, Chin-szu   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L21/4763 Abstract: An interconnect structure and a method of forming the interconnect structure are provided. A dielectric layer and openings therein are formed over a substrate. A conductive seed layer is formed over the top surface and along a bottom and sidewalls of the openings. A conductive fill layer is formed over the seed layer. Metal oxide on the surface of the seed layer may be reduced/removed by a surface pre-treatment. The cleaned surface is covered by depositing fill material over the seed layer without exposing the surface to oxygen. The surface treatment may include a reactive remote plasma clean using hydrogen radicals. If electroplating is used to deposit the fill layer, then the surface treatment may include soaking the substrate in the electrolyte before turning on the electroplating current. Other surface treatments may include active pre-clean (APC) using hydrogen radicals; or Ar sputtering using a metal clean version xT (MCxT) tool.
4
US202043781A1
Semiconductor Device and Method
Publication/Patent Number: US202043781A1 Publication Date: 2020-02-06 Application Number: 20/191,659 Filing Date: 2019-10-11 Inventor: Tsai, Ming-hsing   Wang, Yu-sheng   Hung, Chi-cheng   Su, Ching-hwanq   Lin, Yu-ting   Ou yang liang yueh   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L29/66 Abstract: A method includes forming a first opening in a dielectric layer over a substrate, lining sidewalls and a bottom of the first opening with a conductive barrier layer, and depositing a seed layer over the conductive barrier layer. The method further includes treating the seed layer with a plasma process, and filling the first opening with a conductive material after the treating the seed layer.
5
US2020075407A1
Methods for Forming Contact Plugs with Reduced Corrosion
Publication/Patent Number: US2020075407A1 Publication Date: 2020-03-05 Application Number: 16/678,410 Filing Date: 2019-11-08 Inventor: Wang, Yu-sheng   Hung, Chi-cheng   Kao, Chen-yuan   Chiu, Yi-wei   Ou yang liang yueh   Pai, Yueh-ching   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L21/768 Abstract: A method includes forming an ILD to cover a gate stack of a transistor. The ILD and the gate stack are parts of a wafer. The ILD is etched to form a contact opening, and a source/drain region of the transistor or a gate electrode in the gate stack is exposed through the contact opening. A conductive capping layer is formed to extend into the contact opening. A metal-containing material is plated on the conductive capping layer in a plating solution using electrochemical plating. The metal-containing material has a portion filling the contact opening. The plating solution has a sulfur content lower than about 100 ppm. A planarization is performed on the wafer to remove excess portions of the metal-containing material. A remaining portion of the metal-containing material and a remaining portion of the conductive capping layer in combination form a contact plug.
6
US2020105593A1
Conductive Interconnect Structures in Integrated Circuits
Publication/Patent Number: US2020105593A1 Publication Date: 2020-04-02 Application Number: 16/178,470 Filing Date: 2018-11-01 Inventor: Wu, Jung-tang   Lien, Shao Tzu   Liao, Chi-hung   Wu, Szu-hua   Ou yang liang yueh   Lee, Chin-szu   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L21/768 Abstract: An interconnect structure and a method of forming the interconnect structure are provided. A dielectric layer and openings therein are formed over a substrate. A conductive seed layer is formed over the top surface and along a bottom and sidewalls of the openings. A conductive fill layer is formed over the seed layer. Metal oxide on the surface of the seed layer may be reduced/removed by a surface pre-treatment. The cleaned surface is covered by depositing fill material over the seed layer without exposing the surface to oxygen. The surface treatment may include a reactive remote plasma clean using hydrogen radicals. If electroplating is used to deposit the fill layer, then the surface treatment may include soaking the substrate in the electrolyte before turning on the electroplating current. Other surface treatments may include active pre-clean (APC) using hydrogen radicals; or Ar sputtering using a metal clean version xT (MCxT) tool.
7
US2020043781A1
Semiconductor Device and Method
Publication/Patent Number: US2020043781A1 Publication Date: 2020-02-06 Application Number: 16/599,940 Filing Date: 2019-10-11 Inventor: Wang, Yu-sheng   Hung, Chi-cheng   Su, Ching-hwanq   Ou yang liang yueh   Tsai, Ming-hsing   Lin, Yu-ting   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L21/768 Abstract: A method includes forming a first opening in a dielectric layer over a substrate, lining sidewalls and a bottom of the first opening with a conductive barrier layer, and depositing a seed layer over the conductive barrier layer. The method further includes treating the seed layer with a plasma process, and filling the first opening with a conductive material after the treating the seed layer.
8
US2020258777A1
Conductive Interconnect Structures in Integrated Circuits
Publication/Patent Number: US2020258777A1 Publication Date: 2020-08-13 Application Number: 16/858,838 Filing Date: 2020-04-27 Inventor: Wu, Jung-tang   Lien, Shao Tzu   Liao, Chi-hung   Wu, Szu-hua   Ou yang liang yueh   Lee, Chin-szu   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L21/768 Abstract: An interconnect structure and a method of forming the interconnect structure are provided. A dielectric layer and openings therein are formed over a substrate. A conductive seed layer is formed over the top surface and along a bottom and sidewalls of the openings. A conductive fill layer is formed over the seed layer. Metal oxide on the surface of the seed layer may be reduced/removed by a surface pre-treatment. The cleaned surface is covered by depositing fill material over the seed layer without exposing the surface to oxygen. The surface treatment may include a reactive remote plasma clean using hydrogen radicals. If electroplating is used to deposit the fill layer, then the surface treatment may include soaking the substrate in the electrolyte before turning on the electroplating current. Other surface treatments may include active pre-clean (APC) using hydrogen radicals; or Ar sputtering using a metal clean version xT (MCxT) tool.
9
US10872815B2
Conductive interconnect structures in integrated circuits
Publication/Patent Number: US10872815B2 Publication Date: 2020-12-22 Application Number: 16/858,838 Filing Date: 2020-04-27 Inventor: Wu, Jung-tang   Lien, Shao Tzu   Liao, Chi-hung   Wu, Szu-hua   Ou yang liang yueh   Lee, Chin-szu   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L21/4763 Abstract: An interconnect structure and a method of forming the interconnect structure are provided. A dielectric layer and openings therein are formed over a substrate. A conductive seed layer is formed over the top surface and along a bottom and sidewalls of the openings. A conductive fill layer is formed over the seed layer. Metal oxide on the surface of the seed layer may be reduced/removed by a surface pre-treatment. The cleaned surface is covered by depositing fill material over the seed layer without exposing the surface to oxygen. The surface treatment may include a reactive remote plasma clean using hydrogen radicals. If electroplating is used to deposit the fill layer, then the surface treatment may include soaking the substrate in the electrolyte before turning on the electroplating current. Other surface treatments may include active pre-clean (APC) using hydrogen radicals; or Ar sputtering using a metal clean version xT (MCxT) tool.
10
TWI669784B
Methods for forming contact plugs
Publication/Patent Number: TWI669784B Publication Date: 2019-08-21 Application Number: 106135929 Filing Date: 2017-10-19 Inventor: Wang, Yu Sheng   Chiu, Yi Wei   Hung, Chi Cheng   Kao, Chen Yuan   Pai, Yueh Ching   Ou, Yang Liang Yueh   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L21/768 Abstract: A method includes forming an ILD to cover a gate stack of a transistor. The ILD and the gate stack are parts of a wafer. The ILD is etched to form a contact opening, and a source/drain region of the transistor or a gate electrode in the gate stack is exposed through the contact opening. A conductive capping layer is formed to extend into the contact opening. A metal-containing material is plated on the conductive capping layer in a plating solution using electrochemical plating. The metal-containing material has a portion filling the contact opening. The plating solution has a sulfur content lower than about 100 ppm. A planarization is performed on the wafer to remove excess portions of the metal-containing material. A remaining portion of the metal-containing material and a remaining portion of the conductive capping layer in combination form a contact plug.
11
KR102030242B1
METHODS FOR FORMING CONTACT PLUGS WITH REDUCED CORROSION
Publication/Patent Number: KR102030242B1 Publication Date: 2019-10-10 Application Number: 20170121446 Filing Date: 2017-09-20 Inventor: Kao, Chen Yuan   Pai, Yueh Ching   Hung, Chi Cheng   Ou, Yang Liang Yueh   Chiu, Yi Wei   Wang, Yu Sheng   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.   IPC: H01L21/768 Abstract: A method comprises a step of forming an ILD to cover a gate stack of a transistor, wherein the ILD and gate stack are parts of a wafer. The ILD is etched to form a contact opening, and a gate electrode in a source/drain region of the transistor or the gate stack is exposed through the contact opening. A conductive cover layer is formed to extend into the contact opening, and a metal-containing material is plated on the conductive cover layer in a plating solution by using electrochemical plating, wherein the metal-containing material has a part that fills the contact opening. The plating solution has sulfur content less than about 100 ppm, and planarization is performed on the wafer to remove excess parts of the metal-containing material. In addition, residual parts of the metal-containing material and residual parts of the conductive cover layer are combined to form contact plugs.
12
US10186456B2
Methods for forming contact plugs with reduced corrosion
Publication/Patent Number: US10186456B2 Publication Date: 2019-01-22 Application Number: 15/492,113 Filing Date: 2017-04-20 Inventor: Wang, Yu-sheng   Hung, Chi-cheng   Kao, Chen-yuan   Chiu, Yi-wei   Ou yang liang yueh   Pai, Yueh-ching   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L21/768 Abstract: A method includes forming an ILD to cover a gate stack of a transistor. The ILD and the gate stack are parts of a wafer. The ILD is etched to form a contact opening, and a source/drain region of the transistor or a gate electrode in the gate stack is exposed through the contact opening. A conductive capping layer is formed to extend into the contact opening. A metal-containing material is plated on the conductive capping layer in a plating solution using electrochemical plating. The metal-containing material has a portion filling the contact opening. The plating solution has a sulfur content lower than about 100 ppm. A planarization is performed on the wafer to remove excess portions of the metal-containing material. A remaining portion of the metal-containing material and a remaining portion of the conductive capping layer in combination form a contact plug.
13
US10483165B2
Methods for forming contact plugs with reduced corrosion
Publication/Patent Number: US10483165B2 Publication Date: 2019-11-19 Application Number: 16/213,326 Filing Date: 2018-12-07 Inventor: Wang, Yu-sheng   Hung, Chi-cheng   Kao, Chen-yuan   Chiu, Yi-wei   Ou yang liang yueh   Pai, Yueh-ching   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L29/78 Abstract: A method includes forming an ILD to cover a gate stack of a transistor. The ILD and the gate stack are parts of a wafer. The ILD is etched to form a contact opening, and a source/drain region of the transistor or a gate electrode in the gate stack is exposed through the contact opening. A conductive capping layer is formed to extend into the contact opening. A metal-containing material is plated on the conductive capping layer in a plating solution using electrochemical plating. The metal-containing material has a portion filling the contact opening. The plating solution has a sulfur content lower than about 100 ppm. A planarization is performed on the wafer to remove excess portions of the metal-containing material. A remaining portion of the metal-containing material and a remaining portion of the conductive capping layer in combination form a contact plug.
14
US2019109043A1
Semiconductor Device and Method
Publication/Patent Number: US2019109043A1 Publication Date: 2019-04-11 Application Number: 16/213,868 Filing Date: 2018-12-07 Inventor: Wang, Yu-sheng   Hung, Chi-cheng   Su, Ching-hwanq   Ou yang liang yueh   Tsai, Ming-hsing   Lin, Yu-ting   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L21/768 Abstract: A method includes forming a first opening in a dielectric layer over a substrate, lining sidewalls and a bottom of the first opening with a conductive barrier layer, and depositing a seed layer over the conductive barrier layer. The method further includes treating the seed layer with a plasma process, and filling the first opening with a conductive material after the treating the seed layer.
15
US10497615B2
Semiconductor device and method
Publication/Patent Number: US10497615B2 Publication Date: 2019-12-03 Application Number: 16/213,868 Filing Date: 2018-12-07 Inventor: Wang, Yu-sheng   Hung, Chi-cheng   Su, Ching-hwanq   Ou yang liang yueh   Tsai, Ming-hsing   Lin, Yu-ting   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L21/768 Abstract: A method includes forming a first opening in a dielectric layer over a substrate, lining sidewalls and a bottom of the first opening with a conductive barrier layer, and depositing a seed layer over the conductive barrier layer. The method further includes treating the seed layer with a plasma process, and filling the first opening with a conductive material after the treating the seed layer.
16
US2019115256A1
Methods for Forming Contact Plugs with Reduced Corrosion
Publication/Patent Number: US2019115256A1 Publication Date: 2019-04-18 Application Number: 16/213,326 Filing Date: 2018-12-07 Inventor: Wang, Yu-sheng   Hung, Chi-cheng   Kao, Chen-yuan   Chiu, Yi-wei   Ou yang liang yueh   Pai, Yueh-ching   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L21/768 Abstract: A method includes forming an ILD to cover a gate stack of a transistor. The ILD and the gate stack are parts of a wafer. The ILD is etched to form a contact opening, and a source/drain region of the transistor or a gate electrode in the gate stack is exposed through the contact opening. A conductive capping layer is formed to extend into the contact opening. A metal-containing material is plated on the conductive capping layer in a plating solution using electrochemical plating. The metal-containing material has a portion filling the contact opening. The plating solution has a sulfur content lower than about 100 ppm. A planarization is performed on the wafer to remove excess portions of the metal-containing material. A remaining portion of the metal-containing material and a remaining portion of the conductive capping layer in combination form a contact plug.
17
KR20180118031A
METHODS FOR FORMING CONTACT PLUGS WITH REDUCED CORROSION
Publication/Patent Number: KR20180118031A Publication Date: 2018-10-30 Application Number: 20170121446 Filing Date: 2017-09-20 Inventor: Kao, Chen Yuan   Pai, Yueh Ching   Hung, Chi Cheng   Ou, Yang Liang Yueh   Chiu, Yi Wei   Wang, Yu Sheng   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.   IPC: H01L21/768 Abstract: A method comprises a step of forming an ILD to cover a gate stack of a transistor, wherein the ILD and gate stack are parts of a wafer. The ILD is etched to form a contact opening, and a gate electrode in a source/drain region of the transistor or the gate stack is exposed through the contact opening. A conductive cover layer is formed to extend into the contact opening, and a metal-containing material is plated on the conductive cover layer in a plating solution by using electrochemical plating, wherein the metal-containing material has a part that fills the contact opening. The plating solution has sulfur content less than about 100 ppm, and planarization is performed on the wafer to remove excess parts of the metal-containing material. In addition, residual parts of the metal-containing material and residual parts of the conductive cover layer are combined to form contact plugs.
18
TW201839911A
Methods for forming contact plugs
Publication/Patent Number: TW201839911A Publication Date: 2018-11-01 Application Number: 106135929 Filing Date: 2017-10-19 Inventor: Wang, Yu Sheng   Chiu, Yi Wei   Hung, Chi Cheng   Kao, Chen Yuan   Pai, Yueh Ching   Ou, Yang Liang Yueh   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L21/768 Abstract: A method includes forming an ILD to cover a gate stack of a transistor. The ILD and the gate stack are parts of a wafer. The ILD is etched to form a contact opening, and a source/drain region of the transistor or a gate electrode in the gate stack is exposed through the contact opening. A conductive capping layer is formed to extend into the contact opening. A metal-containing material is plated on the conductive capping layer in a plating solution using electrochemical plating. The metal-containing material has a portion filling the contact opening. The plating solution has a sulfur content lower than about 100 ppm. A planarization is performed on the wafer to remove excess portions of the metal-containing material. A remaining portion of the metal-containing material and a remaining portion of the conductive capping layer in combination form a contact plug.
19
KR20180121826A
SEMICONDUCTOR DEVICE AND METHOD
Publication/Patent Number: KR20180121826A Publication Date: 2018-11-09 Application Number: 20170166505 Filing Date: 2017-12-06 Inventor: Hung, Chi Cheng   Ou, Yang Liang Yueh   Su, Ching Hwanq   Wang, Yu Sheng   Lin, Yu Ting   Tsai, Ming Hsing   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.   IPC: H01L21/768 Abstract: A method capable of processing a small feature size includes the steps of: forming a first opening in a dielectric layer over a substrate; lining sidewalls and the bottom of the first opening with a conductive barrier layer; and depositing a seed layer over the conductive barrier layer. The method further includes: treating the seed layer with a plasma process; and filling the first opening with a conductive material after treating the seed layer.
20
US2018315647A1
Semiconductor Device and Method
Publication/Patent Number: US2018315647A1 Publication Date: 2018-11-01 Application Number: 15/583,789 Filing Date: 2017-05-01 Inventor: Wang, Yu-sheng   Hung, Chi-cheng   Su, Ching-hwanq   Ou yang liang yueh   Tsai, Ming-hsing   Lin, Yu-ting   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L21/768 Abstract: A method includes forming a first opening in a dielectric layer over a substrate, lining sidewalls and a bottom of the first opening with a conductive barrier layer, and depositing a seed layer over the conductive barrier layer. The method further includes treating the seed layer with a plasma process, and filling the first opening with a conductive material after the treating the seed layer.
Total 2 pages