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1
US2021036147A1
GATE STRUCTURE, METHOD OF FORMING THE SAME, AND SEMICONDUCTOR DEVICE HAVING THE SAME
Publication/Patent Number: US2021036147A1 Publication Date: 2021-02-04 Application Number: 16/888,846 Filing Date: 2020-05-31 Inventor: Wang, Chun-chieh   Yeh, Sheng-wei   Pai yueh ching   Yang, Chi-jen   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L29/78 Abstract: Provided are a gate structure and a method of forming the same. The gate structure includes a gate dielectric layer, a metal layer, and a cluster layer. The metal layer is disposed over the gate dielectric layer. The cluster layer is sandwiched between the metal layer and the gate dielectric layer, wherein the cluster layer at least includes an amorphous silicon layer, an amorphous carbon layer, or an amorphous germanium layer. In addition, a semiconductor device including the gate structure is provided.
2
US10964590B2
Contact metallization process
Publication/Patent Number: US10964590B2 Publication Date: 2021-03-30 Application Number: 15/967,056 Filing Date: 2018-04-30 Inventor: Chou, Tien-pei   Chang, Ken-yu   Lin, Sheng-hsuan   Pai yueh ching   Lin, Yu-ting   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L21/768 Abstract: The present disclosure describes a method to a metallization process with improved gap fill properties. The method includes forming a contact opening in an oxide, forming a barrier layer in the contact opening, forming a liner layer on the barrier layer, and forming a first metal layer on the liner layer to partially fill the contact opening. The method further includes forming a second metal layer on the first metal layer to fill the contact opening, where forming the second metal layer includes sputter depositing the second metal layer with a first radio frequency (RF) power and a direct current power, as well as reflowing the second metal layer with a second RF power.
3
US10937910B2
Semiconductor structure with source/drain multi-layer structure and method for forming the same
Publication/Patent Number: US10937910B2 Publication Date: 2021-03-02 Application Number: 16/654,175 Filing Date: 2019-10-16 Inventor: Wang, Chun-chieh   Lin, Yu-ting   Pai yueh ching   Chang, Shih-chieh   Yang, Huai-tei   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD   IPC: H01L29/78 Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure formed over a fin structure and a gate spacer formed on a sidewall surface of the gate structure. The semiconductor structure also includes a first source/drain (S/D) epitaxial layer formed in the fin structure and adjacent to the gate spacer, and a second S/D epitaxial layer formed over the first S/D epitaxial layer. A top surface of the second S/D layer is higher than a top surface of the first S/D epitaxial layer.
4
US2020043927A1
Semiconductor Device and Method
Publication/Patent Number: US2020043927A1 Publication Date: 2020-02-06 Application Number: 16/276,143 Filing Date: 2019-02-14 Inventor: Wang, Chun-chieh   Pai yueh ching   Yang, Huai-tei   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L27/092 Abstract: A semiconductor device including a cap layer and a method for forming the same are disclosed. In an embodiment, a method includes epitaxially growing a first semiconductor layer over an N-well; etching the first semiconductor layer to form a first recess; epitaxially growing a second semiconductor layer filling the first recess; etching the second semiconductor layer, the first semiconductor layer, and the N-well to form a first fin; forming a shallow trench isolation region adjacent the first fin; and forming a cap layer over the first fin, the cap layer contacting the second semiconductor layer, forming the cap layer including performing a pre-clean process to remove a native oxide from exposed surfaces of the second semiconductor layer; performing a sublimation process to produce a first precursor; and performing a deposition process wherein material from the first precursor is deposited on the second semiconductor layer to form the cap layer.
5
US10679995B2
Semiconductor device and method
Publication/Patent Number: US10679995B2 Publication Date: 2020-06-09 Application Number: 16/276,143 Filing Date: 2019-02-14 Inventor: Wang, Chun-chieh   Pai yueh ching   Yang, Huai-tei   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L29/66 Abstract: A semiconductor device including a cap layer and a method for forming the same are disclosed. In an embodiment, a method includes epitaxially growing a first semiconductor layer over an N-well; etching the first semiconductor layer to form a first recess; epitaxially growing a second semiconductor layer filling the first recess; etching the second semiconductor layer, the first semiconductor layer, and the N-well to form a first fin; forming a shallow trench isolation region adjacent the first fin; and forming a cap layer over the first fin, the cap layer contacting the second semiconductor layer, forming the cap layer including performing a pre-clean process to remove a native oxide from exposed surfaces of the second semiconductor layer; performing a sublimation process to produce a first precursor; and performing a deposition process wherein material from the first precursor is deposited on the second semiconductor layer to form the cap layer.
6
US2020303378A1
Semiconductor Device and Method
Publication/Patent Number: US2020303378A1 Publication Date: 2020-09-24 Application Number: 16/895,035 Filing Date: 2020-06-08 Inventor: Wang, Chun-chieh   Pai yueh ching   Yang, Huai-tei   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L27/092 Abstract: A semiconductor device including a cap layer and a method for forming the same are disclosed. In an embodiment, a method includes epitaxially growing a first semiconductor layer over an N-well; etching the first semiconductor layer to form a first recess; epitaxially growing a second semiconductor layer filling the first recess; etching the second semiconductor layer, the first semiconductor layer, and the N-well to form a first fin; forming a shallow trench isolation region adjacent the first fin; and forming a cap layer over the first fin, the cap layer contacting the second semiconductor layer, forming the cap layer including performing a pre-clean process to remove a native oxide from exposed surfaces of the second semiconductor layer; performing a sublimation process to produce a first precursor; and performing a deposition process wherein material from the first precursor is deposited on the second semiconductor layer to form the cap layer.
7
US202043927A1
Semiconductor Device and Method
Publication/Patent Number: US202043927A1 Publication Date: 2020-02-06 Application Number: 20/191,627 Filing Date: 2019-02-14 Inventor: Wang, Chun-chieh   Yang, Huai-tei   Pai yueh ching   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L29/10 Abstract: A semiconductor device including a cap layer and a method for forming the same are disclosed. In an embodiment, a method includes epitaxially growing a first semiconductor layer over an N-well; etching the first semiconductor layer to form a first recess; epitaxially growing a second semiconductor layer filling the first recess; etching the second semiconductor layer, the first semiconductor layer, and the N-well to form a first fin; forming a shallow trench isolation region adjacent the first fin; and forming a cap layer over the first fin, the cap layer contacting the second semiconductor layer, forming the cap layer including performing a pre-clean process to remove a native oxide from exposed surfaces of the second semiconductor layer; performing a sublimation process to produce a first precursor; and performing a deposition process wherein material from the first precursor is deposited on the second semiconductor layer to form the cap layer.
8
US2020126797A1
Silicon Intermixing Layer for Blocking Diffusion
Publication/Patent Number: US2020126797A1 Publication Date: 2020-04-23 Application Number: 16/290,118 Filing Date: 2019-03-01 Inventor: Wang, Chun-chieh   Huang, Kuo-jung   Pai yueh ching   Yang, Huai-tei   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L21/28 Abstract: A method of forming an integrated circuit structure includes forming a gate dielectric on a wafer, forming a work function layer over the gate dielectric, depositing a capping layer over the work function layer, soaking the capping layer in a silicon-containing gas to form a silicon-containing layer, forming a blocking layer after the silicon-containing layer is formed, and forming a metal-filling region over the blocking layer.
9
US10629700B1
High-K metal gate process and device
Publication/Patent Number: US10629700B1 Publication Date: 2020-04-21 Application Number: 16/145,382 Filing Date: 2018-09-28 Inventor: Liao, Chien-shun   Yang, Huai-tei   Chun-chieh, Wang   Pai yueh ching   Wu, Chun-i   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L21/28 Abstract: An embodiment is a method of semiconductor processing. The method includes depositing a high-k gate dielectric layer over a semiconductor fin. A barrier layer is deposited over the high-k gate dielectric layer. A silicon passivation layer is deposited over the barrier layer. A nitrogen treatment is performed on the silicon passivation layer. A capping layer is deposited over the silicon passivation layer. The capping layer is annealed.
10
US2020052126A1
SEMICONDUCTOR STRUCTURE WITH SOURCE/DRAIN MULTI-LAYER STRUCTURE AND METHOD FOR FORMING THE SAME
Publication/Patent Number: US2020052126A1 Publication Date: 2020-02-13 Application Number: 16/654,175 Filing Date: 2019-10-16 Inventor: Wang, Chun-chieh   Lin, Yu-ting   Pai yueh ching   Chang, Shih-chieh   Yang, Huai-tei   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L29/78 Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure formed over a fin structure and a gate spacer formed on a sidewall surface of the gate structure. The semiconductor structure also includes a first source/drain (S/D) epitaxial layer formed in the fin structure and adjacent to the gate spacer, and a second S/D epitaxial layer formed over the first S/D epitaxial layer. A top surface of the second S/D layer is higher than a top surface of the first S/D epitaxial layer.
11
US202052126A1
SEMICONDUCTOR STRUCTURE WITH SOURCE/DRAIN MULTI-LAYER STRUCTURE AND METHOD FOR FORMING THE SAME
Publication/Patent Number: US202052126A1 Publication Date: 2020-02-13 Application Number: 20/191,665 Filing Date: 2019-10-16 Inventor: Wang, Chun-chieh   Yang, Huai-tei   Lin, Yu-ting   Chang, Shih-chieh   Pai yueh ching   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L29/78 Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure formed over a fin structure and a gate spacer formed on a sidewall surface of the gate structure. The semiconductor structure also includes a first source/drain (S/D) epitaxial layer formed in the fin structure and adjacent to the gate spacer, and a second S/D epitaxial layer formed over the first S/D epitaxial layer. A top surface of the second S/D layer is higher than a top surface of the first S/D epitaxial layer.
12
US2020105532A1
High-K Metal Gate Process and Device
Publication/Patent Number: US2020105532A1 Publication Date: 2020-04-02 Application Number: 16/145,382 Filing Date: 2018-09-28 Inventor: Liao, Chien-shun   Yang, Huai-tei   Wang, Chun-chieh   Pai yueh ching   Wu, Chun-i   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L21/28 Abstract: An embodiment is a method of semiconductor processing. The method includes depositing a high-k gate dielectric layer over a semiconductor fin. A barrier layer is deposited over the high-k gate dielectric layer. A silicon passivation layer is deposited over the barrier layer. A nitrogen treatment is performed on the silicon passivation layer. A capping layer is deposited over the silicon passivation layer. The capping layer is annealed.
13
US10752995B2
Material delivery system and method
Publication/Patent Number: US10752995B2 Publication Date: 2020-08-25 Application Number: 15/442,467 Filing Date: 2017-02-24 Inventor: Liu, Ke-chih   Tsai, Chia-ming   Chen, Yen-yu   Pai yueh ching   Chang, Yu-min   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: C23C16/52 Abstract: A method includes applying a first amount of heat to a vapor region of a precursor canister, measuring an indication of saturated vapor pressure within the vapor region during the applying the first amount of heat, and applying a second amount of heat to the vapor region of the precursor canister, the second amount of heat being adjusted from the first amount of heat based on the indication of saturated vapor pressure.
14
US2020251574A1
High-K Metal Gate Process and Device
Publication/Patent Number: US2020251574A1 Publication Date: 2020-08-06 Application Number: 16/852,819 Filing Date: 2020-04-20 Inventor: Liao, Chien-shun   Yang, Huai-tei   Wang, Chun-chieh   Pai yueh ching   Wu, Chun-i   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L29/66 Abstract: An embodiment is a method of semiconductor processing. The method includes depositing a high-k gate dielectric layer over a semiconductor fin. A barrier layer is deposited over the high-k gate dielectric layer. A silicon passivation layer is deposited over the barrier layer. A nitrogen treatment is performed on the silicon passivation layer. A capping layer is deposited over the silicon passivation layer. The capping layer is annealed.
15
US2020075407A1
Methods for Forming Contact Plugs with Reduced Corrosion
Publication/Patent Number: US2020075407A1 Publication Date: 2020-03-05 Application Number: 16/678,410 Filing Date: 2019-11-08 Inventor: Wang, Yu-sheng   Hung, Chi-cheng   Kao, Chen-yuan   Chiu, Yi-wei   Ou, Yang Liang-yueh   Pai yueh ching   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L21/768 Abstract: A method includes forming an ILD to cover a gate stack of a transistor. The ILD and the gate stack are parts of a wafer. The ILD is etched to form a contact opening, and a source/drain region of the transistor or a gate electrode in the gate stack is exposed through the contact opening. A conductive capping layer is formed to extend into the contact opening. A metal-containing material is plated on the conductive capping layer in a plating solution using electrochemical plating. The metal-containing material has a portion filling the contact opening. The plating solution has a sulfur content lower than about 100 ppm. A planarization is performed on the wafer to remove excess portions of the metal-containing material. A remaining portion of the metal-containing material and a remaining portion of the conductive capping layer in combination form a contact plug.
16
US2020135471A1
FORMATION AND IN-SITU ETCHING PROCESSES FOR METAL LAYERS
Publication/Patent Number: US2020135471A1 Publication Date: 2020-04-30 Application Number: 16/729,725 Filing Date: 2019-12-30 Inventor: Lin, Po-yu   Chou, Chi-yu   Lee, Hsien-ming   Yang, Huai-tei   Wang, Chun-chieh   Pai yueh ching   Yang, Chi-jen   Tang, Tsung-ta   Wang, Yi-ting   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L21/28 Abstract: The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.
17
US10872769B2
Formation and in-situ etching processes for metal layers
Publication/Patent Number: US10872769B2 Publication Date: 2020-12-22 Application Number: 16/729,725 Filing Date: 2019-12-30 Inventor: Lin, Po-yu   Chou, Chi-yu   Lee, Hsien-ming   Yang, Huai-tei   Wang, Chun-chieh   Pai yueh ching   Yang, Chi-jen   Tang, Tsung-ta   Wang, Yi-ting   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L21/28 Abstract: The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.
18
US10535523B1
Formation and in-situ etching processes for metal layers
Publication/Patent Number: US10535523B1 Publication Date: 2020-01-14 Application Number: 16/117,234 Filing Date: 2018-08-30 Inventor: Lin, Po-yu   Chou, Chi-yu   Lee, Hsien-ming   Yang, Huai-tei   Wang, Chun-chieh   Pai yueh ching   Yang, Chi-jen   Tang, Tsung-ta   Wang, Yi-ting   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L21/28 Abstract: The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.
19
TWI669784B
Methods for forming contact plugs
Publication/Patent Number: TWI669784B Publication Date: 2019-08-21 Application Number: 106135929 Filing Date: 2017-10-19 Inventor: Wang, Yu Sheng   Chiu, Yi Wei   Hung, Chi Cheng   Kao, Chen Yuan   Pai, Yueh Ching   Ou, Yang Liang Yueh   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L21/768 Abstract: A method includes forming an ILD to cover a gate stack of a transistor. The ILD and the gate stack are parts of a wafer. The ILD is etched to form a contact opening, and a source/drain region of the transistor or a gate electrode in the gate stack is exposed through the contact opening. A conductive capping layer is formed to extend into the contact opening. A metal-containing material is plated on the conductive capping layer in a plating solution using electrochemical plating. The metal-containing material has a portion filling the contact opening. The plating solution has a sulfur content lower than about 100 ppm. A planarization is performed on the wafer to remove excess portions of the metal-containing material. A remaining portion of the metal-containing material and a remaining portion of the conductive capping layer in combination form a contact plug.
20
KR102030242B1
METHODS FOR FORMING CONTACT PLUGS WITH REDUCED CORROSION
Publication/Patent Number: KR102030242B1 Publication Date: 2019-10-10 Application Number: 20170121446 Filing Date: 2017-09-20 Inventor: Kao, Chen Yuan   Pai, Yueh Ching   Hung, Chi Cheng   Ou, Yang Liang Yueh   Chiu, Yi Wei   Wang, Yu Sheng   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.   IPC: H01L21/768 Abstract: A method comprises a step of forming an ILD to cover a gate stack of a transistor, wherein the ILD and gate stack are parts of a wafer. The ILD is etched to form a contact opening, and a gate electrode in a source/drain region of the transistor or the gate stack is exposed through the contact opening. A conductive cover layer is formed to extend into the contact opening, and a metal-containing material is plated on the conductive cover layer in a plating solution by using electrochemical plating, wherein the metal-containing material has a part that fills the contact opening. The plating solution has sulfur content less than about 100 ppm, and planarization is performed on the wafer to remove excess parts of the metal-containing material. In addition, residual parts of the metal-containing material and residual parts of the conductive cover layer are combined to form contact plugs.
Total 2 pages