Country
Full text data for US,EP,CN
Type
Legal Validity
Legal Status
Filing Date
Publication Date
Inventor
Assignee
Click to expand
IPC(Section)
IPC(Class)
IPC(Subclass)
IPC(Group)
IPC(Subgroup)
Agent
Agency
Claims Number
Figures Number
Citation Number of Times
Assignee Number
No. Publication Number Title Publication/Patent Number Publication/Patent Number Publication Date Publication Date
Application Number Application Number Filing Date Filing Date
Inventor Inventor Assignee Assignee IPC IPC
1
US10566371B2
Bump structures for interconnecting focal plane arrays
Publication/Patent Number: US10566371B2 Publication Date: 2020-02-18 Application Number: 16/126,314 Filing Date: 2018-09-10 Inventor: Paik namwoong   Huang, Wei   Assignee: Sensors Unlimited, Inc.   IPC: H01L23/48 Abstract: A method of forming bump structures for interconnecting components includes dry etching a layer of insulating material to create a pattern for bump structures. A seed layer is deposited on the insulating material over the pattern. The seed layer is patterned with a photo resist material. The method also includes forming bump structures over the seed layer and the photo resist material with a plating material to form bump structures in the pattern, wherein the bump structures are isolated from one another.
2
US10879204B2
Bump structures for high density flip chip interconnection
Publication/Patent Number: US10879204B2 Publication Date: 2020-12-29 Application Number: 16/838,322 Filing Date: 2020-04-02 Inventor: Zhang, Wei   Huang, Wei   Lund, Joshua   Paik namwoong   Assignee: Sensors Unlimited, Inc.   IPC: H01L23/00 Abstract: A method of forming bump structures for interconnecting components includes applying an insulating layer over a device substrate, coating the insulating layer with a dielectric material layer, forming a pattern with photolithography on the dielectric material layer, etching the dielectric material layer to transfer the pattern to the insulating layer, etching the insulating layer to form pockets in the insulating layer following the pattern, applying photolithography to and etching the dielectric material layer to reduce overhang of the dielectric material layer relative to the insulating layer, removing material from top and side walls of the pockets in the insulating layer, and depositing electrically conductive bump material in the pattern so a respective bump is formed in each pocket.
3
US2020227370A1
BUMP STRUCTURES FOR HIGH DENSITY FLIP CHIP INTERCONNECTION
Publication/Patent Number: US2020227370A1 Publication Date: 2020-07-16 Application Number: 16/838,322 Filing Date: 2020-04-02 Inventor: Zhang, Wei   Huang, Wei   Lund, Joshua   Paik namwoong   Assignee: Sensors Unlimited, Inc.   IPC: H01L23/00 Abstract: A method of forming bump structures for interconnecting components includes applying an insulating layer over a device substrate, coating the insulating layer with a dielectric material layer, forming a pattern with photolithography on the dielectric material layer, etching the dielectric material layer to transfer the pattern to the insulating layer, etching the insulating layer to form pockets in the insulating layer following the pattern, applying photolithography to and etching the dielectric material layer to reduce overhang of the dielectric material layer relative to the insulating layer, removing material from top and side walls of the pockets in the insulating layer, and depositing electrically conductive bump material in the pattern so a respective bump is formed in each pocket.
4
US10622324B2
Bump structures for high density flip chip interconnection
Publication/Patent Number: US10622324B2 Publication Date: 2020-04-14 Application Number: 15/891,889 Filing Date: 2018-02-08 Inventor: Zhang, Wei   Huang, Wei   Lund, Joshua   Paik namwoong   Assignee: Sensors Unlimited, Inc.   IPC: H01L23/00 Abstract: A method of forming bump structures for interconnecting components includes applying an insulating layer over a device substrate, coating the insulating layer with a dielectric material layer, forming a pattern with photolithography on the dielectric material layer, etching the dielectric material layer to transfer the pattern to the insulating layer, etching the insulating layer to form pockets in the insulating layer following the pattern, applying photolithography to and etching the dielectric material layer to reduce overhang of the dielectric material layer relative to the insulating layer, removing material from top and side walls of the pockets in the insulating layer, and depositing electrically conductive bump material in the pattern so a respective bump is formed in each pocket.
5
US2020052012A1
MESA TRENCH ETCH WITH STACKED SIDEWALL PASSIVATION
Publication/Patent Number: US2020052012A1 Publication Date: 2020-02-13 Application Number: 16/057,191 Filing Date: 2018-08-07 Inventor: Zhang, Wei   Evans, Michael J.   Malchow, Douglas Stewart   Bereznycky, Paul L.   Paik namwoong   Assignee: Sensors Unlimited, Inc.   IPC: H01L27/146 Abstract: A method of forming an array of photodiodes includes forming a cap layer on a surface of an absorption layer. The method includes forming a plurality of spaced apart pixel diffusion areas in the cap layer. The method includes forming a mesa trench with opposed sidewalls through the cap layer, wherein the mesa trench surrounds each of the pixel diffusion areas separating the pixel diffusion areas from one another. The method includes forming a sidewall passivation layer over the sidewalls of the mesa trench and removing a portion of the sidewall passivation layer to expose a respective contact electrically connected to each of the pixel diffusion areas, but leaving the sidewalls of the mesa trench covered with the sidewall passivation layer wherein the contact is open and uncovered for electrical connection.
6
US202052012A1
MESA TRENCH ETCH WITH STACKED SIDEWALL PASSIVATION
Publication/Patent Number: US202052012A1 Publication Date: 2020-02-13 Application Number: 20/181,605 Filing Date: 2018-08-07 Inventor: Zhang, Wei   Malchow, Douglas Stewart   Evans, Michael J.   Paik namwoong   Bereznycky, Paul L.   Assignee: Sensors Unlimited, Inc.   IPC: H01L27/146 Abstract: A method of forming an array of photodiodes includes forming a cap layer on a surface of an absorption layer. The method includes forming a plurality of spaced apart pixel diffusion areas in the cap layer. The method includes forming a mesa trench with opposed sidewalls through the cap layer, wherein the mesa trench surrounds each of the pixel diffusion areas separating the pixel diffusion areas from one another. The method includes forming a sidewall passivation layer over the sidewalls of the mesa trench and removing a portion of the sidewall passivation layer to expose a respective contact electrically connected to each of the pixel diffusion areas, but leaving the sidewalls of the mesa trench covered with the sidewall passivation layer wherein the contact is open and uncovered for electrical connection.
7
EP3608962A1
MESA TRENCH ETCH WITH STACKED SIDEWALL PASSIVATION
Publication/Patent Number: EP3608962A1 Publication Date: 2020-02-12 Application Number: 19189836.0 Filing Date: 2019-08-02 Inventor: Zhang, Wei   Evans, Michael J.   Malchow, Douglas Stewart   Bereznycky, Paul L.   Paik namwoong   Assignee: Sensors Unlimited, Inc.   IPC: H01L27/146 Abstract: A method of forming an array of photodiodes includes forming a cap layer (102) on a surface (104) of an absorption layer (106). The method includes forming a plurality of spaced apart pixel diffusion areas (116) in the cap layer (102). The method includes forming a mesa trench (124) with opposed sidewalls (126) through the cap layer (102), wherein the mesa trench (124) surrounds each of the pixel diffusion areas (116) separating the pixel diffusion areas (116) from one another. The method includes forming a sidewall passivation layer (128) over the sidewalls (126) of the mesa trench (124) and removing a portion of the sidewall passivation layer (128) to expose a respective contact (118) electrically connected to each of the pixel diffusion areas (116), but leaving the sidewalls (126) of the mesa trench covered with the sidewall passivation layer (128) wherein the contact (118) is open and uncovered for electrical connection.
8
US2020312900A1
INTERCONNECT BUMP STRUCTURES FOR PHOTO DETECTORS
Publication/Patent Number: US2020312900A1 Publication Date: 2020-10-01 Application Number: 16/902,318 Filing Date: 2020-06-16 Inventor: Zhang, Wei   Malchow, Douglas Stewart   Evans, Michael J.   Huang, Wei   Bereznycky, Paul L.   Paik namwoong   Assignee: Sensors Unlimited, Inc.   IPC: H01L27/146 Abstract: A method of assembling a photodetector assembly includes depositing bumps on a read out integrated circuit (ROIC) without depositing bumps on a photodiode array (PDA). The method includes assembling the PDA and ROIC together wherein each bump electrically interconnects the ROIC with a respective contact of the PDA. A photodetector assembly includes a PDA. A ROIC is assembled to the PDA, wherein the ROIC is electrically interconnected with the PDA through a plurality of electrically conductive bumps. Each bump is confined within a respective pocket between the ROIC and a respective contact of the PDA. The disclosed methods can enable focal plane array manufacturers to achieve low-cost production of ultra-fine pitch, large format imaging arrays.
9
EP3624191A1
INTERCONNECT BUMP STRUCTURES FOR PHOTO DETECTORS
Publication/Patent Number: EP3624191A1 Publication Date: 2020-03-18 Application Number: 19197065.6 Filing Date: 2019-09-12 Inventor: Zhang, Wei   Malchow, Douglas Stewart   Evans, Michael J.   Huang, Wei   Bereznycky, Paul L.   Paik namwoong   Assignee: Sensors Unlimited, Inc.   IPC: H01L27/146 Abstract: A method of assembling a photodetector assembly includes depositing bumps on a read out integrated circuit (ROIC) without depositing bumps on a photodiode array (PDA). The method includes assembling the PDA and ROIC together wherein each bump electrically interconnects the ROIC with a respective contact of the PDA. A photodetector assembly includes a PDA. A ROIC is assembled to the PDA, wherein the ROIC is electrically interconnected with the PDA through a plurality of electrically conductive bumps. Each bump is confined within a respective pocket between the ROIC and a respective contact of the PDA. The disclosed methods can enable focal plane array manufacturers to achieve low-cost production of ultra-fine pitch, large format imaging arrays.
10
US10727267B2
Interconnect bump structures for photo detectors
Publication/Patent Number: US10727267B2 Publication Date: 2020-07-28 Application Number: 16/129,402 Filing Date: 2018-09-12 Inventor: Zhang, Wei   Malchow, Douglas Stewart   Evans, Michael J.   Huang, Wei   Bereznycky, Paul L.   Paik namwoong   Assignee: Sensors Unlimited, Inc.   IPC: H01L27/146 Abstract: A method of assembling a photodetector assembly includes depositing bumps on a read out integrated circuit (ROIC) without depositing bumps on a photodiode array (PDA). The method includes assembling the PDA and ROIC together wherein each bump electrically interconnects the ROIC with a respective contact of the PDA. A photodetector assembly includes a PDA. A ROIC is assembled to the PDA, wherein the ROIC is electrically interconnected with the PDA through a plurality of electrically conductive bumps. Each bump is confined within a respective pocket between the ROIC and a respective contact of the PDA. The disclosed methods can enable focal plane array manufacturers to achieve low-cost production of ultra-fine pitch, large format imaging arrays.
11
US2020083272A1
INTERCONNECT BUMP STRUCTURES FOR PHOTO DETECTORS
Publication/Patent Number: US2020083272A1 Publication Date: 2020-03-12 Application Number: 16/129,402 Filing Date: 2018-09-12 Inventor: Zhang, Wei   Malchow, Douglas Stewart   Evans, Michael J.   Huang, Wei   Bereznycky, Paul L.   Paik namwoong   Assignee: Sensors Unlimited, Inc.   IPC: H01L27/146 Abstract: A method of assembling a photodetector assembly includes depositing bumps on a read out integrated circuit (ROIC) without depositing bumps on a photodiode array (PDA). The method includes assembling the PDA and ROIC together wherein each bump electrically interconnects the ROIC with a respective contact of the PDA. A photodetector assembly includes a PDA. A ROIC is assembled to the PDA, wherein the ROIC is electrically interconnected with the PDA through a plurality of electrically conductive bumps. Each bump is confined within a respective pocket between the ROIC and a respective contact of the PDA. The disclosed methods can enable focal plane array manufacturers to achieve low-cost production of ultra-fine pitch, large format imaging arrays.
12
US201906409A1
BUMP STRUCTURES FOR INTERCONNECTING FOCAL PLANE ARRAYS
Publication/Patent Number: US201906409A1 Publication Date: 2019-01-03 Application Number: 20/181,612 Filing Date: 2018-09-10 Inventor: Paik namwoong   Huang, Wei   Assignee: Sensors Unlimited, Inc.   IPC: H01L27/146 Abstract: A method of forming bump structures for interconnecting components includes dry etching a layer of insulating material to create a pattern for bump structures. A seed layer is deposited on the insulating material over the pattern. The seed layer is patterned with a photo resist material. The method also includes forming bump structures over the seed layer and the photo resist material with a plating material to form bump structures in the pattern, wherein the bump structures are isolated from one another.
13
US2019006409A1
BUMP STRUCTURES FOR INTERCONNECTING FOCAL PLANE ARRAYS
Publication/Patent Number: US2019006409A1 Publication Date: 2019-01-03 Application Number: 16/126,314 Filing Date: 2018-09-10 Inventor: Paik namwoong   Huang, Wei   Assignee: Sensors Unlimited, Inc.   IPC: H01L27/146 Abstract: A method of forming bump structures for interconnecting components includes dry etching a layer of insulating material to create a pattern for bump structures. A seed layer is deposited on the insulating material over the pattern. The seed layer is patterned with a photo resist material. The method also includes forming bump structures over the seed layer and the photo resist material with a plating material to form bump structures in the pattern, wherein the bump structures are isolated from one another.
14
US2019244924A1
BUMP STRUCTURES FOR HIGH DENSITY FLIP CHIP INTERCONNECTION
Publication/Patent Number: US2019244924A1 Publication Date: 2019-08-08 Application Number: 15/891,889 Filing Date: 2018-02-08 Inventor: Paik namwoong   Lund, Joshua   Huang, Wei   Zhang, Wei   Assignee: Sensors Unlimited, Inc.   IPC: H01L27/146 Abstract: A method of forming bump structures for interconnecting components includes applying an insulating layer over a device substrate, coating the insulating layer with a dielectric material layer, forming a pattern with photolithography on the dielectric material layer, etching the dielectric material layer to transfer the pattern to the insulating layer, etching the insulating layer to form pockets in the insulating layer following the pattern, applying photolithography to and etching the dielectric material layer to reduce overhang of the dielectric material layer relative to the insulating layer, removing material from top and side walls of the pockets in the insulating layer, and depositing electrically conductive bump material in the pattern so a respective bump is formed in each pocket.
15
US10468437B2
Mesas and implants in two-dimensional arrays
Publication/Patent Number: US10468437B2 Publication Date: 2019-11-05 Application Number: 15/935,080 Filing Date: 2018-03-26 Inventor: Huang, Wei   Zhang, Wei   Lund, Joshua   Paik namwoong   Assignee: Sensors Unlimited, Inc.   IPC: H01L21/02 Abstract: A photodiode includes an absorption layer. A cap layer is disposed on a surface of the absorption layer. A pixel diffusion area within the cap layer extends beyond the surface of the absorption layer and into the absorption layer to receive a charge generated from photons therefrom. A mesa trench is defined through the cap layer surrounding the pixel diffusion area, wherein the mesa trench defines a floor at the surface of the absorption layer and opposed sidewalls extending away from the surface of the absorption layer. An implant is aligned with the mesa trench and extends from the floor of the mesa trench through the absorption layer surrounding a portion of the absorption layer proximate the pixel diffusion area.
16
US2019296058A1
MESAS AND IMPLANTS IN TWO-DIMENSIONAL ARRAYS
Publication/Patent Number: US2019296058A1 Publication Date: 2019-09-26 Application Number: 15/935,080 Filing Date: 2018-03-26 Inventor: Huang, Wei   Zhang, Wei   Lund, Joshua   Paik namwoong   Assignee: Sensors Unlimited, Inc.   IPC: H01L27/144 Abstract: A photodiode includes an absorption layer. A cap layer is disposed on a surface of the absorption layer. A pixel diffusion area within the cap layer extends beyond the surface of the absorption layer and into the absorption layer to receive a charge generated from photons therefrom. A mesa trench is defined through the cap layer surrounding the pixel diffusion area, wherein the mesa trench defines a floor at the surface of the absorption layer and opposed sidewalls extending away from the surface of the absorption layer. An implant is aligned with the mesa trench and extends from the floor of the mesa trench through the absorption layer surrounding a portion of the absorption layer proximate the pixel diffusion area.
17
EP3306652A3
BUMP STRUCTURES FOR INTERCONNECTING FOCAL PLANE ARRAYS
Publication/Patent Number: EP3306652A3 Publication Date: 2018-04-25 Application Number: 17195798.8 Filing Date: 2017-10-10 Inventor: Paik namwoong   Huang, Wei   Assignee: Sensors Unlimited, Inc.   IPC: H01L21/60 Abstract: A method of forming bump structures (116) for interconnecting components includes dry etching a layer of insulating material (102) to create a pattern for bump structures. A seed layer (112) is deposited on the insulating material (102) over the pattern. The seed layer (112) is patterned with a photo resist material (114). The method also includes forming bump structures over the seed layer (112) and the photo resist material (114) with a plating material to form bump structures (116) in the pattern, wherein the bump structures are isolated from one another.
18
US2018102391A1
BUMP STRUCTURES FOR INTERCONNECTING FOCAL PLANE ARRAYS
Publication/Patent Number: US2018102391A1 Publication Date: 2018-04-12 Application Number: 15/289,627 Filing Date: 2016-10-10 Inventor: Huang, Wei   Paik namwoong   Assignee: Sensors Unlimited, Inc.   IPC: H01L27/146 Abstract: A method of forming bump structures for interconnecting components includes dry etching a layer of insulating material to create a pattern for bump structures. A seed layer is deposited on the insulating material over the pattern. The seed layer is patterned with a photo resist material. The method also includes forming bump structures over the seed layer and the photo resist material with a plating material to form bump structures in the pattern, wherein the bump structures are isolated from one another.
19
US10096639B2
Bump structures for interconnecting focal plane arrays
Publication/Patent Number: US10096639B2 Publication Date: 2018-10-09 Application Number: 15/289,627 Filing Date: 2016-10-10 Inventor: Paik namwoong   Huang, Wei   Assignee: Sensors Unlimited, Inc.   IPC: H01L23/48 Abstract: A method of forming bump structures for interconnecting components includes dry etching a layer of insulating material to create a pattern for bump structures. A seed layer is deposited on the insulating material over the pattern. The seed layer is patterned with a photo resist material. The method also includes forming bump structures over the seed layer and the photo resist material with a plating material to form bump structures in the pattern, wherein the bump structures are isolated from one another.
20
EP2294243A1
DEPOSITION METHOD
Publication/Patent Number: EP2294243A1 Publication Date: 2011-03-16 Application Number: 09750258.7 Filing Date: 2009-05-22 Inventor: Paik namwoong   Joerg, Jeffrey   Assignee: NXP B.V.   IPC: C23C16/44