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1 | US2021028360A1 |
SEMICONDUCTOR DEVICE INCLUDING A DATA STORAGE MATERIAL PATTERN
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Publication/Patent Number: US2021028360A1 | Publication Date: 2021-01-28 | Application Number: 16/807,245 | Filing Date: 2020-03-03 | Inventor： Kim, Youngtak Park, Sangjine Lee, Wonjun Seo, Hyeyeong Shin, Jaeuk | Assignee: SAMSUNG ELECTRONICS CO., LTD. | IPC: H01L45/00 | Abstract: A semiconductor device, includes: a first conductive structure on a substrate; a second conductive structure on the first conductive structure; and a first memory cell structure between the first conductive structure and the second conductive structure, wherein the first memory cell structure includes: a switching material pattern on the first conductive structure; a data storage material pattern on the switching material pattern; and an upper conductive pattern on the data storage material pattern, wherein a first width of a lower region of the data storage material pattern is less than a first width of the switching material pattern, and wherein a first width of the upper conductive pattern is less than a width of an upper region of the data storage material pattern. | |||
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2 | US202012375A1 |
DISPLAY APPARATUS INCLUDING A TOUCH DRIVING CIRCUIT
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Publication/Patent Number: US202012375A1 | Publication Date: 2020-01-09 | Application Number: 20/191,650 | Filing Date: 2019-07-05 | Inventor： Jeong, Deog-kyoon Park, Sangjine Oh, Jonghyun Park, Youngmin Park, Jiheon Park, Sanghune | Assignee: Samsung Display Co., Ltd. Seoul National University, R&DB Foundation | IPC: G06F3/041 | Abstract: A display apparatus includes a display panel, a touch sensing unit, and a touch driving circuit. The touch sensing unit includes a transmission touch line. The touch driving circuit provides a touch driving signal to the transmission touch line. The touch driving circuit may include a switch group and a control switch group. The switch group may include a plurality of switch devices, each of which has one end connected to the transmission touch line. The control switch group may be connected to the other end of at least a portion of the switch devices, include a plurality of control switch devices and a capacitor device, and receive a driving voltage and a ground voltage. The touch driving signal has N voltage levels, where N is a natural number of 3 or more. | |||
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3 | US2020012375A1 |
DISPLAY APPARATUS INCLUDING A TOUCH DRIVING CIRCUIT
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Publication/Patent Number: US2020012375A1 | Publication Date: 2020-01-09 | Application Number: 16/503,741 | Filing Date: 2019-07-05 | Inventor： Jeong, Deog-kyoon Park, Youngmin Park, Sangjine Park, Jiheon Oh, Jonghyun Park, Sanghune | Assignee: SEOUL NATIONAL UNIVERSITY, R&DB FOUNDATION | IPC: G06F3/041 | Abstract: A display apparatus includes a display panel, a touch sensing unit, and a touch driving circuit. The touch sensing unit includes a transmission touch line. The touch driving circuit provides a touch driving signal to the transmission touch line. The touch driving circuit may include a switch group and a control switch group. The switch group may include a plurality of switch devices, each of which has one end connected to the transmission touch line. The control switch group may be connected to the other end of at least a portion of the switch devices, include a plurality of control switch devices and a capacitor device, and receive a driving voltage and a ground voltage. The touch driving signal has N voltage levels, where N is a natural number of 3 or more. | |||
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4 | US2020388484A1 |
WAFER CLEANING APPARATUS BASED ON LIGHT IRRADIATION AND WAFER CLEANING SYSTEM INCLUDING THE SAME
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Publication/Patent Number: US2020388484A1 | Publication Date: 2020-12-10 | Application Number: 16/744,667 | Filing Date: 2020-01-16 | Inventor： Cho, Byungkwon Park, Sangjine Ko, Yongsun Jeon, Seulgee Jeong, Jihoon Hong, Seongsik | Assignee: Samsung Electronics Co., Ltd. | IPC: H01L21/02 | Abstract: Provided are a wafer cleaning apparatus based on light irradiation capable of effectively cleaning residue on a wafer without damaging the wafer, and a wafer cleaning system including the cleaning apparatus. The wafer cleaning apparatus is configured to clean residue on the wafer by light irradiation and includes: a light irradiation unit configured to irradiate light onto the wafer during the light irradiation; a wafer processing unit configured accommodate the wafer and to control a position of the wafer such that the light is irradiated onto the wafer during the light irradiation; and a cooling unit configured to cool the wafer after the light irradiation has been completed. The light irradiation unit, the wafer processing unit, and the cooling unit are sequentially arranged in a vertical structure with the light irradiation unit above the wafer processing unit and the wafer processing unit above the cooling unit. | |||
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5 | US2020365537A1 |
SEMICONDUCTOR DEVICES HAVING LANDING PADS
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Publication/Patent Number: US2020365537A1 | Publication Date: 2020-11-19 | Application Number: 16/674,056 | Filing Date: 2019-11-05 | Inventor： Choi, Bowo Kim, Youngtak Park, Sangjine Kim, Suji Shin, Jaeuk Lee, Hyunjung Cheon, Jihun | Assignee: Samsung Electronics Co., Ltd. | IPC: H01L23/00 | Abstract: A semiconductor device includes a landing pad, a first insulating pattern in contact with a lower portion of a side surface of the landing pad, a pad oxide layer having a lateral portion disposed on a portion of an upper surface of the landing pad and a vertical portion in contact with an upper portion of the side surface of the landing pad, a second insulating pattern in contact with an upper surface of the first insulating pattern and covering the first insulating pattern and the pad oxide layer, and a lower electrode that vertically passes through the second insulating pattern and is in contact with a portion of the upper surface and an upper portion of a side surface of the landing pad. | |||
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6 | US10714472B2 |
Semiconductor devices and methods of fabricating the same
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Publication/Patent Number: US10714472B2 | Publication Date: 2020-07-14 | Application Number: 15/676,317 | Filing Date: 2017-08-14 | Inventor： Kwon, Kee Sang Yoon, Boun Park, Sangjine Song, Myunggeun Ko, Ki-hyung Yun, Jiwon | Assignee: Samsung Electronics Co., Ltd. | IPC: H01L29/51 | Abstract: Semiconductor devices may include a substrate, gate electrodes on the substrate, and source/drain regions at both sides of each of the gate electrodes. Each of the gate electrodes may include a gate insulating pattern on the substrate, a lower work-function electrode pattern that is on the gate insulating pattern and has a recessed upper surface, and an upper work-function electrode pattern that conformally extends on the recessed upper surface of the lower work function electrode pattern. Topmost surfaces of the lower work-function electrode patterns may be disposed at an equal level, and the upper work-function electrode patterns may have different thicknesses from each other. | |||
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7 | US2020227253A1 |
SUPERCRITICAL DRYING APPARATUS AND METHOD OF DRYING SUBSTRATE USING THE SAME
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Publication/Patent Number: US2020227253A1 | Publication Date: 2020-07-16 | Application Number: 16/561,078 | Filing Date: 2019-09-05 | Inventor： Park, Sangjine Cho, Byung-kwon Jeong, Jihoon Kim, Youngtak Ko, Yongsun Jeon, Seulgee | Assignee: SAMSUNG ELECTRONICS CO., LTD. | IPC: H01L21/02 | Abstract: A supercritical drying apparatus and a method of drying a substrate, the apparatus including a drying chamber configured to receive a supercritical fluid and to dry a substrate; a chuck in the drying chamber, the chuck being configured to receive the substrate; and a particle remover in the drying chamber, the particle remover being configured to remove dry particles from the substrate by heating the substrate with radiant heat. | |||
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8 | KR20190051654A |
method for treating substrate
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Publication/Patent Number: KR20190051654A | Publication Date: 2019-05-15 | Application Number: 20170147527 | Filing Date: 2017-11-07 | Inventor： Cho, Yong Jhin Lee, Kuntack Cha, Ji Hoon Cho, Byung Kwon Gil, Yeonjin Park, Sangjine | Assignee: SAMSUNG ELECTRONICS CO., LTD. | IPC: H01L21/687 | Abstract: The present invention discloses a substrate processing apparatus. The apparatus includes: a lower housing; an upper housing covering the lower housing; and a chuck provided between the upper housing and the lower housing and receiving a substrate. The upper housing can have a gap of 1.5 mm to 5.5 mm from the substrate on the chuck. | |||
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9 | US9966432B2 |
Semiconductor devices including an etch stop pattern and a sacrificial pattern with coplanar upper surfaces and a gate and a gap fill pattern with coplanar upper surfaces
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Publication/Patent Number: US9966432B2 | Publication Date: 2018-05-08 | Application Number: 15/010,470 | Filing Date: 2016-01-29 | Inventor： Han, Jeongnam Yoon, Boun Park, Sangjine | Assignee: Samsung Electronics Co., Ltd. | IPC: H01L29/417 | Abstract: Semiconductor devices and methods of manufacturing semiconductor devices. A semiconductor device includes a metal gate electrode stacked on a semiconductor substrate with a gate insulation layer disposed therebetween, spacer structures disposed on the semiconductor substrate at both sides of the metal gate electrode, source/drain regions formed in the semiconductor substrate at the both sides of the metal gate electrode, and an etch stop pattern including a bottom portion covering the source/drain regions and a sidewall portion extended from the bottom portion to cover a portion of sidewalls of the spacer structures, in which an upper surface of the sidewall portion of the etch stop pattern is positioned under an upper surface of the metal gate electrode. | |||
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10 | US10084051B2 |
Semiconductor devices including field effect transistors and methods of fabricating the same
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Publication/Patent Number: US10084051B2 | Publication Date: 2018-09-25 | Application Number: 15/133,424 | Filing Date: 2016-04-20 | Inventor： Park, Sangjine Lee, Jae-hwan Ko, Yongsun | Assignee: SAMSUNG ELECTRONICS CO., LTD. | IPC: H01L29/78 | Abstract: A semiconductor device includes a fin structure on a substrate, device isolation patterns on the substrate at opposite sides of the fin structure, a gate electrode intersecting the fin structure and the device isolation patterns, a gate dielectric pattern between the gate electrode and the fin structure and between the gate electrode and the device isolation patterns, and gate spacers on opposite sidewalls of the gate electrode, wherein, on each of the device isolation patterns, a bottom surface of the gate dielectric pattern is at a higher level than bottom surfaces of the gate spacers. | |||
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11 | US10128336B2 |
Semiconductor devices and methods for manufacturing the same
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Publication/Patent Number: US10128336B2 | Publication Date: 2018-11-13 | Application Number: 15/009,119 | Filing Date: 2016-01-28 | Inventor： Park, Sangjine Yoon, Boun Han, Jeongnam | Assignee: Samsung Electronics Co., Ltd. | IPC: H01L29/66 | Abstract: Semiconductor devices and methods of manufacturing semiconductor devices. A semiconductor device includes a metal gate electrode stacked on a semiconductor substrate with a gate insulation layer disposed therebetween, spacer structures disposed on the semiconductor substrate at both sides of the metal gate electrode, source/drain regions formed in the semiconductor substrate at the both sides of the metal gate electrode, and an etch stop pattern including a bottom portion covering the source/drain regions and a sidewall portion extended from the bottom portion to cover a portion of sidewalls of the spacer structures, in which an upper surface of the sidewall portion of the etch stop pattern is positioned under an upper surface of the metal gate electrode. | |||
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12 | US9960241B2 |
Semiconductor device for manufacturing
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Publication/Patent Number: US9960241B2 | Publication Date: 2018-05-01 | Application Number: 14/989,485 | Filing Date: 2016-01-06 | Inventor： Yoon, Boun Baek, Jae-jik Kwon, Kee Sang Park, Sangjine | Assignee: Samsung Electronics Co., Ltd. | IPC: H01L21/8234 | Abstract: A semiconductor device includes an active pattern protruding from a substrate, gate structures crossing over the active pattern, gate spacers on sidewalls of the gate structures, a source/drain region in the active pattern between the gate structures, and a source/drain contact on and connected to the source/drain region. The source/drain contact includes a first portion between the gate structures and being in contact with the gate spacers, a second portion on the first portion and not being in contact with the gate spacers, and a third portion on the second portion. A first boundary between the second and third portions is at the substantially same height as a top surface of the gate structure. | |||
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13 | US2017154991A1 |
Semiconductor Devices
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Publication/Patent Number: US2017154991A1 | Publication Date: 2017-06-01 | Application Number: 15/245,549 | Filing Date: 2016-08-24 | Inventor： Ko, Yongsun Park, Sangjine Cho, Hagju Park, Byungjae Han, Jeongnam | Assignee: Samsung Electronics Co., Ltd. | IPC: H01L29/78 | Abstract: A semiconductor device may include a pair of active patterns spaced apart from each other in a first direction, a pair of gate electrodes intersecting the pair of the active patterns in a second direction crossing the first direction, gate spacers on sidewalls of the pair of the active patterns, source/drain regions on the pair active patterns between the pair of the gate electrodes, and a spacer protection pattern between the pair of the gate electrodes and between the pair of the active patterns. The spacer protection pattern may be commonly connected to the gate spacers. | |||
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14 | DE102016119492A1 |
Halbleitervorrichtungen
Title (English):
semiconductor device
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Publication/Patent Number: DE102016119492A1 | Publication Date: 2017-06-01 | Application Number: 102016119492 | Filing Date: 2016-10-13 | Inventor： Ko, Yongsun Han, Jeongnam Cho, Hagju Park, Byungjae Park, Sangjine | Assignee: Samsung Electronics Co., Ltd. | IPC: H01L21/8234 | Abstract: Eine Halbleitervorrichtung kann ein Paar von aktiven Strukturen (AP) beabstandet voneinander in einer ersten Richtung (D1) aufweisen | |||
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15 | US2017345822A1 |
SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME
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Publication/Patent Number: US2017345822A1 | Publication Date: 2017-11-30 | Application Number: 15/676,317 | Filing Date: 2017-08-14 | Inventor： Kwon, Kee Sang Yoon, Boun Park, Sangjine Song, Myunggeun Ko, Ki-hyung Yun, Jiwon | Assignee: Samsung Electronics Co., Ltd. | IPC: H01L27/088 | Abstract: Semiconductor devices may include a substrate, gate electrodes on the substrate, and source/drain regions at both sides of each of the gate electrodes. Each of the gate electrodes may include a gate insulating pattern on the substrate, a lower work-function electrode pattern that is on the gate insulating pattern and has a recessed upper surface, and an upper work-function electrode pattern that conformally extends on the recessed upper surface of the lower work function electrode pattern. Topmost surfaces of the lower work-function electrode patterns may be disposed at an equal level, and the upper work-function electrode patterns may have different thicknesses from each other. | |||
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16 | US9716162B2 |
Semiconductor device and method of fabricating the same
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Publication/Patent Number: US9716162B2 | Publication Date: 2017-07-25 | Application Number: 14/697,829 | Filing Date: 2015-04-28 | Inventor： Park, Sangjine Baek, Jae-jik Song, Myunggeun Yoon, Boun Choi, Sukhun Han, Jeongnam | Assignee: Samsung Electronics Co., Ltd. | IPC: H01L29/66 | Abstract: Provided is a semiconductor device including a substrate with an active pattern, a gate electrode crossing the active pattern, and a gate capping pattern on the gate electrode. The gate capping pattern may have a width larger than that of the gate electrode, and the gate capping pattern may include extended portions extending toward the substrate and at least partially covering both sidewalls of the gate electrode. | |||
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17 | US2017301773A1 |
SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
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Publication/Patent Number: US2017301773A1 | Publication Date: 2017-10-19 | Application Number: 15/632,735 | Filing Date: 2017-06-26 | Inventor： Park, Sangjine Baek, Jae-jik Song, Myunggeun Yoon, Boun Choi, Sukhun Han, Jeongnam | Assignee: Samsung Electronics Co., Ltd. | IPC: H01L29/66 | Abstract: Provided is a semiconductor device including a substrate with an active pattern, a gate electrode crossing the active pattern, and a gate capping pattern on the gate electrode. The gate capping pattern may have a width larger than that of the gate electrode, and the gate capping pattern may include extended portions extending toward the substrate and at least partially covering both sidewalls of the gate electrode. |
