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No. Publication Number Title Publication/Patent Number Publication/Patent Number Publication Date Publication Date
Application Number Application Number Filing Date Filing Date
Inventor Inventor Assignee Assignee IPC IPC
1
US2021005534A1
SEMICONDUCTOR DEVICE WITH THROUGH-SUBSTRATE VIA AND ITS METHOD OF MANUFACTURE
Publication/Patent Number: US2021005534A1 Publication Date: 2021-01-07 Application Number: 16/968,815 Filing Date: 2019-02-15 Inventor: Sidorov, Victor   Jessenig, Stefan   Parteder, Georg   Assignee: ams AG   IPC: H01L23/48 Abstract: A dielectric layer is arranged on a main surface of a semiconductor substrate, a metal layer providing a contact area is embedded in the dielectric layer, a top metal is arranged on an opposite main surface of the substrate, and an electrically conductive interconnection through the substrate, which comprises a plurality of metallizations arranged in a plurality of via holes, connects the contact area with the top metal. The plurality of metallizations is surrounded by an insulating layer penetrating the substrate.
2
US2021020511A1
METHOD OF FORMING A THROUGH-SUBSTRATE VIA AND A SEMICONDUCTOR DEVICE COMPRISING A THROUGH-SUBSTRATE VIA
Publication/Patent Number: US2021020511A1 Publication Date: 2021-01-21 Application Number: 16/980,197 Filing Date: 2019-04-03 Inventor: Kraft, Jochen   Parteder, Georg   Jessenig, Stefan   Schrank, Franz   Siegert, Jörg   Assignee: ams AG   IPC: H01L21/768 Abstract: A substrate is provided with a dielectric, a metal layer embedded in the dielectric, and a metallic layer arranged on the metal layer between the substrate and the metal layer. A via hole is formed in the substrate and in a region of the dielectric that is between the substrate and the metal layer. An insulation layer is applied in the via hole and removed from above a contact area of the metal layer, and the metallic layer is completely removed from the contact area. A metallization is applied in the via hole on the contact area.
3
EP3460835B1
METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
Publication/Patent Number: EP3460835B1 Publication Date: 2020-04-01 Application Number: 17192105.9 Filing Date: 2017-09-20 Inventor: Parteder, Georg   Kraft, Jochen   Coppeta, Raffaele   Assignee: ams AG   IPC: H01L21/768
4
EP3756216A1
SEMICONDUCTOR DEVICE WITH THROUGH-SUBSTRATE VIA AND ITS METHOD OF MANUFACTURE
Publication/Patent Number: EP3756216A1 Publication Date: 2020-12-30 Application Number: 19705355.6 Filing Date: 2019-02-15 Inventor: Sidorov, Victor   Jessenig, Stefan   Parteder, Georg   Assignee: AMS AG   IPC: H01L21/768
5
US2020020611A1
Semiconductor Device
Publication/Patent Number: US2020020611A1 Publication Date: 2020-01-16 Application Number: 16/483,884 Filing Date: 2018-02-14 Inventor: Kraft, Jochen   Parteder, Georg   Singulani, Anderson   Coppeta, Raffaele   Schrank, Franz   Assignee: ams AG   IPC: H01L23/48 Abstract: A semiconductor device comprises a semiconductor body and an electrically conductive via which extends through at least a part of the semiconductor body, where the via has a lateral size which is given in a first lateral direction that is perpendicular to a vertical direction given by the main axis of extension of the via and where the via has a top side and a bottom side that faces away from the top side. The semiconductor device further comprises an electrically conductive etch-stop layer arranged at the bottom side of the via in a plane which is parallel to the first lateral direction, and at least one electrically conductive contact layer at the bottom side of the via in a plane which is parallel to the first lateral direction. The lateral extent in the first lateral direction of the etch-stop layer is larger than the lateral size of the via and the lateral extent in the first lateral direction of the contact layer is smaller than the lateral size of the via. Furthermore, the etch-stop layer is arranged between the electrically conductive via and the contact layer in the vertical direction.
6
US202020611A1
Semiconductor Device
Publication/Patent Number: US202020611A1 Publication Date: 2020-01-16 Application Number: 20/181,648 Filing Date: 2018-02-14 Inventor: Singulani, Anderson   Kraft, Jochen   Parteder, Georg   Coppeta, Raffaele   Schrank, Franz   Assignee: ams AG   IPC: H01L23/528 Abstract: A semiconductor device comprises a semiconductor body and an electrically conductive via which extends through at least a part of the semiconductor body, where the via has a lateral size which is given in a first lateral direction that is perpendicular to a vertical direction given by the main axis of extension of the via and where the via has a top side and a bottom side that faces away from the top side. The semiconductor device further comprises an electrically conductive etch-stop layer arranged at the bottom side of the via in a plane which is parallel to the first lateral direction, and at least one electrically conductive contact layer at the bottom side of the via in a plane which is parallel to the first lateral direction. The lateral extent in the first lateral direction of the etch-stop layer is larger than the lateral size of the via and the lateral extent in the first lateral direction of the contact layer is smaller than the lateral size of the via. Furthermore, the etch-stop layer is arranged between the electrically conductive via and the contact layer in the vertical direction.
7
EP3550600B1
METHOD OF FORMING A THROUGH-SUBSTRATE VIA AND SEMICONDUCTOR DEVICE COMPRISING THE THROUGH-SUBSTRATE VIA
Publication/Patent Number: EP3550600B1 Publication Date: 2020-08-05 Application Number: 18165692.7 Filing Date: 2018-04-04 Inventor: Kraft, Jochen   Parteder, Georg   Jessenig, Stefan   Schrank, Franz   Siegert, Jörg   Assignee: ams AG   IPC: H01L21/768
8
TW201916249A
Method for manufacturing a semiconductor device and semiconductor device
Publication/Patent Number: TW201916249A Publication Date: 2019-04-16 Application Number: 107130141 Filing Date: 2018-08-29 Inventor: Kraft, Jochen   Parteder, Georg   Coppeta, Raffaele   Assignee: AMS AG   IPC: H01L21/76 Abstract: A method for manufacturing a semiconductor device (10) is provided. The method comprises the steps of providing a semiconductor body (11), forming a trench (12) in the semiconductor body (11) in a vertical direction (z) which is perpendicular to the main plane of extension of the semiconductor body (11), and coating inner walls (13) of the trench (12) with an isolation layer (14). The method further comprises the steps of coating the isolation layer (14) at the inner walls (13) with a metallization layer (15), coating a top side (16) of the semiconductor body (11), at which the trench (12) is formed, at least partially with an electrically conductive contact layer (17), where the contact layer (17) is electrically connected with the metallization layer (15), coating the top side (16) of the semiconductor body (11) at least partially and the trench (12) with a capping layer (24), and forming a contact pad (18) at the top side (16) of the semiconductor body (11) by removing the contact layer (17) and the capping layer (24) at least partially. Furthermore, a semiconductor device (10) is provided.
9
EP3460835A1
METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
Publication/Patent Number: EP3460835A1 Publication Date: 2019-03-27 Application Number: 17192105.9 Filing Date: 2017-09-20 Inventor: Parteder, Georg   Kraft, Jochen   Coppeta, Raffaele   Assignee: ams AG   IPC: H01L21/768 Abstract: A method for manufacturing a semiconductor device (10) is provided. The method comprises the steps of providing a semiconductor body (11), forming a trench (12) in the semiconductor body (11) in a vertical direction (z) which is perpendicular to the main plane of extension of the semiconductor body (11), and coating inner walls (13) of the trench (12) with an isolation layer (14). The method further comprises the steps of coating the isolation layer (14) at the inner walls (13) with a metallization layer (15), coating a top side (16) of the semiconductor body (11), at which the trench (12) is formed, at least partially with an electrically conductive contact layer (17), where the contact layer (17) is electrically connected with the metallization layer (15), coating the top side (16) of the semiconductor body (11) at least partially and the trench (12) with a capping layer (24), and forming a contact pad (18) at the top side (16) of the semiconductor body (11) by removing the contact layer (17) and the capping layer (24) at least partially. Furthermore, a semiconductor device (10) is provided.
10
WO2019057436A1
METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
Publication/Patent Number: WO2019057436A1 Publication Date: 2019-03-28 Application Number: 2018072767 Filing Date: 2018-08-23 Inventor: Kraft, Jochen   Parteder, Georg   Coppeta, Raffaele   Assignee: AMS AG   IPC: H01L23/48 Abstract: A method for manufacturing a semiconductor device (10) is provided. The method comprises the steps of providing a semiconductor body (11), forming a trench (12) in the semiconductor body (11) in a vertical direction (z) which is perpendicular to the main plane of extension of the semiconductor body (11), and coating inner walls (13) of the trench (12) with an isolation layer (14). The method further comprises the steps of coating the isolation layer (14) at the inner walls (13) with a metallization layer (15), coating a top side (16) of the semiconductor body (11), at which the trench (12) is formed, at least partially with an electrically conductive contact layer (17), where the contact layer (17) is electrically connected with the metallization layer (15), coating the top side (16) of the semiconductor body (11) at least partially and the trench (12) with a capping layer (24), and forming a contact pad (18) at the top side (16) of the semiconductor body (11) by removing the contact layer (17) and the capping layer (24) at least partially. Furthermore, a semiconductor device (10) is provided.
11
EP3528281A1
SEMICONDUCTOR DEVICE WITH THROUGH-SUBSTRATE VIA AND ITS METHOD OF MANUFACTURE
Publication/Patent Number: EP3528281A1 Publication Date: 2019-08-21 Application Number: 18157371.8 Filing Date: 2018-02-19 Inventor: Sidorov, Victor   Jessenig, Stefan   Parteder, Georg   Assignee: ams AG   IPC: H01L21/768 Abstract: A dielectric layer (2) is arranged on a main surface (10) of a semiconductor substrate (1), a metal layer (3) providing a contact area (4) is embedded in the dielectric layer, a top metal (5) is arranged on an opposite main surface (11) of the substrate, and an electrically conductive interconnection (6) through the substrate, which comprises a plurality of metallizations (7) arranged in a plurality of via holes (17), connects the contact area with the top metal. The plurality of metallizations is surrounded by an insulating layer (8) penetrating the substrate.
12
WO2019158706A1
SEMICONDUCTOR DEVICE WITH THROUGH-SUBSTRATE VIA AND ITS METHOD OF MANUFACTURE
Publication/Patent Number: WO2019158706A1 Publication Date: 2019-08-22 Application Number: 2019053847 Filing Date: 2019-02-15 Inventor: Jessenig, Stefan   Parteder, Georg   Sidorov, Victor   Assignee: AMS AG   IPC: H01L21/768 Abstract: A dielectric layer (2) is arranged on a main surface (10) of a semiconductor substrate (1), a metal layer (3) providing a contact area (4) is embedded in the dielectric layer, a top metal (5) is arranged on an opposite main surface (11) of the substrate,and an electrically conductive interconnection (6) through the substrate, which comprises a plurality of metallizations (7) arranged in a plurality of via holes (17), connects the contact area with the top metal. The plurality of metallizations is surrounded by an insulating layer (8) penetrating the substrate.
13
WO2019211041A1
SEMICONDUCTOR DEVICE WITH THROUGH-SUBSTRATE VIA
Publication/Patent Number: WO2019211041A1 Publication Date: 2019-11-07 Application Number: 2019056964 Filing Date: 2019-03-20 Inventor: Schrank, Franz   Kraft, Jochen   Parteder, Georg   Singulani, Anderson   Coppeta, Raffaele   Assignee: AMS AG   IPC: H01L23/48 Abstract: A semiconductor device (10) comprises a semiconductor body (11), an electrically conductive via (12) which extends through at least a part of the semiconductor body (11), and where the via (12) has a top side (13) and a bottom side (14) that faces away from the top side (13), an electrically conductive etch-stop layer (15) arranged at the bottom side (14) of the via (12) in a plane which is parallel to a lateral direction (x), where the lateral direction (x) is perpendicular to a vertical direction (z) given by the main axis of extension of the via (12), and at least one electrically conductive contact layer (16) at the bottom side (14) of the via (12) in a plane which is parallel to the lateral direction (x). The etch-stop layer (16) is arranged between the electrically conductive via (12) and the contact layer (16) in the vertical direction (z), the lateral extent in the lateral direction (x) of the etch-stop layer (15) amounts to at least 2.5 times the lateral extent of the via (12) in the lateral direction (x), and the lateral extent of the contact layer (16) is smaller than the lateral extent of the via (12) or the lateral extent of the contact layer (16) amounts to at least 2.5 times the lateral extent of the via (12).
14
US10243017B2
Sensor chip stack and method of producing a sensor chip stack
Publication/Patent Number: US10243017B2 Publication Date: 2019-03-26 Application Number: 15/636,545 Filing Date: 2017-06-28 Inventor: Parteder, Georg   Kraft, Jochen   Schrank, Franz   Troxler, Thomas   Fitzi, Andreas   Assignee: ams International AG   IPC: H01L27/146 Abstract: The sensor chip stack comprises a sensor substrate of a semiconductor material including a sensor, a chip fastened to the sensor substrate, the chip including an integrated circuit, electric interconnections between the sensor substrate and the chip, electric terminals of the chip, the chip being arranged between the electric terminals and the sensor substrate, and a molding material arranged adjacent to the chip, the electric terminals of the chip being free from the molding material.
15
EP3564994A1
SEMICONDUCTOR DEVICE WITH THROUGH-SUBSTRATE VIA
Publication/Patent Number: EP3564994A1 Publication Date: 2019-11-06 Application Number: 18170639.1 Filing Date: 2018-05-03 Inventor: Kraft, Dr. Jochen   Parteder, Georg   Singulani, Anderson   Coppeta, Raffaele   Schrank, Franz   Assignee: ams AG   IPC: H01L23/48 Abstract: A semiconductor device (10) comprises a semiconductor body (11), an electrically conductive via (12) which extends through at least a part of the semiconductor body (11), and where the via (12) has a top side (13) and a bottom side (14) that faces away from the top side (13), an electrically conductive etch-stop layer (15) arranged at the bottom side (14) of the via (12) in a plane which is parallel to a lateral direction (x), where the lateral direction (x) is perpendicular to a vertical direction (z) given by the main axis of extension of the via (12), and at least one electrically conductive contact layer (16) at the bottom side (14) of the via (12) in a plane which is parallel to the lateral direction (x). The etch-stop layer (16) is arranged between the electrically conductive via (12) and the contact layer (16) in the vertical direction (z), the lateral extent in the lateral direction (x) of the etch-stop layer (15) amounts to at least 2.5 times the lateral extent of the via (12) in the lateral direction (x), and the lateral extent of the contact layer (16) is smaller than the lateral extent of the via (12) or the lateral extent of the contact layer (16) amounts to at least 2.5 times the lateral extent of the via (12) .
16
WO2019193067A1
METHOD OF FORMING A THROUGH-SUBSTRATE VIA AND A SEMICONDUCTOR DEVICE COMPRISING A THROUGH-SUBSTRATE VIA
Publication/Patent Number: WO2019193067A1 Publication Date: 2019-10-10 Application Number: 2019058430 Filing Date: 2019-04-03 Inventor: Schrank, Franz   Kraft, Jochen   Jessenig, Stefan   Siegert, JÖrg   Parteder, Georg   Assignee: AMS AG   IPC: H01L23/48 Abstract: A substrate (1) is provided with a dielectric (2), a metal layer (3) embedded in the dielectric, and a metallic layer (4) arranged on the metal layer between the substrate and the metal layer. A via hole (9) is formed in the substrate and in a region of the dielectric that is between the substrate and the metal layer. An insulation layer (11) is applied in the via hole and removed from above a contact area (10) of the metal layer, and the metallic layer is completely removed from the contact area (10). A metallization (12) is applied in the via hole on the contact area.
17
EP3550600A1
METHOD OF FORMING A THROUGH-SUBSTRATE VIA AND A SEMICONDUCTOR DEVICE COMPRISING A THROUGH-SUBSTRATE VIA
Publication/Patent Number: EP3550600A1 Publication Date: 2019-10-09 Application Number: 18165692.7 Filing Date: 2018-04-04 Inventor: Kraft, Jochen   Parteder, Georg   Jessenig, Stefan   Schrank, Franz   Siegert, Jörg   Assignee: ams AG   IPC: H01L21/768 Abstract: A substrate (1) is provided with a dielectric (2), a metal layer (3) embedded in the dielectric, and a metallic layer (4) arranged on the metal layer between the substrate and the metal layer. A via hole (9) is formed in the substrate and in a region of the dielectric that is between the substrate and the metal layer. An insulation layer (11) is applied in the via hole and removed from above a contact area (10) of the metal layer, and the metallic layer is completely removed from the contact area (10). A metallization (12) is applied in the via hole on the contact area.
18
US201896969A1
METHOD OF PRODUCING AN INTERPOSER-CHIP-ARRANGEMENT FOR DENSE PACKAGING OF CHIPS
Publication/Patent Number: US201896969A1 Publication Date: 2018-04-05 Application Number: 20/171,572 Filing Date: 2017-10-06 Inventor: Schrems, Martin   Schrank, Franz   Parteder, Georg   Assignee: ams AG   IPC: H01L25/065 Abstract: The method of producing an interposer-chip-arrangement, comprises providing an interposer (1) with an integrated circuit (25), arranging a dielectric layer (2) with metal layers embedded in the dielectric layer above a main surface (10) of the interposer, connecting the integrated circuit with at least one of the metal layers, forming an interconnection (7) through the interposer, the interconnection contacting one of the metal layers, arranging a further dielectric layer (3) above a further main surface (11) of the interposer opposite the main surface and arranging a further metal layer in or on the further dielectric layer, the further metal layer being connected with the interconnection, arranging a chip provided with at least one contact pad at the main surface or at the further main surface, and electrically conductively connecting the contact pad with the interconnection.
19
EP3312874A1
METHOD OF FORMING A THROUGH-SUBSTRATE VIA AND A SEMICONDUCTOR DEVICE COMPRISING A THROUGH-SUBSTRATE VIA
Publication/Patent Number: EP3312874A1 Publication Date: 2018-04-25 Application Number: 16194866.6 Filing Date: 2016-10-20 Inventor: Kraft, Jochen   Parteder, Georg   Jessenig, Stefan   Schrank, Franz   Assignee: ams AG   IPC: H01L21/768 Abstract: The method of forming a through-substrate via comprises providing a substrate (1) with a dielectric (2) arranged on the substrate (1) and with a metal layer (3) embedded in the dielectric (2), forming a via hole (9) penetrating the substrate (1), removing the dielectric (2) from above the metal layer (3), so that the via hole (9) reaches the metal layer (3), and a contact area (10) of the metal layer (3) is exposed inside the via hole (9), applying an insulation layer (11) in the via hole (9), removing the insulation layer (11) from above the metal layer (3), and applying a metallization (12) in the via hole (9), the metallization (12) contacting a contact area (10) of the metal layer (3) and being insulated from the substrate (1) by the insulation layer (11).
20
EP3364454A1
SEMICONDUCTOR DEVICE
Publication/Patent Number: EP3364454A1 Publication Date: 2018-08-22 Application Number: 17156319.0 Filing Date: 2017-02-15 Inventor: Kraft, Jochen   Parteder, Georg   Singulani, Anderson   Coppeta, Raffaele   Schrank, Franz   Assignee: AMS AG   IPC: H01L23/48 Abstract: A semiconductor device (10) comprises a semiconductor body (11) and an electrically conductive via (12) which extends through at least a part of the semiconductor body (11), where the via (12) has a lateral size which is given in a first lateral direction (x) that is perpendicular to a vertical direction (z) given by the main axis of extension of the via (12) and where the via (12) has a top side (13) and a bottom side (14) that faces away from the top side (13). The semiconductor device (10) further comprises an electrically conductive etch-stop layer (15) arranged at the bottom side (14) of the via (12) in a plane which is parallel to the first lateral direction (x), and at least one electrically conductive contact layer (16) at the bottom side (14) of the via (12) in a plane which is parallel to the first lateral direction (x). The lateral extent in the first lateral direction (x) of the etch-stop layer (15) is larger than the lateral size of the via (12) and the lateral extent in the first lateral direction (x) of the contact layer (16) is smaller than the lateral size of the via (12). Furthermore, the etch-stop layer (15) is arranged between the electrically conductive via (12) and the contact layer (16) in the vertical direction (z).
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