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1
US2021080487A1
ELECTROMAGNETIC SHIELDING DURING WAFER STAGE TESTING
Publication/Patent Number: US2021080487A1 Publication Date: 2021-03-18 Application Number: 16/572,369 Filing Date: 2019-09-16 Inventor: Peng ching nen   Wang, Hsien-tang   Wang, Mill-jer   Lai, Chi-chang   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: G01R1/18 Abstract: A circuit probe includes a shielding probe having a base and a conductive probe ring on the base. A shielding cage is attached to the conductive probe ring and has an interior. The shielding cage is configured to be positioned to contain in the interior of the shielding cage at least one integrated circuit formed on a wafer, and to provide electromagnetic shielding of the at least one integrated circuit during testing of the at least one integrated circuit.
2
US2021013748A1
COMPOSITE INTEGRATED CIRCUITS AND METHODS FOR WIRELESS INTERACTIONS THEREWITH
Publication/Patent Number: US2021013748A1 Publication Date: 2021-01-14 Application Number: 17/015,602 Filing Date: 2020-09-09 Inventor: Wang, Min-jer   Peng ching nen   Jou, Chewn-pu   Kuo, Feng Wei   Chen, Hao   Lin, Hung-chih   Chen, Huan-neng   Yen, Kuang-kai   Liu, Ming-chieh   Lee, Tsung-hsiung   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H02J50/40 Abstract: An integrated circuit (IC) includes a first circuit layer that includes a first wireless power transfer (WPT) device, a first chip electrically connected to the first circuit layer, and a first tracking circuit disposed in the first chip. The first WPT device may be configured to extract energy from an electromagnetic signal and provide an output voltage. The first tracking circuit may be powered by the output voltage of the first WPT device and may output tracking data in response to an instruction extracted from the electromagnetic signal.
3
US2020245439A1
THREE DIMENSIONAL INTEGRATED CIRCUIT ELECTROSTATIC DISCHARGE PROTECTION AND PREVENTION TEST INTERFACE
Publication/Patent Number: US2020245439A1 Publication Date: 2020-07-30 Application Number: 16/851,873 Filing Date: 2020-04-17 Inventor: Wang, Mill-jer   Peng ching nen   Lin, Hung-chih   Cheng, Hao   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H05F3/02 Abstract: The present disclosure provides a system and method for providing electrostatic discharge protection. A probe card assembly is provided which is electrically connected to a plurality of input/output channels. The probe card assembly can be contacted with a secondary assembly having an interposer electrically connected to one or more wafers each wafer having a device under test. Voltage can be forced on ones of the plural input/output channels of the probe card assembly to slowly dissipate charges resident on the wafer to thereby provide electrostatic discharge protection. A socket assembly adaptable to accept a 3DIC package is also provided, the assembly having a loadboard assembly electrically connected to a plurality of input/output channels. Once the 3DIC package is placed within the socket assembly, voltage is forced on ones of the input/output channels to slowly dissipate charges resident on the 3DIC package to thereby provide electrostatic discharge protection.
4
US10652987B2
Three dimensional integrated circuit electrostatic discharge protection and prevention test interface
Publication/Patent Number: US10652987B2 Publication Date: 2020-05-12 Application Number: 15/882,256 Filing Date: 2018-01-29 Inventor: Wang, Mill-jer   Peng ching nen   Lin, Hung-chih   Cheng, Hao   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H05F3/00 Abstract: The present disclosure provides a system and method for providing electrostatic discharge protection. A probe card assembly is provided which is electrically connected to a plurality of input/output channels. The probe card assembly can be contacted with a secondary assembly having an interposer electrically connected to one or more wafers each wafer having a device under test. Voltage can be forced on ones of the plural input/output channels of the probe card assembly to slowly dissipate charges resident on the wafer to thereby provide electrostatic discharge protection. A socket assembly adaptable to accept a 3DIC package is also provided, the assembly having a loadboard assembly electrically connected to a plurality of input/output channels. Once the 3DIC package is placed within the socket assembly, voltage is forced on ones of the input/output channels to slowly dissipate charges resident on the 3DIC package to thereby provide electrostatic discharge protection.
5
US2020326370A1
TESTING HOLDERS FOR CHIP UNIT AND DIE PACKAGE
Publication/Patent Number: US2020326370A1 Publication Date: 2020-10-15 Application Number: 16/912,017 Filing Date: 2020-06-25 Inventor: Wang, Mill-jer   Liu, Kuo-chuan   Peng ching nen   Lin, Hung-chih   Chen, Hao   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.   IPC: G01R31/28 Abstract: A testing holder for a chip unit, a multi site holding frame for plural chip units and a method for testing a die thereof are provided. The proposed multi site holding frame for testing plural chip units simultaneously includes a first holder frame having a plurality of testing holders. Each of the plurality of testing holders includes a holder body containing a specific one of the plural chip units, and a pressure releasing device formed on the holder body to release an insertion pressure when the specific one of the plural chip units is inserted in the holder body.
6
US2020264227A1
ALIGNMENT TESTING FOR TIERED SEMICONDUCTOR STRUCTURE
Publication/Patent Number: US2020264227A1 Publication Date: 2020-08-20 Application Number: 16/865,804 Filing Date: 2020-05-04 Inventor: Wang, Mill-jer   Peng ching nen   Lin, Hung-chih   Chen, Hao   Lee, Mincent   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED   IPC: G01R31/28 Abstract: Among other things, one or more techniques or systems for evaluating a tiered semiconductor structure, such as a stacked CMOS structure, for misalignment are provided. In an embodiment, a connectivity test is performed on vias between a first layer and a second layer to determine a via diameter and a via offset that are used to evaluate misalignment. In an embodiment, a connectivity test for vias within a first layer is performed to determine an alignment rotation based upon which vias are connected through a conductive arc within a second layer or which vias are connected to a conductive pattern out of a set of conductive patterns. In this way, the via diameter, the via offset, or the alignment rotation are used to evaluate the tiered semiconductor structure, such as during a stacked CMOS process, for misalignment.
7
US10698026B2
Testing holders for chip unit and die package
Publication/Patent Number: US10698026B2 Publication Date: 2020-06-30 Application Number: 16/119,871 Filing Date: 2018-08-31 Inventor: Wang, Mill-jer   Liu, Kuo-chuan   Peng ching nen   Lin, Hung-chih   Chen, Hao   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.   IPC: G01R31/28 Abstract: A testing holder for a chip unit, a multi site holding frame for plural chip units and a method for testing a die thereof are provided. The proposed multi site holding frame for testing plural chip units simultaneously includes a first holder frame having a plurality of testing holders. Each of the plurality of testing holders includes a holder body containing a specific one of the plural chip units, and a pressure releasing device formed on the holder body to release an insertion pressure when the specific one of the plural chip units is inserted in the holder body.
8
US10641819B2
Alignment testing for tiered semiconductor structure
Publication/Patent Number: US10641819B2 Publication Date: 2020-05-05 Application Number: 16/126,458 Filing Date: 2018-09-10 Inventor: Wang, Mill-jer   Peng ching nen   Lin, Hung-chih   Chen, Hao   Lee, Mincent   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED   IPC: G01R31/28 Abstract: Among other things, one or more techniques or systems for evaluating a tiered semiconductor structure, such as a stacked CMOS structure, for misalignment are provided. In an embodiment, a connectivity test is performed on vias between a first layer and a second layer to determine a via diameter and a via offset that are used to evaluate misalignment. In an embodiment, a connectivity test for vias within a first layer is performed to determine an alignment rotation based upon which vias are connected through a conductive arc within a second layer or which vias are connected to a conductive pattern out of a set of conductive patterns. In this way, the via diameter, the via offset, or the alignment rotation are used to evaluate the tiered semiconductor structure, such as during a stacked CMOS process, for misalignment.
9
US2020348341A1
DEVICES FOR HIGH-DENSITY PROBING TECHNIQUES AND METHOD OF IMPLEMENTING THE SAME
Publication/Patent Number: US2020348341A1 Publication Date: 2020-11-05 Application Number: 16/933,576 Filing Date: 2020-07-20 Inventor: Wang, Mill-jer   Peng ching nen   Lin, Hung-chih   Lin, Wei-hsun   Hsu, Sen-kuei   Liu, De-jian   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: G01R1/073 Abstract: A testing apparatus with reduced warping of the probe card and a method of reducing warping of a probe card of a testing apparatus are disclosed. The testing apparatus can include a testing head and a platform opposite the testing head, where the testing head and platform move relative to one another to bring a sample into contact with probing tips of the testing apparatus. The testing head can include a probe card printed circuit board, a stiffener, a discontinuous backer and a plurality of probing tips. The stiffener can be coupled to and reinforcing the probe card. The discontinuous backer can extend from the probe card to the stiffener, and can include at least one unfilled void extending from the stiffener to the probe card. The plurality of probing tips can extend from a distal end of the testing head.
10
US10718790B2
Devices for high-density probing techniques and method of implementing the same
Publication/Patent Number: US10718790B2 Publication Date: 2020-07-21 Application Number: 16/378,288 Filing Date: 2019-04-08 Inventor: Wang, Mill-jer   Peng ching nen   Lin, Hung-chih   Lin, Wei-hsun   Hsu, Sen-kuei   Liu, De-jian   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: G01R1/073 Abstract: A testing apparatus with reduced warping of the probe card and a method of reducing warping of a probe card of a testing apparatus are disclosed. The testing apparatus can include a testing head and a platform opposite the testing head, where the testing head and platform move relative to one another to bring a sample into contact with probing tips of the testing apparatus. The testing head can include a probe card printed circuit board, a stiffener, a discontinuous backer and a plurality of probing tips. The stiffener can be coupled to and reinforcing the probe card. The discontinuous backer can extend from the probe card to the stiffener, and can include at least one unfilled void extending from the stiffener to the probe card. The plurality of probing tips can extend from a distal end of the testing head.
11
US10725090B2
Test circuit and method
Publication/Patent Number: US10725090B2 Publication Date: 2020-07-28 Application Number: 15/893,466 Filing Date: 2018-02-09 Inventor: Wang, Mill-jer   Peng ching nen   Lin, Hung-chih   Hsu, Sen-kuei   Wang, Chuan-ching   Chen, Hao   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.   IPC: G01R31/265 Abstract: A method that is disclosed that includes the operations outlined below. Dies are arranged on a test fixture, and each of the dies includes first antennas and at least one via array, wherein the at least one via array is formed between at least two of the first antennas to separate the first antennas. By the first antennas of the dies, test processes are sequentially performed on an under-test device including second antennas that positionally correspond to the first antennas, according to signal transmissions between the first antennas and the second antennas.
12
US2020355737A1
TEST CIRCUIT AND METHOD
Publication/Patent Number: US2020355737A1 Publication Date: 2020-11-12 Application Number: 16/939,784 Filing Date: 2020-07-27 Inventor: Wang, Mill-jer   Peng ching nen   Lin, Hung-chih   Hsu, Sen-kuei   Wang, Chuan-ching   Chen, Hao   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED   IPC: G01R31/265 Abstract: A method that is disclosed that includes the operations outlined below. Dies are arranged on a test fixture, and each of the dies includes first antennas and at least one via array, wherein the at least one via array is formed between at least two of the first antennas to separate the first antennas. By the first antennas of the dies, test processes are sequentially performed on an under-test device including second antennas that positionally correspond to the first antennas, according to signal transmissions between the first antennas and the second antennas.
13
US10790707B2
Composite integrated circuits and methods for wireless interactions therewith
Publication/Patent Number: US10790707B2 Publication Date: 2020-09-29 Application Number: 16/220,514 Filing Date: 2018-12-14 Inventor: Wang, Min-jer   Peng ching nen   Jou, Chewn-pu   Kuo, Feng Wei   Chen, Hao   Lin, Hung-chih   Chen, Huan-neng   Yen, Kuang-kai   Liu, Ming-chieh   Lee, Tsung-hsiung   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.   IPC: G06F11/00 Abstract: An integrated circuit (IC) includes a first circuit layer that includes a first wireless power transfer (WPT) device, a first chip electrically connected to the first circuit layer, and a first tracking circuit disposed in the first chip. The first WPT device may be configured to extract energy from an electromagnetic signal and provide an output voltage. The first tracking circuit may be powered by the output voltage of the first WPT device and may output tracking data in response to an instruction extracted from the electromagnetic signal.
14
US201925368A1
ALIGNMENT TESTING FOR TIERED SEMICONDUCTOR STRUCTURE
Publication/Patent Number: US201925368A1 Publication Date: 2019-01-24 Application Number: 20/181,612 Filing Date: 2018-09-10 Inventor: Lee, Mincent   Wang, Mill-jer   Lin, Hung-chih   Chen, Hao   Peng ching nen   Assignee: Taiwan Semiconductor Manufacturing Company Limited   IPC: G01B7/12 Abstract: Among other things, one or more techniques or systems for evaluating a tiered semiconductor structure, such as a stacked CMOS structure, for misalignment are provided. In an embodiment, a connectivity test is performed on vias between a first layer and a second layer to determine a via diameter and a via offset that are used to evaluate misalignment. In an embodiment, a connectivity test for vias within a first layer is performed to determine an alignment rotation based upon which vias are connected through a conductive arc within a second layer or which vias are connected to a conductive pattern out of a set of conductive patterns. In this way, the via diameter, the via offset, or the alignment rotation are used to evaluate the tiered semiconductor structure, such as during a stacked CMOS process, for misalignment.
15
US2019025368A1
ALIGNMENT TESTING FOR TIERED SEMICONDUCTOR STRUCTURE
Publication/Patent Number: US2019025368A1 Publication Date: 2019-01-24 Application Number: 16/126,458 Filing Date: 2018-09-10 Inventor: Wang, Mill-jer   Peng ching nen   Lin, Hung-chih   Chen, Hao   Lee, Mincent   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED   IPC: G01R31/28 Abstract: Among other things, one or more techniques or systems for evaluating a tiered semiconductor structure, such as a stacked CMOS structure, for misalignment are provided. In an embodiment, a connectivity test is performed on vias between a first layer and a second layer to determine a via diameter and a via offset that are used to evaluate misalignment. In an embodiment, a connectivity test for vias within a first layer is performed to determine an alignment rotation based upon which vias are connected through a conductive arc within a second layer or which vias are connected to a conductive pattern out of a set of conductive patterns. In this way, the via diameter, the via offset, or the alignment rotation are used to evaluate the tiered semiconductor structure, such as during a stacked CMOS process, for misalignment.
16
US10274518B2
Devices for high-density probing techniques and method of implementing the same
Publication/Patent Number: US10274518B2 Publication Date: 2019-04-30 Application Number: 15/140,758 Filing Date: 2016-04-28 Inventor: Wang, Mill-jer   Peng ching nen   Lin, Hung-chih   Lin, Wei-hsun   Hsu, Sen-kuei   Liu, De-jian   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: G01R1/073 Abstract: A testing apparatus with reduced warping of the probe card and a method of reducing warping of a probe card of a testing apparatus are disclosed. The testing apparatus can include a testing head and a platform opposite the testing head, where the testing head and platform move relative to one another to bring a sample into contact with probing tips of the testing apparatus. The testing head can include a probe card printed circuit board, a stiffener, a discontinuous backer and a plurality of probing tips. The stiffener can be coupled to and reinforcing the probe card. The discontinuous backer can extend from the probe card to the stiffener, and can include at least one unfilled void extending from the stiffener to the probe card. The plurality of probing tips can extend from a distal end of the testing head.
17
US2019302146A1
DEVICES FOR HIGH-DENSITY PROBING TECHNIQUES AND METHOD OF IMPLEMENTING THE SAME
Publication/Patent Number: US2019302146A1 Publication Date: 2019-10-03 Application Number: 16/378,288 Filing Date: 2019-04-08 Inventor: Wang, Mill-jer   Peng ching nen   Lin, Hung-chih   Lin, Wei-hsun   Hsu, Sen-kuei   Liu, De-jian   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: G01R1/073 Abstract: A testing apparatus with reduced warping of the probe card and a method of reducing warping of a probe card of a testing apparatus are disclosed. The testing apparatus can include a testing head and a platform opposite the testing head, where the testing head and platform move relative to one another to bring a sample into contact with probing tips of the testing apparatus. The testing head can include a probe card printed circuit board, a stiffener, a discontinuous backer and a plurality of probing tips. The stiffener can be coupled to and reinforcing the probe card. The discontinuous backer can extend from the probe card to the stiffener, and can include at least one unfilled void extending from the stiffener to the probe card. The plurality of probing tips can extend from a distal end of the testing head.
18
US2019140488A1
Composite Integrated Circuits and Methods for Wireless Interactions Therewith
Publication/Patent Number: US2019140488A1 Publication Date: 2019-05-09 Application Number: 16/220,514 Filing Date: 2018-12-14 Inventor: Wang, Min-jer   Peng ching nen   Jou, Chewn-pu   Kuo, Feng Wei   Chen, Hao   Lin, Hung-chih   Chen, Huan-neng   Yen, Kuang-kai   Liu, Ming-chieh   Lee, Tsung-hsiung   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H02J50/40 Abstract: An integrated circuit (IC) includes a first circuit layer that includes a first wireless power transfer (WPT) device, a first chip electrically connected to the first circuit layer, and a first tracking circuit disposed in the first chip. The first WPT device may be configured to extract energy from an electromagnetic signal and provide an output voltage. The first tracking circuit may be powered by the output voltage of the first WPT device and may output tracking data in response to an instruction extracted from the electromagnetic signal.
19
US9900970B2
Three dimensional integrated circuit electrostatic discharge protection and prevention test interface
Publication/Patent Number: US9900970B2 Publication Date: 2018-02-20 Application Number: 14/975,951 Filing Date: 2015-12-21 Inventor: Wang, Mill-jer   Peng ching nen   Lin, Hung-chih   Chen, Hao   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H05K1/18 Abstract: The present disclosure provides a system and method for providing electrostatic discharge protection. A probe card assembly is provided which is electrically connected to a plurality of input/output channels. The probe card assembly can be contacted with a secondary assembly having an interposer electrically connected to one or more wafers each wafer having a device under test. Voltage can be forced on ones of the plural input/output channels of the probe card assembly to slowly dissipate charges resident on the wafer to thereby provide electrostatic discharge protection. A socket assembly adaptable to accept a 3DIC package is also provided, the assembly having a loadboard assembly electrically connected to a plurality of input/output channels. Once the 3DIC package is placed within the socket assembly, voltage is forced on ones of the input/output channels to slowly dissipate charges resident on the 3DIC package to thereby provide electrostatic discharge protection.
20
US2018153026A1
THREE DIMENSIONAL INTEGRATED CIRCUIT ELECTROSTATIC DISCHARGE PROTECTION AND PREVENTION TEST INTERFACE
Publication/Patent Number: US2018153026A1 Publication Date: 2018-05-31 Application Number: 15/882,256 Filing Date: 2018-01-29 Inventor: Cheng, Hao   Lin, Hung-chih   Peng ching nen   Wang, Mill-jer   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H02H9/04 Abstract: The present disclosure provides a system and method for providing electrostatic discharge protection. A probe card assembly is provided which is electrically connected to a plurality of input/output channels. The probe card assembly can be contacted with a secondary assembly having an interposer electrically connected to one or more wafers each wafer having a device under test. Voltage can be forced on ones of the plural input/output channels of the probe card assembly to slowly dissipate charges resident on the wafer to thereby provide electrostatic discharge protection. A socket assembly adaptable to accept a 3DIC package is also provided, the assembly having a loadboard assembly electrically connected to a plurality of input/output channels. Once the 3DIC package is placed within the socket assembly, voltage is forced on ones of the input/output channels to slowly dissipate charges resident on the 3DIC package to thereby provide electrostatic discharge protection.
Total 6 pages