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No. Publication Number Title Publication/Patent Number Publication/Patent Number Publication Date Publication Date
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1 US10635528B2
Memory controller and method of controlling memory controller
Publication/Patent Number: US10635528B2 Publication Date: 2020-04-28 Application Number: 15/323,574 Filing Date: 2015-05-20 Inventor: Shinbashi, Tatsuo   Sakai, Lui   Ikegaya, Ryoji   Assignee: SONY CORPORATION   IPC: G11C29/52 Abstract: A utilization efficiency of a memory is improved. A codeword generation unit generates a codeword in an error detection and correction code from data to be encoded. A write control unit writes one of data obtained by inverting the codeword and the codeword into the memory cell as write data. A read data error correction unit reads out the write data from the memory cell as read data, and corrects an error in the read data. An inversion data error correction unit corrects an error in inversion data obtained by inverting the read data. A correction data output unit, when the number of errors of either only one of the read data and the inversion data does not exceed an error correction capability of the error detection and correction code, selects and outputs the one where the error is corrected as correction data. A utilization efficiency of a memory is improved. A codeword generation unit generates a codeword in an error detection and correction code from data to be encoded. A write control unit writes one of data obtained by inverting the codeword and the codeword into the memory cell ...More ...Less
2 US10545804B2
Memory controller, memory system, and memory controller control method
Publication/Patent Number: US10545804B2 Publication Date: 2020-01-28 Application Number: 15/507,413 Filing Date: 2015-07-22 Inventor: Shinbashi, Tatsuo   Tsutsui, Keiichi   Okubo, Hideaki   Sakai, Lui   Nakanishi, Kenichi   Fujinami, Yasushi   Assignee: Sony Corporation   IPC: G06F11/00 Abstract: [Object] To sufficiently reduce frequency of error occurrence in memory cells. [Solution] A reading unit reads read data from a memory cell, the read data including an information bit and reversal information for determining whether or not the information bit has been reversed. In addition, an error detection/correction unit detects the presence or absence of an error in the information bit and corrects the error. A data reversing unit reverses the information bit that has the error corrected and the reversal information. Furthermore, a writing unit writes the reversed information bit and the reversed reversal information in the memory cell. [Object] To sufficiently reduce frequency of error occurrence in memory cells. [Solution] A reading unit reads read data from a memory cell, the read data including an information bit and reversal information for determining whether or not the information bit has been reversed ...More ...Less
3 EP3211536B1
MEMORY CONTROLLER, MEMORY SYSTEM, AND MEMORY CONTROLLER CONTROL METHOD
Publication/Patent Number: EP3211536B1 Publication Date: 2019-09-04 Application Number: 15851846.4 Filing Date: 2015-07-22 Inventor: Shinbashi, Tatsuo   Tsutsui, Keiichi   Okubo, Hideaki   Sakai, Lui   Nakanishi, Kenichi   Fujinami, Yasushi   Assignee: Sony Corporation   IPC: G06F12/16
4 US10031865B2
Memory system, storage device, and method for controlling memory system
Publication/Patent Number: US10031865B2 Publication Date: 2018-07-24 Application Number: 15/527,374 Filing Date: 2015-10-08 Inventor: Tsutsui, Keiichi   Okubo, Hideaki   Sakai, Lui   Terada, Haruhiko   Assignee: SONY CORPORATION   IPC: G06F11/14 Abstract: To suppress the degradation of memory cells in a non-volatile memory. A read processing unit performs a read process for reading read data from each of a plurality of memory cells on the basis of a first threshold. An error detection unit detects presence or absence of an error in the read data and specifies memory cells in which the error is present among the plurality of memory cells. A re-read processing unit performs a re-read process for reading data, as re-read data, from the specified memory cells on the basis of a second threshold different from the first threshold. A refresh processing unit rewrites, for a memory cell of which the re-read data has a different value from the read data among the specified memory cells, data with the re-read data as a refresh process. To suppress the degradation of memory cells in a non-volatile memory. A read processing unit performs a read process for reading read data from each of a plurality of memory cells on the basis of a first threshold. An error detection unit detects presence or absence of an error ...More ...Less
5 US2018293025A1
INTERFACE CIRCUIT, MEMORY DEVICE, INFORMATION PROCESSING SYSTEM, AND INTERFACE CIRCUIT CONTROLLING METHOD
Publication/Patent Number: US2018293025A1 Publication Date: 2018-10-11 Application Number: 15/522,383 Filing Date: 2015-10-08 Inventor: Sakai, Lui   Shibahara, Yoshiyuki   Yoshida, Tetsuo   Kakioka, Hidenobu   Terada, Haruhiko   Assignee: SONY CORPORATION   IPC: G06F3/06 Abstract: To enable data to be transferred between a memory and a memory controller with accuracy. A memory-side interface circuit synchronizes a first periodic signal having a greater number of cycles than a number of pieces of unit data obtained by dividing read data read from a memory cell by a predetermined unit with the unit data and to sequentially transmit the first periodic signal and the unit data. A controller-side interface circuit sequentially holds the transmitted unit data in holding units of a plurality of stages in synchronization with the periodic signal and sequentially reads and outputs the held unit data in synchronization with a second periodic signal. To enable data to be transferred between a memory and a memory controller with accuracy. A memory-side interface circuit synchronizes a first periodic signal having a greater number of cycles than a number of pieces of unit data obtained by dividing read data read from a memory ...More ...Less
6 US2017329724A1
MEMORY SYSTEM, STORAGE DEVICE, AND METHOD FOR CONTROLLING MEMORY SYSTEM
Publication/Patent Number: US2017329724A1 Publication Date: 2017-11-16 Application Number: 15/527,374 Filing Date: 2015-10-08 Inventor: Terada, Haruhiko   Sakai, Lui   Okubo, Hideaki   Tsutsui, Keiichi   Assignee: SONY CORPORATION   IPC: G06F12/16 Abstract: To suppress the degradation of memory cells in a non-volatile memory. A read processing unit performs a read process for reading read data from each of a plurality of memory cells on the basis of a first threshold. An error detection unit detects presence or absence of an error in the read data and specifies memory cells in which the error is present among the plurality of memory cells. A re-read processing unit performs a re-read process for reading data, as re-read data, from the specified memory cells on the basis of a second threshold different from the first threshold. A refresh processing unit rewrites, for a memory cell of which the re-read data has a different value from the read data among the specified memory cells, data with the re-read data as a refresh process. To suppress the degradation of memory cells in a non-volatile memory. A read processing unit performs a read process for reading read data from each of a plurality of memory cells on the basis of a first threshold. An error detection unit detects presence or absence of an error ...More ...Less