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1
WO2020004075A1
RECEPTION DEVICE AND RECEPTION METHOD
Publication/Patent Number: WO2020004075A1 Publication Date: 2020-01-02 Application Number: 2019023691 Filing Date: 2019-06-14 Inventor: Sakai, Lui   Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION   IPC: H04N21/438 Abstract: This technology relates to a reception device and a reception method which make it possible to shorten the time that elapses before transmission control information is acquired. Provided is a reception device equipped with a control unit which, when a physical layer frame including transmission control information in a plurality of code words is received, performs control for confirming success of decoding while sequentially shifting a code to be decoded from among the plurality of code words code sequence by code sequence, and acquiring the transmission control information included in the plurality of code words obtained as a result of the decoding. This technology is applicable, for example, to data transmission corresponding to a predetermined broadcast system.
2
WO2020003701A1
RECEPTION DEVICE, COMMUNICATION SYSTEM, AND RECEPTION DEVICE CONTROL METHOD
Publication/Patent Number: WO2020003701A1 Publication Date: 2020-01-02 Application Number: 2019016400 Filing Date: 2019-04-17 Inventor: Sakai, Lui   Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION   IPC: H04L27/26 Abstract: The purpose of the invention is to shorten the delay time before the start of decoding in a reception device that receives and decodes a frame. This reception device is provided with a reception unit and a head position acquisition unit. The reception unit receives a frame that includes a plurality of pieces of divided data obtained by dividing a block sequence in which a predetermined number of encoded blocks are arranged and that also includes the tail position of the last encoded block in the last piece of divided data of the plurality of pieces of divided data. The head position acquisition unit acquires the head position of the encoded blocks in a particular piece of divided data among the plurality of pieces of divided data on the basis of the tail position.
3
US10635528B2
Memory controller and method of controlling memory controller
Publication/Patent Number: US10635528B2 Publication Date: 2020-04-28 Application Number: 15/323,574 Filing Date: 2015-05-20 Inventor: Shinbashi, Tatsuo   Sakai, Lui   Ikegaya, Ryoji   Assignee: SONY CORPORATION   IPC: G11C29/52 Abstract: A utilization efficiency of a memory is improved. A codeword generation unit generates a codeword in an error detection and correction code from data to be encoded. A write control unit writes one of data obtained by inverting the codeword and the codeword into the memory cell as write data. A read data error correction unit reads out the write data from the memory cell as read data, and corrects an error in the read data. An inversion data error correction unit corrects an error in inversion data obtained by inverting the read data. A correction data output unit, when the number of errors of either only one of the read data and the inversion data does not exceed an error correction capability of the error detection and correction code, selects and outputs the one where the error is corrected as correction data.
4
US10545804B2
Memory controller, memory system, and memory controller control method
Publication/Patent Number: US10545804B2 Publication Date: 2020-01-28 Application Number: 15/507,413 Filing Date: 2015-07-22 Inventor: Shinbashi, Tatsuo   Tsutsui, Keiichi   Okubo, Hideaki   Sakai, Lui   Nakanishi, Kenichi   Fujinami, Yasushi   Assignee: Sony Corporation   IPC: G06F11/00 Abstract: [Object] To sufficiently reduce frequency of error occurrence in memory cells. [Solution] A reading unit reads read data from a memory cell, the read data including an information bit and reversal information for determining whether or not the information bit has been reversed. In addition, an error detection/correction unit detects the presence or absence of an error in the information bit and corrects the error. A data reversing unit reverses the information bit that has the error corrected and the reversal information. Furthermore, a writing unit writes the reversed information bit and the reversed reversal information in the memory cell.
5
WO2019239689A1
RECEPTION DEVICE, COMMUNICATION SYSTEM, AND RECEPTION METHOD
Publication/Patent Number: WO2019239689A1 Publication Date: 2019-12-19 Application Number: 2019015055 Filing Date: 2019-04-05 Inventor: Sakai, Lui   Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION   IPC: H04L27/26 Abstract: The present invention improves transmission efficiency in a communication system that transmits forward error correction (FEC) blocks. A reception device is equipped with a reception unit and a processing unit. The reception unit of the reception device receives divided data generated by dividing a series, in which a prescribed number of FEC blocks each having a prescribed size are arranged, using a division unit that differs from the aforementioned size. Also, the processing unit of the reception device performs a process for calculating, from the size and the division unit, the start positions of the FEC blocks in the divided data received by the reception unit.
6
WO2019003888A1
INFORMATION PROCESSING DEVICE AND METHOD
Publication/Patent Number: WO2019003888A1 Publication Date: 2019-01-03 Application Number: 2018022302 Filing Date: 2018-06-12 Inventor: Sakai, Lui   Yamamoto, Makiko   Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION   IPC: H03M13/19 Abstract: The present disclosure relates to an information processing device and method which allow an increase in circuit scale to be suppressed. Multiple pieces of information to be used for decoding are stored in mutually different regions of a storage unit, the regions for storing the pieces of information are shifted in accordance with decoding-related operations so as to correspond to shifts in a column direction of a check matrix for the decoding, the pieces of information are read from predetermined regions of the storage unit, the decoding-related operations are performed using the pieces of information read from the storage unit, the pieces of information are updated, and the updated pieces of information are rearranged so as to correspond to the shifts in the column direction of the check matrix and written into the predetermined regions of the storage unit. The present disclosure can be applied, for example, to an information processing device, a communication device, a reception device, an information processing method, or a program.
7
EP3211536B1
MEMORY CONTROLLER, MEMORY SYSTEM, AND MEMORY CONTROLLER CONTROL METHOD
Publication/Patent Number: EP3211536B1 Publication Date: 2019-09-04 Application Number: 15851846.4 Filing Date: 2015-07-22 Inventor: Shinbashi, Tatsuo   Tsutsui, Keiichi   Okubo, Hideaki   Sakai, Lui   Nakanishi, Kenichi   Fujinami, Yasushi   Assignee: Sony Corporation   IPC: G06F12/16
8
US10031865B2
Memory system, storage device, and method for controlling memory system
Publication/Patent Number: US10031865B2 Publication Date: 2018-07-24 Application Number: 15/527,374 Filing Date: 2015-10-08 Inventor: Tsutsui, Keiichi   Okubo, Hideaki   Sakai, Lui   Terada, Haruhiko   Assignee: SONY CORPORATION   IPC: G06F11/14 Abstract: To suppress the degradation of memory cells in a non-volatile memory. A read processing unit performs a read process for reading read data from each of a plurality of memory cells on the basis of a first threshold. An error detection unit detects presence or absence of an error in the read data and specifies memory cells in which the error is present among the plurality of memory cells. A re-read processing unit performs a re-read process for reading data, as re-read data, from the specified memory cells on the basis of a second threshold different from the first threshold. A refresh processing unit rewrites, for a memory cell of which the re-read data has a different value from the read data among the specified memory cells, data with the re-read data as a refresh process.
9
US2018293025A1
INTERFACE CIRCUIT, MEMORY DEVICE, INFORMATION PROCESSING SYSTEM, AND INTERFACE CIRCUIT CONTROLLING METHOD
Publication/Patent Number: US2018293025A1 Publication Date: 2018-10-11 Application Number: 15/522,383 Filing Date: 2015-10-08 Inventor: Sakai, Lui   Shibahara, Yoshiyuki   Yoshida, Tetsuo   Kakioka, Hidenobu   Terada, Haruhiko   Assignee: SONY CORPORATION   IPC: G06F3/06 Abstract: To enable data to be transferred between a memory and a memory controller with accuracy. A memory-side interface circuit synchronizes a first periodic signal having a greater number of cycles than a number of pieces of unit data obtained by dividing read data read from a memory cell by a predetermined unit with the unit data and to sequentially transmit the first periodic signal and the unit data. A controller-side interface circuit sequentially holds the transmitted unit data in holding units of a plurality of stages in synchronization with the periodic signal and sequentially reads and outputs the held unit data in synchronization with a second periodic signal.
10
US2017147433A1
MEMORY CONTROLLER AND METHOD OF CONTROLLING MEMORY CONTROLLER
Publication/Patent Number: US2017147433A1 Publication Date: 2017-05-25 Application Number: 15/323,574 Filing Date: 2015-05-20 Inventor: Shinbashi, Tatsuo   Sakai, Lui   Ikegaya, Ryoji   Assignee: SONY CORPORATION   IPC: G06F11/10 Abstract: A utilization efficiency of a memory is improved. A codeword generation unit generates a codeword in an error detection and correction code from data to be encoded. A write control unit writes one of data obtained by inverting the codeword and the codeword into the memory cell as write data. A read data error correction unit reads out the write data from the memory cell as read data, and corrects an error in the read data. An inversion data error correction unit corrects an error in inversion data obtained by inverting the read data. A correction data output unit, when the number of errors of either only one of the read data and the inversion data does not exceed an error correction capability of the error detection and correction code, selects and outputs the one where the error is corrected as correction data.
11
US2017329724A1
MEMORY SYSTEM, STORAGE DEVICE, AND METHOD FOR CONTROLLING MEMORY SYSTEM
Publication/Patent Number: US2017329724A1 Publication Date: 2017-11-16 Application Number: 15/527,374 Filing Date: 2015-10-08 Inventor: Terada, Haruhiko   Sakai, Lui   Okubo, Hideaki   Tsutsui, Keiichi   Assignee: SONY CORPORATION   IPC: G06F12/16 Abstract: To suppress the degradation of memory cells in a non-volatile memory. A read processing unit performs a read process for reading read data from each of a plurality of memory cells on the basis of a first threshold. An error detection unit detects presence or absence of an error in the read data and specifies memory cells in which the error is present among the plurality of memory cells. A re-read processing unit performs a re-read process for reading data, as re-read data, from the specified memory cells on the basis of a second threshold different from the first threshold. A refresh processing unit rewrites, for a memory cell of which the re-read data has a different value from the read data among the specified memory cells, data with the re-read data as a refresh process.
12
US9542270B2
Storage control device, storage device, information processing system and storage control method
Publication/Patent Number: US9542270B2 Publication Date: 2017-01-10 Application Number: 14/318,927 Filing Date: 2014-06-30 Inventor: Sakai, Lui   Tsutsui, Keiichi   Fujinami, Yasushi   Assignee: Sony Corporation   IPC: G11C29/00 Abstract: An error detection-correction unit reads system information for operating a system from a first memory and performs error detection-correction processing. A control unit supplies the system information to a host computer in a case where the error detection-correction processing is successful. In addition, the control unit reads a backup of the system information from a second memory that is different from the first memory and supplies the backup of the system information to the host computer in a case where the detection-correction processing fails.
13
EP2216908B1
BIT PERMUTATION PATTERN FOR BICM WITH A LDPC CODE OF RATE 5/6 AND A 4096QAM CONSTELLATION
Publication/Patent Number: EP2216908B1 Publication Date: 2017-08-30 Application Number: 08854263.4 Filing Date: 2008-11-26 Inventor: Yokokawa, Takashi   Sakai, Lui   Okada, Satoshi   Yamamoto, Makiko   Ikegaya, Ryoji   Assignee: Saturn Licensing LLC   IPC: H04L27/34 Abstract: The present invention relates to a data processing apparatus and a data processing method which can improve the tolerance to errors of data. A demultiplexer 25 replaces, in accordance with an allocation rule for allocating code bits of an LDPC code to symbol bits representative of symbols, mb bits from among the code bits and sets the code bits after the replacement as symbol bits of b symbols. According to the allocation rule, where groups into which the code bits and the symbol bits are to be grouped in response to an error probability thereof are set as code bit groups and symbol bit groups, respectively, a combination of any of the code bit groups and the symbol bit group of the symbol bits to which the code bits of the code bit group are to be allocated and bit numbers of the code bits and the symbols bits are prescribed.