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No. Publication Number Title Publication/Patent Number Publication/Patent Number Publication Date Publication Date
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1
US201894976A1
Spectrometers with Self-Compensation of Rotational Misalignment
Publication/Patent Number: US201894976A1 Publication Date: 2018-04-05 Application Number: 20/171,582 Filing Date: 2017-11-22 Inventor: Saraswat, Krishna C   Na, Yeul   Lee, Jae Hyung   Na, Yeul   Assignee: Stratio   IPC: G01J3/28 Abstract: An apparatus for analyzing light includes an input aperture for receiving light; a first set of one or more lenses configured to relay light from the input aperture; and a prism assembly configured to disperse light from the first set of one or more lenses. The prism assembly includes a plurality of prisms that includes a first prism, a second prism that is distinct from the first prism, and a third prism that is distinct from the first prism and the second prism. The first prism is mechanically coupled with the second prism and the second prism is mechanically coupled with the third prism. The apparatus also includes a second set of one or more lenses configured to focus the dispersed light from the prism assembly; and an array detector configured for converting the light from the second set of one or more lenses to electrical signals.
2
US9595812B2
Crossed nanobeam structure for a low-threshold germanium laser
Publication/Patent Number: US9595812B2 Publication Date: 2017-03-14 Application Number: 14/747,756 Filing Date: 2015-06-23 Inventor: Nam, Donguk   Petykiewicz, Jan A.   Sukhdeo, Devanand S.   Gupta, Shashank   Vuckovic, Jelena   Saraswat krishna c   Assignee: The Board of Trustees of the Leland Stanford Junior University   IPC: H01S5/32 Abstract: A crossed nanobeam structure for strain engineering in semiconductor devices is provided. For example, such a structure can be used for a low-threshold germanium laser. While the photonic crystal nanobeam enables light confinement in a subwavelength volume with small optical loss, another crossing nanobeam induces high tensile strain in the small region where the optical mode is tightly confined. As maintaining a small optical loss and a high tensile strain reduces the required pumping for achieving net optical gain beyond cavity losses, this technique can be used to develop an extremely low-threshold Ge laser source. Moreover, the structure can be easily integrated into electronic and photonic circuits.
3
US9343608B2
Depletion-mode field-effect transistor-based phototransistor
Publication/Patent Number: US9343608B2 Publication Date: 2016-05-17 Application Number: 14/461,038 Filing Date: 2014-08-15 Inventor: Na, Yeul   Saraswat, Krishna C   Assignee: Board of Regents, The University of Texas System   IPC: H01L31/112 Abstract: A depletion-mode phototransitor is disclosed. The phototransistor having a substrate, a gate, a source, a drain and a channel. The source, drain and channel are doped to be the same type of semiconductor. The substrate can be made of silicon and/or germanium. The gate can be made of either aluminum or polysilicon.
4
WO2015077477A1
SOLAR CELLS HAVING SELECTIVE CONTACTS AND THREE OR MORE TERMINALS
Publication/Patent Number: WO2015077477A1 Publication Date: 2015-05-28 Application Number: 2014066664 Filing Date: 2014-11-20 Inventor: Saraswat, Krishna C   Nainani, Aneesh   Islam, Raisul   Shine, Gautam   Assignee: The Board of Trustees of the Leland Stanford Junior University   IPC: H01L31/04 Abstract: Junction-less solar cells having three or more terminals are provided. Electron- and hole- selective contacts and interfaces are used in combination with two more absorber layers having different bandgaps to provide multi-material solar cells that have no requirement for either lattice matching or current matching.
5
US2015136214A1
Solar cells having selective contacts and three or more terminals
Publication/Patent Number: US2015136214A1 Publication Date: 2015-05-21 Application Number: 14/549,235 Filing Date: 2014-11-20 Inventor: Islam, Raisul   Shine, Gautam   Nainani, Aneesh   Saraswat krishna c   Assignee: The Board of Trustees of the Leland Stanford Junior University   IPC: H01L31/0224 Abstract: Junction-less solar cells having three or more terminals are provided. Electron- and hole-selective contacts and interfaces are used in combination with two or more absorber layers having different bandgaps to provide multi-material solar cells that have no requirement for either lattice matching or current matching.
6
US2015372455A1
Crossed Nanobeam Structure for a Low-Threshold Germanium Laser
Publication/Patent Number: US2015372455A1 Publication Date: 2015-12-24 Application Number: 14/747,756 Filing Date: 2015-06-23 Inventor: Nam, Donguk   Petykiewicz, Jan A.   Sukhdeo, Devanand S.   Gupta, Shashank   Vuckovic, Jelena   Saraswat krishna c   Assignee: The Board of Trustees of the Leland Stanford Junior University   IPC: H01S5/32 Abstract: A crossed nanobeam structure for strain engineering in semiconductor devices is provided. For example, such a structure can be used for a low-threshold germanium laser. While the photonic crystal nanobeam enables light confinement in a subwavelength volume with small optical loss, another crossing nanobeam induces high tensile strain in the small region where the optical mode is tightly confined. As maintaining a small optical loss and a high tensile strain reduces the required pumping for achieving net optical gain beyond cavity losses, this technique can be used to develop an extremely low-threshold Ge laser source. Moreover, the structure can be easily integrated into electronic and photonic circuits.
7
US2014363917A1
DEPLETION-MODE FIELD-EFFECT TRANSISTOR-BASED PHOTOTRANSISTOR
Publication/Patent Number: US2014363917A1 Publication Date: 2014-12-11 Application Number: 14/461,038 Filing Date: 2014-08-15 Inventor: Na, Yeul   Saraswat krishna c   Assignee: The Board of Trustees of the Leland Stanford Junior University   IPC: H01L31/112 Abstract: A depletion-mode phototransitor is disclosed. The phototransistor having a substrate, a gate, a source, a drain and a channel. The source, drain and channel are doped to be the same type of semiconductor. The substrate can be made of silicon and/or germanium. The gate can be made of either aluminum or polysilicon.
8
US8896083B2
Depletion-mode field-effect transistor-based phototransitor
Publication/Patent Number: US8896083B2 Publication Date: 2014-11-25 Application Number: 13/835,662 Filing Date: 2013-03-15 Inventor: Na, Yeul   Saraswat krishna c   Assignee: Board of Regents, The University of Texas System   IPC: H01L31/06 Abstract: A depletion-mode phototransitor is disclosed. The phototransistor having a substrate, a gate, a source, a drain and a channel. The source, drain and channel are doped to be the same type of semiconductor. The substrate can be made of silicon and/or germanium. The gate can be made of either aluminum or polysilicon.
9
US2014264501A1
DEPLETION-MODE FIELD-EFFECT TRANSISTOR-BASED PHOTOTRANSITOR
Publication/Patent Number: US2014264501A1 Publication Date: 2014-09-18 Application Number: 13/835,662 Filing Date: 2013-03-15 Inventor: Na, Yeul   Saraswat krishna c   Assignee: SEMICONDUCTOR RESEARCH CORPORATION   IPC: H01L31/062 Abstract: A depletion-mode phototransitor is disclosed. The phototransistor having a substrate, a gate, a source, a drain and a channel. The source, drain and channel are doped to be the same type of semiconductor. The substrate can be made of silicon and/or germanium. The gate can be made of either aluminum or polysilicon.
10
US2014308801A1
Anything on Glass
Publication/Patent Number: US2014308801A1 Publication Date: 2014-10-16 Application Number: 14/251,164 Filing Date: 2014-04-11 Inventor: Lee, Jae Hyung   Jung, Woo Shik   Saraswat krishna c   Assignee: The Board of Trustees of the Leland Stanford Junior University   IPC: H01L21/18 Abstract: Bonding of one or more semiconductor layers to a glass substrate is facilitated by depositing spin-on-glass (SOG) on the top of the semiconductor layers. The SOG is then bonded to the glass substrate, and after that, the original substrate of the semiconductor layers is removed. The resulting structure has the semiconductor layers disposed on the glass substrate with a layer of SOG sandwiched between. Bonding is always between glass and glass, and is independent of the composition of the target layers. Thus, it can provide “anything on glass”. For example, X-on-insulator (XOI), where X can be silicon, germanium, GaAs, GaN, SiC, graphene, etc. The spin-on-glass also helps with the surface roughness requirement.
11
US7919381B2
Germanium substrate-type materials and approach therefor
Publication/Patent Number: US7919381B2 Publication Date: 2011-04-05 Application Number: 12/719,796 Filing Date: 2010-03-08 Inventor: Nayfeh, Ammar Munir   Chui, Chi On   Saraswat krishna c   Yonehara, Takao   Assignee: Canon Kabushiki Kaisha   The Board of Trustees of the Leland Stanford Junior University   IPC: H01L21/76 Abstract: Germanium circuit-type structures are facilitated. In one example embodiment, a multi-step growth and anneal process is implemented to grow Germanium (Ge) containing material, such as heteroepitaxial-Germanium, on a substrate including Silicon (Si) or Silicon-containing material. In certain applications, defects are generally confined near a Silicon/Germanium interface, with defect threading to an upper surface of the Germanium containing material generally being inhibited. These approaches are applicable to a variety of devices including Germanium MOS capacitors, pMOSFETs and optoelectronic devices.
12
US7772078B2
Germanium substrate-type materials and approach therefor
Publication/Patent Number: US7772078B2 Publication Date: 2010-08-10 Application Number: 12/198,838 Filing Date: 2008-08-26 Inventor: Nayfeh, Ammar Munir   Chui, Chi On   Saraswat krishna c   Yonehara, Takao   Assignee: The Board of Trustees of the Leland Stanford Junior University   Canon Kabushiki Kaisha   IPC: H01L21/76 Abstract: Germanium circuit-type structures are facilitated. In one example embodiment, a multi-step growth and anneal process is implemented to grow Germanium (Ge) containing material, such as heteroepitaxial-Germanium, on a substrate including Silicon (Si) or Silicon-containing material. In certain applications, defects are generally confined near a Silicon/Germanium interface, with defect threading to an upper surface of the Germanium containing material generally being inhibited. These approaches are applicable to a variety of devices including Germanium MOS capacitors, pMOSFETs and optoelectronic devices.
13
US2010159678A1
GERMANIUM SUBSTRATE-TYPE MATERIALS AND APPROACH THEREFOR
Publication/Patent Number: US2010159678A1 Publication Date: 2010-06-24 Application Number: 12/719,796 Filing Date: 2010-03-08 Inventor: Nayfeh, Ammar Munir   Chui, Chi On   Saraswat krishna c   Yonehara, Takao   Assignee: CANON KABUSHIKI KAISHA   The Board of Trustees of the Leland Stanford Junior University   IPC: H01L21/20 Abstract: Germanium circuit-type structures are facilitated. In one example embodiment, a multi-step growth and anneal process is implemented to grow Germanium (Ge) containing material, such as heteroepitaxial-Germanium, on a substrate including Silicon (Si) or Silicon-containing material. In certain applications, defects are generally confined near a Silicon/Germanium interface, with defect threading to an upper surface of the Germanium containing material generally being inhibited. These approaches are applicable to a variety of devices including Germanium MOS capacitors, pMOSFETs and optoelectronic devices.
14
US7495313B2
Germanium substrate-type materials and approach therefor
Publication/Patent Number: US7495313B2 Publication Date: 2009-02-24 Application Number: 11/188,140 Filing Date: 2005-07-22 Inventor: Nayfeh, Ammar Munir   Chui, Chi On   Saraswat krishna c   Yonehara, Takao   Assignee: Board of Trustees of the Leland Stanford Junior University   Canon Kabushiki Kaisha   IPC: H01L27/082 Abstract: Germanium circuit-type structures are facilitated. In one example embodiment, a multi-step growth and anneal process is implemented to grow Germanium (Ge) containing material, such as heteroepitaxial-Germanium, on a substrate including Silicon (Si) or Silicon-containing material. In certain applications, defects are generally confined near a Silicon/Germanium interface, with defect threading to an upper surface of the Germanium containing material generally being inhibited. These approaches are applicable to a variety of devices including Germanium MOS capacitors, pMOSFETs and optoelectronic devices.
15
US2009061604A1
GERMANIUM SUBSTRATE-TYPE MATERIALS AND APPROACH THEREFOR
Publication/Patent Number: US2009061604A1 Publication Date: 2009-03-05 Application Number: 12/198,838 Filing Date: 2008-08-26 Inventor: Nayfeh, Ammar Munir   Chui, Chi On   Saraswat krishna c   Yonehara, Takao   Assignee: CANON KABUSHIKI KAISHA   The Board of Trustees of the Leland Stanford Junior University   IPC: H01L21/205 Abstract: Germanium circuit-type structures are facilitated. In one example embodiment, a multi-step growth and anneal process is implemented to grow Germanium (Ge) containing material, such as heteroepitaxial-Germanium, on a substrate including Silicon (Si) or Silicon-containing material. In certain applications, defects are generally confined near a Silicon/Germanium interface, with defect threading to an upper surface of the Germanium containing material generally being inhibited. These approaches are applicable to a variety of devices including Germanium MOS capacitors, pMOSFETs and optoelectronic devices.
16
WO2006012544A3
GERMANIUM SUBSTRATE-TYPE MATERIALS AND APPROACH THEREFOR
Publication/Patent Number: WO2006012544A3 Publication Date: 2007-09-13 Application Number: 2005026113 Filing Date: 2005-07-22 Inventor: Yonehara, Takao   Chui, Chi On   Saraswat, Krishna C   Nayfeh, Ammar Munir   Assignee: Canon Kabushiki Kaisha   The Board of Trustees of the Leland Stanford Junior University   IPC: C03B25/04 Abstract: Germanium circuit-type structures are facilitated. In one example embodiment
17
US7271458B2
High-k dielectric for thermodynamically-stable substrate-type materials
Publication/Patent Number: US7271458B2 Publication Date: 2007-09-18 Application Number: 10/404,876 Filing Date: 2003-03-31 Inventor: Chui, Chi On   Saraswat krishna c   Triplett, Baylor B.   Mcintyre, Paul   Assignee: The Board of Trustees of the LeLand Stanford Junior University   IPC: H01L29/76 Abstract: Excellent capacitor-voltage characteristics with near-ideal hysteresis are realized in a capacitive-like structure that uses an electrode substrate-type material with a high-k dielectric layer having a thickness of a few-to-several Angstroms capacitance-based SiO2 equivalent (“TOx, Eq”). According to one particular example embodiment, a semiconductor device structure has an electrode substrate-type material having a Germanium-rich surface material. The electrode substrate-type material is processed to provide this particular electrode surface material in a form that is thermodynamically stable with a high-k dielectric material. A dielectric layer is then formed over the electrode surface material with the high-k dielectric material at a surface that faces, lies against and is thermodynamically stable with the electrode surface material.
18
WO2006012544A2
GERMANIUM SUBSTRATE-TYPE MATERIALS AND APPROACH THEREFOR
Publication/Patent Number: WO2006012544A2 Publication Date: 2006-02-02 Application Number: 2005026113 Filing Date: 2005-07-22 Inventor: Yonehara, Takao   Chui, Chi On   Saraswat, Krishna C   Nayfeh, Ammar Munir   Assignee: Canon Kabushiki Kaisha   The Board of Trustees of the Leland Stanford Junior University   IPC: C03B25/04 Abstract: Germanium circuit-type structures are facilitated. In one example embodiment
19
AU2002305179A1
HIGH-K DIELECTRIC FOR THERMODYNAMICALLY-STABLE SUBSTRATE-TYPE MATERIALS
Publication/Patent Number: AU2002305179A1 Publication Date: 2003-11-11 Application Number: 2002305179 Filing Date: 2002-04-15 Inventor: Chui, Chi On   Saraswat, Krishna C   Triplett, Baylor B   Assignee: Stanford University   CHUI, CHI, ON   Saraswat krishna c   TRIPLETT, BAYLOR, B.   IPC: H01L21/28
20
WO03096390A1
HIGH-K DIELECTRIC FOR THERMODYNAMICALLY-STABLE SUBSTRATE-TYPE MATERIALS
Publication/Patent Number: WO03096390A1 Publication Date: 2003-11-20 Application Number: 0211785 Filing Date: 2002-04-15 Inventor: Chui, Chi On   Saraswat, Krishna C   Triplett, Baylor B   Assignee: Stanford University   CHUI, CHI, ON   Saraswat krishna c   TRIPLETT, BAYLOR, B.   IPC: H01L21/28 Abstract: Excellent capacitor-voltage characteristics with near-ideal hysteresis are realized in a capacitive-like structure that uses an electrode substrate-type material with a hi-k dielectric layer having a thickness of a few-to-several Angstroms capacitance-based SiO2 equivalent ('TOX
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