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No. Publication Number Title Publication/Patent Number Publication/Patent Number Publication Date Publication Date
Application Number Application Number Filing Date Filing Date
Inventor Inventor Assignee Assignee IPC IPC
1
US10943936B2
Method of producing an optical sensor at wafer-level and optical sensor
Publication/Patent Number: US10943936B2 Publication Date: 2021-03-09 Application Number: 16/316,724 Filing Date: 2017-08-08 Inventor: Toschkoff, Gregor   Bodner, Thomas   Schrank, Franz   Assignee: AMS AG   IPC: H01L27/146 Abstract: A method is proposed to produce an optical sensor at wafer-level, the methods comprises the following steps. A wafer is provided and has a main top surface and a main back surface. At or near the top surface of the wafer at least one integrated circuit is arranged having a light sensitive component. A first mold tool is placed over the at least one integrated circuit such that at least one channel remains between the first mold tool and the top surface to enter a first mold material. A first mold structure is formed by wafer-level molding the first mold material via the at least one channel. The first mold material creates at least one runner structure. A second mold tool is placed over the first mold structure and a second mold structure is formed by wafer-level molding a second mold material by means of the second mold tool. A light path blocking structure is arranged on the top surface to block light from entering via the at least one runner structure.
2
EP2889901B1
Semiconductor device with through-substrate via and corresponding method
Publication/Patent Number: EP2889901B1 Publication Date: 2021-02-03 Application Number: 13199683.7 Filing Date: 2013-12-27 Inventor: Schrank, Franz   Carniello, Sara   Enichlmair, Hubert   Kraft, Jochen   Löffler, Bernhard   Holzhaider, Rainer   Assignee: ams AG   IPC: H01L21/768
3
EP3301425B1
PRESSURE SENSOR DEVICE AND METHOD FOR FORMING A PRESSURE SENSOR DEVICE
Publication/Patent Number: EP3301425B1 Publication Date: 2021-01-20 Application Number: 16196616.3 Filing Date: 2016-10-31 Inventor: Siegert, Jörg   Besling, Willem Frederik Adrianus   Tak, Coenraad Cornelis   Schrems, Martin   Schrank, Franz   Assignee: Sciosense B.V.   IPC: G01L19/04
4
US2021020511A1
METHOD OF FORMING A THROUGH-SUBSTRATE VIA AND A SEMICONDUCTOR DEVICE COMPRISING A THROUGH-SUBSTRATE VIA
Publication/Patent Number: US2021020511A1 Publication Date: 2021-01-21 Application Number: 16/980,197 Filing Date: 2019-04-03 Inventor: Kraft, Jochen   Parteder, Georg   Jessenig, Stefan   Schrank, Franz   Siegert, Jörg   Assignee: ams AG   IPC: H01L21/768 Abstract: A substrate is provided with a dielectric, a metal layer embedded in the dielectric, and a metallic layer arranged on the metal layer between the substrate and the metal layer. A via hole is formed in the substrate and in a region of the dielectric that is between the substrate and the metal layer. An insulation layer is applied in the via hole and removed from above a contact area of the metal layer, and the metallic layer is completely removed from the contact area. A metallization is applied in the via hole on the contact area.
5
EP2573829B1
Light emitting diode module
Publication/Patent Number: EP2573829B1 Publication Date: 2020-04-22 Application Number: 12198155.9 Filing Date: 2007-10-16 Inventor: Schrank, Franz   Hoschopf, Hans   Assignee: Tridonic Jennersdorf GmbH   Lumitech Patentverwertung GmbH   IPC: H01L33/48
6
EP2573829B8
Light emitting diode module
Publication/Patent Number: EP2573829B8 Publication Date: 2020-06-10 Application Number: 12198155.9 Filing Date: 2007-10-16 Inventor: Schrank, Franz   Hoschopf, Hans   Assignee: Tridonic GmbH & Co. KG   Lumitech Patentverwertung GmbH   IPC: H01L33/48
7
US10734534B2
Method of producing an optical sensor at wafer-level and optical sensor
Publication/Patent Number: US10734534B2 Publication Date: 2020-08-04 Application Number: 15/746,342 Filing Date: 2016-07-22 Inventor: Etschmaier, Harald   Toschkoff, Gregor   Bodner, Thomas   Schrank, Franz   Assignee: ams AG   IPC: H01L31/0203 Abstract: A method of producing an optical sensor at wafer-level, comprising the steps of providing a wafer having a main top surface and a main back surface and arrange at or near the top surface of the wafer at least one first integrated circuit having at least one light sensitive component. Furthermore, providing in the wafer at least one through-substrate via for electrically contacting the top surface and back surface and forming a first mold structure by wafer-level molding a first mold material over the top surface of the wafer, such that the first mold structure at least partly encloses the first integrated circuit. Finally, forming a second mold structure by wafer-level molding a second mold material over the first mold structure, such that the second mold structure at least partly encloses the first mold structure.
8
US2020243387A1
METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
Publication/Patent Number: US2020243387A1 Publication Date: 2020-07-30 Application Number: 16/754,323 Filing Date: 2018-10-11 Inventor: Bodner, Thomas   Jessenig, Stefan   Schrank, Franz   Assignee: ams AG   IPC: H01L21/768 Abstract: A method for manufacturing a semiconductor device comprises the steps of providing a semiconductor body with a main plane of extension, and forming a trench in the semiconductor body from a top side of the semiconductor body in a vertical direction which is perpendicular to the main plane of extension of the semiconductor body. The method further comprises the steps of coating inner walls of the trench with an isolation layer, depositing a metallization layer within the trench, and depositing a passivation layer within the trench such that an inner volume of the trench is free of any material, wherein inner surfaces that are adjacent to the inner volume are treated to be hydrophobic at least in places. Furthermore, a semiconductor device is provided.
9
US10644047B2
Optoelectronic device with a refractive element and a method of producing such an optoelectronic device
Publication/Patent Number: US10644047B2 Publication Date: 2020-05-05 Application Number: 16/069,802 Filing Date: 2016-12-15 Inventor: Hofrichter, Jens   Schrank, Franz   Siegert, Joerg   Assignee: ams AG   IPC: H01L27/146 Abstract: A top surface of a substrate is provided with a detection element for detecting electromagnetic radiation. A refractive element is formed by a portion of a cover element, which is attached to the substrate, so that the refractive element is arranged facing the detection element. The refractive element may be arranged within a recess of the cover element, so that a cavity is formed between the detection element and the refraction element.
10
EP3193368B1
AN OPTOELECTRONIC DEVICE WITH A REFRACTIVE ELEMENT AND A METHOD OF PRODUCING SUCH AN OPTOELECTRONIC DEVICE
Publication/Patent Number: EP3193368B1 Publication Date: 2020-03-18 Application Number: 16151134.0 Filing Date: 2016-01-13 Inventor: Hofrichter, Jens   Schrank, Franz   Siegert, Jörg   Assignee: ams AG   IPC: H01L27/146
11
EP2665096B1
A METHOD OF WAFER-SCALE INTEGRATION OF SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICE
Publication/Patent Number: EP2665096B1 Publication Date: 2020-04-22 Application Number: 12168069.8 Filing Date: 2012-05-15 Inventor: Cassidy, Cathal   Siegert, Jörg   Schrank, Franz   Assignee: ams AG   IPC: H01L27/146
12
EP3024029B1
Method of producing a semiconductor device comprising an aperture array
Publication/Patent Number: EP3024029B1 Publication Date: 2020-04-22 Application Number: 14193859.7 Filing Date: 2014-11-19 Inventor: Siegert, Jörg   Schrank, Franz   Schrems, Martin   Assignee: ams AG   IPC: H01L27/146
13
EP3660902A1
SEMICONDUCTOR DEVICE COMPRISING AN APERTURE ARRAY
Publication/Patent Number: EP3660902A1 Publication Date: 2020-06-03 Application Number: 20152454.3 Filing Date: 2014-11-19 Inventor: Siegert, Jörg   Schrank, Franz   Schrems, Martin   Assignee: AMS AG   IPC: H01L27/146 Abstract: A photosensor (2) is arranged in a semiconductor substrate (1) at a main surface (10), a dielectric layer (4) is arranged on or above the main surface, the dielectric layer including a metal layer (6) electrically connected with the photosensor, and an aperture layer (16) formed from an opaque or semitransparent material is arranged on or above the dielectric layer. The aperture layer is provided with an array of transparent aperture zones (18) above the photosensor, each of the aperture zones penetrating the aperture layer.
14
EP3471132B1
METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
Publication/Patent Number: EP3471132B1 Publication Date: 2020-02-26 Application Number: 17196160.0 Filing Date: 2017-10-12 Inventor: Bodner, Thomas   Jessenig, Stefan   Schrank, Franz   Assignee: ams AG   IPC: H01L21/768
15
EP2908335B1
Dicing method
Publication/Patent Number: EP2908335B1 Publication Date: 2020-04-15 Application Number: 14155240.6 Filing Date: 2014-02-14 Inventor: Schrank, Franz   Schrems, Martin   Stering, Bernhard   Assignee: ams AG   IPC: H01L21/768
16
US2020168772A1
LED/LD ILLUMINATION DEVICE WITH SEPARATE LUMINOPHORE CONFIGURATION, AND METHOD FOR PRODUCING SAME
Publication/Patent Number: US2020168772A1 Publication Date: 2020-05-28 Application Number: 16/627,823 Filing Date: 2018-05-24 Inventor: Riemer, Steffen   Schrank, Franz   Uitz, Patrick   Brugger, Wilhelm   Irran, Thomas   Assignee: Tridonic Jennersdorf GmbH   W&H Dentalwerk Bürmoos GmbH   IPC: H01L33/50 Abstract: The invention relates to an illuminating device (1) comprising a substrate (2), a non-transparent spacer (4) which is connected to the substrate (2) so as to be hermetically sealed, an opening in the spacer (4), opposite said substrate (2), and an illumination element (3) positioned beneath the spacer (4) and beneath the opening, which element is connected to the substrate (2) so as to be hermetically sealed, characterized in that the opening in the spacer (4) is closed, so as to be hermetically sealed, by an optical element (5) consisting of a glass material the volume of which comprises at least one luminophore and thus constitutes a luminescent composite glass material.
17
US10847664B2
Optical package and method of producing an optical package
Publication/Patent Number: US10847664B2 Publication Date: 2020-11-24 Application Number: 15/773,539 Filing Date: 2016-11-04 Inventor: Mehrl, David   Bodner, Thomas   Toschkoff, Gregor   Etschmaier, Harald   Schrank, Franz   Assignee: AMS AG   IPC: H01L31/0232 Abstract: An optical package is proposed comprising a carrier, an optoelectronic component, an aspheric lens, and a reflective layer. The carrier comprises electrical interconnections and the optoelectric component is arranged for emitting and/or detecting electromagnetic radiation in a specified wavelength range. Furthermore, the optoelectric component is mounted on the carrier or integrated into the carrier and electrically connected to the electric interconnections. The aspheric lens has an upper surface, a lateral surface, and a bottom surface and the bottom surface is arranged on or near the optoelectric component. The aspheric lens comprises a material which is at least transparent in the specified wavelength range. The reflective layer comprises a reflective material, wherein the reflective layer at least partly covers the lateral surface of the aspheric lens, and wherein the reflective material is at least partly reflective in the specified wavelength range.
18
US202020611A1
Semiconductor Device
Publication/Patent Number: US202020611A1 Publication Date: 2020-01-16 Application Number: 20/181,648 Filing Date: 2018-02-14 Inventor: Singulani, Anderson   Kraft, Jochen   Parteder, Georg   Coppeta, Raffaele   Schrank, Franz   Assignee: ams AG   IPC: H01L23/528 Abstract: A semiconductor device comprises a semiconductor body and an electrically conductive via which extends through at least a part of the semiconductor body, where the via has a lateral size which is given in a first lateral direction that is perpendicular to a vertical direction given by the main axis of extension of the via and where the via has a top side and a bottom side that faces away from the top side. The semiconductor device further comprises an electrically conductive etch-stop layer arranged at the bottom side of the via in a plane which is parallel to the first lateral direction, and at least one electrically conductive contact layer at the bottom side of the via in a plane which is parallel to the first lateral direction. The lateral extent in the first lateral direction of the etch-stop layer is larger than the lateral size of the via and the lateral extent in the first lateral direction of the contact layer is smaller than the lateral size of the via. Furthermore, the etch-stop layer is arranged between the electrically conductive via and the contact layer in the vertical direction.
19
EP3651680A1
LED/LD ILLUMINATION DEVICE WITH SEPARATE LUMINOPHORE CONFIGURATION, AND METHOD FOR PRODUCING SAME
Publication/Patent Number: EP3651680A1 Publication Date: 2020-05-20 Application Number: 18727772.8 Filing Date: 2018-05-24 Inventor: Riemer, Steffen   Schrank, Franz   Uitz, Patrick   Brugger, Wilhelm   Irran, Thomas   Assignee: Tridonic Jennersdorf GmbH   W & H Dentalwerk Bürmoos GmbH   IPC: A61C1/08
20
US2020020611A1
Semiconductor Device
Publication/Patent Number: US2020020611A1 Publication Date: 2020-01-16 Application Number: 16/483,884 Filing Date: 2018-02-14 Inventor: Kraft, Jochen   Parteder, Georg   Singulani, Anderson   Coppeta, Raffaele   Schrank, Franz   Assignee: ams AG   IPC: H01L23/48 Abstract: A semiconductor device comprises a semiconductor body and an electrically conductive via which extends through at least a part of the semiconductor body, where the via has a lateral size which is given in a first lateral direction that is perpendicular to a vertical direction given by the main axis of extension of the via and where the via has a top side and a bottom side that faces away from the top side. The semiconductor device further comprises an electrically conductive etch-stop layer arranged at the bottom side of the via in a plane which is parallel to the first lateral direction, and at least one electrically conductive contact layer at the bottom side of the via in a plane which is parallel to the first lateral direction. The lateral extent in the first lateral direction of the etch-stop layer is larger than the lateral size of the via and the lateral extent in the first lateral direction of the contact layer is smaller than the lateral size of the via. Furthermore, the etch-stop layer is arranged between the electrically conductive via and the contact layer in the vertical direction.
Total 19 pages