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No. Publication Number Title Publication/Patent Number Publication/Patent Number Publication Date Publication Date
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21
US2020313031A1
METHOD FOR MANUFACTURING AN OPTICAL SENSOR AND OPTICAL SENSOR
Publication/Patent Number: US2020313031A1 Publication Date: 2020-10-01 Application Number: 16/756,025 Filing Date: 2018-10-15 Inventor: Toschkoff, Gregor   Bodner, Thomas   Schrank, Franz   Labodi, Miklos   Siegert, Joerg   Schrems, Martin   Assignee: ams AG   IPC: H01L31/18 Abstract: A method for manufacturing an optical sensor is provided. The method comprises providing an optical sensor arrangement which comprises at least two optical sensor elements on a carrier, where the optical sensor arrangement comprises a light entrance surface at the side of the optical sensor elements facing away from the carrier. The method further comprises forming a trench between two optical sensor elements in a vertical direction which is perpendicular to the main plane of extension of the carrier, where the trench extends from the light entrance surface of the sensor arrangement at least to the carrier. Moreover, the method comprises coating the trench with an opaque material, forming electrical contacts for the at least two optical sensor elements on a back side of the carrier facing away from the optical sensor elements, and forming at least one optical sensor by dicing the optical sensor arrangement along the trench. Each optical sensor comprises an optical sensor element, and the light entrance surface is free of electrical contacts and at least partially free of the opaque material above the optical sensor elements. Furthermore, an optical sensor is provided.
22
EP3550600B1
METHOD OF FORMING A THROUGH-SUBSTRATE VIA AND SEMICONDUCTOR DEVICE COMPRISING THE THROUGH-SUBSTRATE VIA
Publication/Patent Number: EP3550600B1 Publication Date: 2020-08-05 Application Number: 18165692.7 Filing Date: 2018-04-04 Inventor: Kraft, Jochen   Parteder, Georg   Jessenig, Stefan   Schrank, Franz   Siegert, Jörg   Assignee: ams AG   IPC: H01L21/768
23
DE102017211727A1
Gebondete LED-Chips in einer Polymermatrix
Publication/Patent Number: DE102017211727A1 Publication Date: 2019-01-10 Application Number: 102017211727 Filing Date: 2017-07-10 Inventor: Schrank, Franz   Assignee: TRIDONIC JENNERSDORF GMBH   IPC: H01L33/56 Abstract: Beleuchtungsvorrichtung (1) aufweisend- einen Träger (2);- zumindest zwei LED-Chips (3) die mit dem Träger (2) mechanisch verbunden und über Bonddrähte (4) mit dem Träger und/oder mit einem benachbarten LED-Chip (3) elektrisch kontaktiert sind;- ein im Bereich der LED-Chips (3) vergossener und ausgehärteter Verguss (7), aufweisend eine Matrix, in die vorzugsweise Farbkonversionspartikel und/oder Streupartikel eingebettet sind.Die Beleuchtungsvorrichtung (1) ist dadurch gekennzeichnet, dass zwischen dem Verguss (7) und den Oberflächen der Komponenten- Träger (2)- Bonddrähte (4) und- LED-Chips (3) eine im Wesentlichem zusammenhängende Pufferschicht (8) existiert, die das Vergussmaterial (7) von den Oberflächen der genannten Komponenten (2),(4),(3) mechanisch entkoppelt und die mechanische Belastung der Bonddrähte verringert.
24
EP2290716B1
LED module
Publication/Patent Number: EP2290716B1 Publication Date: 2019-06-12 Application Number: 10184330.8 Filing Date: 2007-10-16 Inventor: Schrank, Franz   Hoschopf, Hans   Assignee: Tridonic Jennersdorf GmbH   Lumitech Patentverwertung GmbH   IPC: H01L33/50
25
US10340254B2
Method of producing an interposer-chip-arrangement for dense packaging of chips
Publication/Patent Number: US10340254B2 Publication Date: 2019-07-02 Application Number: 15/726,905 Filing Date: 2017-10-06 Inventor: Kraft, Jochen   Schrems, Martin   Schrank, Franz   Assignee: ams AG   IPC: H01L21/00 Abstract: The method of producing an interposer-chip-arrangement, comprises providing an interposer (1) with an integrated circuit (25), arranging a dielectric layer (2) with metal layers embedded in the dielectric layer above a main surface (10) of the interposer, connecting the integrated circuit with at least one of the metal layers, forming an interconnection (7) through the interposer, the interconnection contacting one of the metal layers, arranging a further dielectric layer (3) above a further main surface (11) of the interposer opposite the main surface and arranging a further metal layer in or on the further dielectric layer, the further metal layer being connected with the interconnection, arranging a chip provided with at least one contact pad at the main surface or at the further main surface, and electrically conductively connecting the contact pad with the interconnection.
26
US2019165020A1
METHOD OF PRODUCING AN OPTICAL SENSOR AT WAFER-LEVEL AND OPTICAL SENSOR
Publication/Patent Number: US2019165020A1 Publication Date: 2019-05-30 Application Number: 16/316,724 Filing Date: 2017-08-08 Inventor: Toschkoff, Gregor   Bodner, Thomas   Schrank, Franz   Assignee: ams AG   IPC: H01L27/146 Abstract: A method is proposed to produce an optical sensor at wafer-level, the methods comprises the following steps. A wafer is provided and has a main top surface and a main back surface. At or near the top surface of the wafer at least one integrated circuit is arranged having a light sensitive component. A first mold tool is placed over the at least one integrated circuit such that at least one channel remains between the first mold tool and the top surface to enter a first mold material. A first mold structure is formed by wafer-level molding the first mold material via the at least one channel. The first mold material creates at least one runner structure. A second mold tool is placed over the first mold structure and a second mold structure is formed by wafer-level molding a second mold material by means of the second mold tool. A light path blocking structure is arranged on the top surface to block light from entering via the at least one runner structure.
27
EP2881983B1
Interposer-chip-arrangement for dense packaging of chips
Publication/Patent Number: EP2881983B1 Publication Date: 2019-09-18 Application Number: 13198854.5 Filing Date: 2013-12-20 Inventor: Kraft, Jochen   Schrank, Franz   Schrems, Martin   Assignee: ams AG   IPC: H01L21/60
28
US201935835A1
AN OPTOELECTRONIC DEVICE WITH A REFRACTIVE ELEMENT AND A METHOD OF PRODUCING SUCH AN OPTOELECTRONIC DEVICE
Publication/Patent Number: US201935835A1 Publication Date: 2019-01-31 Application Number: 20/161,606 Filing Date: 2016-12-15 Inventor: Schrank, Franz   Hofrichter, Jens   Siegert, Joerg   Assignee: ams AG   IPC: H01L31/0232 Abstract: A top surface of a substrate is provided with a detection element for detecting electromagnetic radiation. A refractive element is formed by a portion of a cover element, which is attached to the substrate, so that the refractive element is arranged facing the detection element. The refractive element may be arranged within a recess of the cover element, so that a cavity is formed between the detection element and the refraction element.
29
US10283541B2
Semiconductor device comprising an aperture array and method of producing such a semiconductor device
Publication/Patent Number: US10283541B2 Publication Date: 2019-05-07 Application Number: 15/528,089 Filing Date: 2015-11-09 Inventor: Siegert, Joerg   Schrank, Franz   Schrems, Martin   Assignee: ams AG   IPC: H01L27/146 Abstract: A photosensor (2) is arranged in a semiconductor substrate (1) at a main surface (10), a dielectric layer (4) is arranged on or above the main surface, the dielectric layer including a metal layer (6) electrically connected with the photosensor, and an aperture layer (16) formed from an opaque or semitransparent material is arranged on or above the dielectric layer. The aperture layer is provided with an array of transparent aperture zones (18) above the photosensor, each of the aperture zones penetrating the aperture layer.
30
US10332931B2
Semiconductor device for wafer-scale integration
Publication/Patent Number: US10332931B2 Publication Date: 2019-06-25 Application Number: 15/455,055 Filing Date: 2017-03-09 Inventor: Cassidy, Cathal   Siegert, Joerg   Schrank, Franz   Assignee: ams AG   IPC: H01L27/146 Abstract: The semiconductor device comprises a semiconductor wafer with an integrated circuit, formed by a plurality of dies, a further semiconductor wafer, which differs from the semiconductor wafer in diameter and semiconductor material, the semiconductor wafer and the further semiconductor wafer being bonded to one another by means of a bonding layer, and an electrically conductive contact layer arranged on the further semiconductor wafer opposite to the bonding layer.
31
EP2881753B1
Optical sensor arrangement and method of producing an optical sensor arrangement
Publication/Patent Number: EP2881753B1 Publication Date: 2019-03-06 Application Number: 13199086.3 Filing Date: 2013-12-20 Inventor: Schrank, Franz   Dierschke, Eugene G.   Schrems, Martin   Assignee: ams AG   IPC: G01S7/481
32
US10256147B2
Dicing method
Publication/Patent Number: US10256147B2 Publication Date: 2019-04-09 Application Number: 15/118,836 Filing Date: 2015-02-09 Inventor: Schrems, Martin   Stering, Bernhard   Schrank, Franz   Assignee: ams AG   IPC: H01L21/78 Abstract: The dicing method comprises the steps of providing a substrate (1) of semiconductor material, the substrate having a main surface (10), where integrated components (3) of chips (13) are arranged, and a rear surface (11) opposite the main surface, fastening a first handling wafer above the main surface, thinning the substrate at the rear surface, and forming trenches (20) penetrating the substrate and separating the chips by a single etching step after the substrate has been thinned.
33
US2019035835A1
AN OPTOELECTRONIC DEVICE WITH A REFRACTIVE ELEMENT AND A METHOD OF PRODUCING SUCH AN OPTOELECTRONIC DEVICE
Publication/Patent Number: US2019035835A1 Publication Date: 2019-01-31 Application Number: 16/069,802 Filing Date: 2016-12-15 Inventor: Hofrichter, Jens   Schrank, Franz   Siegert, Joerg   Assignee: ams AG   IPC: H01L27/146 Abstract: A top surface of a substrate is provided with a detection element for detecting electromagnetic radiation. A refractive element is formed by a portion of a cover element, which is attached to the substrate, so that the refractive element is arranged facing the detection element. The refractive element may be arranged within a recess of the cover element, so that a cavity is formed between the detection element and the refraction element.
34
EP3471132A1
METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
Publication/Patent Number: EP3471132A1 Publication Date: 2019-04-17 Application Number: 17196160.0 Filing Date: 2017-10-12 Inventor: Bodner, Thomas   Jessenig, Stefan   Schrank, Franz   Assignee: ams AG   IPC: H01L21/768 Abstract: A method for manufacturing a semiconductor device (10) comprises the steps of providing a semiconductor body (11) with a main plane of extension, and forming a trench (12) in the semiconductor body (11) from a top side (13) of the semiconductor body (11) in a vertical direction (z) which is perpendicular to the main plane of extension of the semiconductor body (11). The method further comprises the steps of coating inner walls (14) of the trench (12) with an isolation layer (15), depositing a metallization layer (16) within the trench (12), and depositing a passivation layer (17) within the trench (12) such that an inner volume (18) of the trench (12) is free of any material, wherein inner surfaces (19) that are adjacent to the inner volume (18) are treated to be hydrophobic at least in places. Furthermore, a semiconductor device (10) is provided.
35
WO2019072970A1
METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
Publication/Patent Number: WO2019072970A1 Publication Date: 2019-04-18 Application Number: 2018077743 Filing Date: 2018-10-11 Inventor: Schrank, Franz   Jessenig, Stefan   Bodner, Thomas   Assignee: AMS AG   IPC: H01L23/48 Abstract: A method for manufacturing a semiconductor device (10) comprises the steps of providing a semiconductor body (11) with a main plane of extension, and forming a trench (12) in the semiconductor body (11) from a top side (13) of the semiconductor body (11) in a vertical direction (z) which is perpendicular to the main plane of extension of the semiconductor body (11). The method further comprises the steps of coating inner walls (14) of the trench (12) with an isolation layer (15), depositing a metallization layer (16) within the trench (12), and depositing a passivation layer (17) within the trench (12) such that an inner volume (18) of the trench (12) is free of any material, wherein inner surfaces (19) that are adjacent to the inner volume (18) are treated to be hydrophobic at least in places. Furthermore, a semiconductor device (10) is provided.
36
WO2019211041A1
SEMICONDUCTOR DEVICE WITH THROUGH-SUBSTRATE VIA
Publication/Patent Number: WO2019211041A1 Publication Date: 2019-11-07 Application Number: 2019056964 Filing Date: 2019-03-20 Inventor: Schrank, Franz   Kraft, Jochen   Parteder, Georg   Singulani, Anderson   Coppeta, Raffaele   Assignee: AMS AG   IPC: H01L23/48 Abstract: A semiconductor device (10) comprises a semiconductor body (11), an electrically conductive via (12) which extends through at least a part of the semiconductor body (11), and where the via (12) has a top side (13) and a bottom side (14) that faces away from the top side (13), an electrically conductive etch-stop layer (15) arranged at the bottom side (14) of the via (12) in a plane which is parallel to a lateral direction (x), where the lateral direction (x) is perpendicular to a vertical direction (z) given by the main axis of extension of the via (12), and at least one electrically conductive contact layer (16) at the bottom side (14) of the via (12) in a plane which is parallel to the lateral direction (x). The etch-stop layer (16) is arranged between the electrically conductive via (12) and the contact layer (16) in the vertical direction (z), the lateral extent in the lateral direction (x) of the etch-stop layer (15) amounts to at least 2.5 times the lateral extent of the via (12) in the lateral direction (x), and the lateral extent of the contact layer (16) is smaller than the lateral extent of the via (12) or the lateral extent of the contact layer (16) amounts to at least 2.5 times the lateral extent of the via (12).
37
US10243017B2
Sensor chip stack and method of producing a sensor chip stack
Publication/Patent Number: US10243017B2 Publication Date: 2019-03-26 Application Number: 15/636,545 Filing Date: 2017-06-28 Inventor: Parteder, Georg   Kraft, Jochen   Schrank, Franz   Troxler, Thomas   Fitzi, Andreas   Assignee: ams International AG   IPC: H01L27/146 Abstract: The sensor chip stack comprises a sensor substrate of a semiconductor material including a sensor, a chip fastened to the sensor substrate, the chip including an integrated circuit, electric interconnections between the sensor substrate and the chip, electric terminals of the chip, the chip being arranged between the electric terminals and the sensor substrate, and a molding material arranged adjacent to the chip, the electric terminals of the chip being free from the molding material.
38
DE102017212030A1
LED/LD-Beleuchtungsvorrichtung mit neuartiger Remote-Leuchtstoff-Konfiguration und Verfahren zur Herstellung einer solchen
Publication/Patent Number: DE102017212030A1 Publication Date: 2019-01-17 Application Number: 102017212030 Filing Date: 2017-07-13 Inventor: Schrank, Franz   Brugger, Wilhelm   Riemer, Steffen   Irran, Thomas   Uitz, Patrick   Assignee: TRIDONIC JENNERSDORF GMBH   W & H DENTALWERK BÜRMOOS GMBH   IPC: F21V9/40 Abstract: Beleuchtungsvorrichtung (1) aufweisend ein Substrat (2), einen nicht transparenten Abstandhalter (4), welcher mit dem Substrat (2) hermetisch dicht verbunden ist, eine dem Substrat (2) gegenüberliegende Öffnung in dem Abstandhalter (4), ein unter dem Abstandhalter (4) und unter der Öffnung befindliches Leuchtelement (3), welches mit dem Substrat (2) hermetisch dicht verbunden ist, dadurch gekennzeichnet, dass die Öffnung des Abstandhalters (4) mit einem optischen Element (5) aus einem Glasmaterial, dessen Volumen mindestens einen Leuchtstoff aufweist und als solches einen lumineszierenden Glasverbundwerkstoff darstellt, hermetisch dicht verschlossen ist.
39
EP3166146B1
OPTICAL PACKAGE AND METHOD OF PRODUCING AN OPTICAL PACKAGE
Publication/Patent Number: EP3166146B1 Publication Date: 2019-04-17 Application Number: 15198468.9 Filing Date: 2015-12-08 Inventor: Mehrl, David   Bodner, Thomas   Toschkoff, Gregor   Etschmaier, Harald   Schrank, Franz   Assignee: ams AG   IPC: H01L25/16 Abstract: An optical package is proposed comprising a carrier (4), an optoelectronic component (2), an aspheric lens (1), and a reflective layer (3). The carrier (4) comprises electrical interconnections (5) and the optoelectric component (2) is arranged for emitting and/or detecting electromagnetic radiation in a specified wavelength range. Furthermore, the optoelectric component (2) is mounted on the carrier (4) or integrated into the carrier (4) and electrically connected to the electric interconnections (5). The aspheric lens (1) has an upper surface (11), a lateral surface (12), and a bottom surface (13) and the bottom surface (13) is arranged on or near the optoelectric component (2). The aspheric lens (1) comprises a material which is at least transparent in the specified wavelength range. The reflective layer (3) comprises a reflective material, wherein the reflective layer at least partly covers the lateral surface (12) of the aspheric lens (1), and wherein the reflective material is at least partly reflective in the specified wavelength range.
40
EP3564994A1
SEMICONDUCTOR DEVICE WITH THROUGH-SUBSTRATE VIA
Publication/Patent Number: EP3564994A1 Publication Date: 2019-11-06 Application Number: 18170639.1 Filing Date: 2018-05-03 Inventor: Kraft, Dr. Jochen   Parteder, Georg   Singulani, Anderson   Coppeta, Raffaele   Schrank, Franz   Assignee: ams AG   IPC: H01L23/48 Abstract: A semiconductor device (10) comprises a semiconductor body (11), an electrically conductive via (12) which extends through at least a part of the semiconductor body (11), and where the via (12) has a top side (13) and a bottom side (14) that faces away from the top side (13), an electrically conductive etch-stop layer (15) arranged at the bottom side (14) of the via (12) in a plane which is parallel to a lateral direction (x), where the lateral direction (x) is perpendicular to a vertical direction (z) given by the main axis of extension of the via (12), and at least one electrically conductive contact layer (16) at the bottom side (14) of the via (12) in a plane which is parallel to the lateral direction (x). The etch-stop layer (16) is arranged between the electrically conductive via (12) and the contact layer (16) in the vertical direction (z), the lateral extent in the lateral direction (x) of the etch-stop layer (15) amounts to at least 2.5 times the lateral extent of the via (12) in the lateral direction (x), and the lateral extent of the contact layer (16) is smaller than the lateral extent of the via (12) or the lateral extent of the contact layer (16) amounts to at least 2.5 times the lateral extent of the via (12) .
Total 19 pages