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Application Number Application Number |
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Inventor Inventor | Assignee Assignee |
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81 | EP3123531A1 |
LED MODULE HAVING AN INTEGRATED SECONDARY OPTICAL UNIT
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Publication/Patent Number: EP3123531A1 | Publication Date: 2017-02-01 | Application Number: 15707321.4 | Filing Date: 2015-02-25 | Inventor： Pfeiler-deutschmann, Martin Wimmer, Florian Schrank, Franz | Assignee: Tridonic Jennersdorf GmbH | IPC: H01L33/50 | ||||
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82 | US2017179183A1 |
SEMICONDUCTOR DEVICE FOR WAFER-SCALE INTEGRATION
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Publication/Patent Number: US2017179183A1 | Publication Date: 2017-06-22 | Application Number: 15/455,055 | Filing Date: 2017-03-09 | Inventor： Cassidy, Cathal Siegert, Joerg Schrank, Franz | Assignee: ams AG | IPC: H01L27/146 | Abstract: The semiconductor device comprises a semiconductor wafer with an integrated circuit, formed by a plurality of dies, a further semiconductor wafer, which differs from the semiconductor wafer in diameter and semiconductor material, the semiconductor wafer and the further semiconductor wafer being bonded to one another by means of a bonding layer, and an electrically conductive contact layer arranged on the further semiconductor wafer opposite to the bonding layer. | |||
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83 | US9735101B2 |
Semiconductor device with through-substrate via covered by a solder ball
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Publication/Patent Number: US9735101B2 | Publication Date: 2017-08-15 | Application Number: 15/283,183 | Filing Date: 2016-09-30 | Inventor： Cassidy, Cathal Schrems, Martin Schrank, Franz | Assignee: AMS AG | IPC: H01L23/48 | Abstract: The semiconductor device comprises a semiconductor substrate (10) with a metallization (111) having an upper terminal layer (22) located at a front side (20) of the substrate. The metallization forms a through-substrate via (23) from the upper terminal layer to a rear terminal layer (13) located opposite to the front side at a rear side (21) of the substrate. The through-substrate via comprises an annular cavity (18) and a void (101), which may be filled with air or another gas. A solder ball (100) closes the void without completely filling it. A variety of interconnections for three-dimensional integration is offered by this scheme. | |||
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84 | US9608035B2 |
Method of wafer-scale integration of semiconductor devices and semiconductor device
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Publication/Patent Number: US9608035B2 | Publication Date: 2017-03-28 | Application Number: 14/401,499 | Filing Date: 2013-04-05 | Inventor： Cassidy, Cathal Siegert, Joerg Schrank, Franz | Assignee: AMS AG | IPC: H01L27/146 | Abstract: The method of wafer-scale integration of semiconductor devices comprises the steps of providing a semiconductor wafer (1), a further semiconductor wafer (2), which differs from the first semiconductor wafer in at least one of diameter, thickness and semiconductor material, and a handling wafer (3), arranging the further semiconductor wafer on the handling wafer, and bonding the further semiconductor wafer to the semiconductor wafer. The semiconductor device may comprise an electrically conductive contact layer (6) arranged on the further semiconductor wafer (2) and a metal layer connecting the contact layer with an integrated circuit. | |||
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85 | US2017309665A1 |
SEMICONDUCTOR DEVICE COMPRISING AN APERTURE ARRAY AND METHOD OF PRODUCING SUCH A SEMICONDUCTOR DEVICE
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Publication/Patent Number: US2017309665A1 | Publication Date: 2017-10-26 | Application Number: 15/528,089 | Filing Date: 2015-11-09 | Inventor： Siegert, Joerg Schrank, Franz Schrems, Martin | Assignee: ams AG | IPC: H01L27/146 | Abstract: A photosensor (2) is arranged in a semiconductor substrate (1) at a main surface (10), a dielectric layer (4) is arranged on or above the main surface, the dielectric layer including a metal layer (6) electrically connected with the photosensor, and an aperture layer (16) formed from an opaque or semitransparent material is arranged on or above the dielectric layer. The aperture layer is provided with an array of transparent aperture zones (18) above the photosensor, each of the aperture zones penetrating the aperture layer. | |||
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86 | US2017062277A1 |
DICING METHOD
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Publication/Patent Number: US2017062277A1 | Publication Date: 2017-03-02 | Application Number: 15/118,836 | Filing Date: 2015-02-09 | Inventor： Schrems, Martin Stering, Bernhard Schrank, Franz | Assignee: ams AG | IPC: H01L21/78 | Abstract: The dicing method comprises the steps of providing a substrate (1) of semiconductor material, the substrate having a main surface (10), where integrated components (3) of chips (13) are arranged, and a rear surface (11) opposite the main surface, fastening a first handling wafer above the main surface, thinning the substrate at the rear surface, and forming trenches (20) penetrating the substrate and separating the chips by a single etching step after the substrate has been thinned. | |||
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87 | US2017018518A1 |
METHOD OF PRODUCING A SEMICONDUCTOR DEVICE WITH THROUGH-SUBSTRATE VIA COVERED BY A SOLDER BALL
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Publication/Patent Number: US2017018518A1 | Publication Date: 2017-01-19 | Application Number: 15/283,189 | Filing Date: 2016-09-30 | Inventor： Cassidy, Cathal Schrems, Martin Schrank, Franz | Assignee: ams AG | IPC: H01L23/00 | Abstract: A semiconductor substrate is provided with a through-substrate via comprising a metallization and an opening. A solder ball is placed on the opening. A reflow of the solder ball is performed in such a way that the solder ball closes the through-substrate via and leaves a void in the through-substrate via. | |||
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88 | KR101791765B1 |
SEMICONDUCTOR DEVICE FOR DETECTION OF RADIATION AND METHOD OF PRODUCING A SEMICONDUCTOR DEVICE FOR DETECTION OF RADIATION
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Publication/Patent Number: KR101791765B1 | Publication Date: 2017-10-30 | Application Number: 20157026638 | Filing Date: 2014-02-24 | Inventor： Schrank, Franz Siegert, Joerg Enichlmair, Hubert | Assignee: AMS AG | IPC: H01L23/48 | Abstract: 방사선 검출용 반도체 장치는 | |||
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89 | US9773729B2 |
Method of producing a semiconductor device with through-substrate via covered by a solder ball
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Publication/Patent Number: US9773729B2 | Publication Date: 2017-09-26 | Application Number: 15/283,189 | Filing Date: 2016-09-30 | Inventor： Cassidy, Cathal Schrems, Martin Schrank, Franz | Assignee: ams AG | IPC: H01L21/44 | Abstract: A semiconductor substrate is provided with a through-substrate via comprising a metallization and an opening. A solder ball is placed on the opening. A reflow of the solder ball is performed in such a way that the solder ball closes the through-substrate via and leaves a void in the through-substrate via. | |||
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90 | WO2017013256A1 |
METHOD OF PRODUCING AN OPTICAL SENSOR AT WAFER-LEVEL AND OPTICAL SENSOR
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Publication/Patent Number: WO2017013256A1 | Publication Date: 2017-01-26 | Application Number: 2016067563 | Filing Date: 2016-07-22 | Inventor： Schrank, Franz Toschkoff, Gregor Etschmaier, Harald Bodner, Thomas | Assignee: AMS AG | IPC: H01L31/0203 | Abstract: A method of producing an optical sensor at wafer-level | |||
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91 | EP3166146A1 |
OPTICAL PACKAGE AND METHOD OF PRODUCING AN OPTICAL PACKAGE
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Publication/Patent Number: EP3166146A1 | Publication Date: 2017-05-10 | Application Number: 15198468.9 | Filing Date: 2015-12-08 | Inventor： Mehrl, David Bodner, Thomas Toschkoff, Gregor Etschmaier, Harald Schrank, Franz | Assignee: ams AG | IPC: H01L25/16 | Abstract: An optical package is proposed comprising a carrier (4), an optoelectronic component (2), an aspheric lens (1), and a reflective layer (3). The carrier (4) comprises electrical interconnections (5) and the optoelectric component (2) is arranged for emitting and/or detecting electromagnetic radiation in a specified wavelength range. Furthermore, the optoelectric component (2) is mounted on the carrier (4) or integrated into the carrier (4) and electrically connected to the electric interconnections (5). The aspheric lens (1) has an upper surface (11), a lateral surface (12), and a bottom surface (13) and the bottom surface (13) is arranged on or near the optoelectric component (2). The aspheric lens (1) comprises a material which is at least transparent in the specified wavelength range. The reflective layer (3) comprises a reflective material, wherein the reflective layer at least partly covers the lateral surface (12) of the aspheric lens (1), and wherein the reflective material is at least partly reflective in the specified wavelength range. | |||
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92 | DE102016201890A1 |
LED-Lichtquelle mit Übertemperaturschutz
Title (English):
Led light source with high temperature protection
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Publication/Patent Number: DE102016201890A1 | Publication Date: 2017-08-10 | Application Number: 102016201890 | Filing Date: 2016-02-09 | Inventor： Schrank, Franz Fink, Bernhard KÖberl, Karl Kusterle, Peter | Assignee: TRIDONIC JENNERSDORF GMBH | IPC: F21V25/10 | Abstract: Bei einer LED-Lichtquelle (100) mit einem ringartigen Gehäuse (10) | |||
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93 | WO2017077051A1 |
OPTICAL PACKAGE AND METHOD OF PRODUCING AN OPTICAL PACKAGE
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Publication/Patent Number: WO2017077051A1 | Publication Date: 2017-05-11 | Application Number: 2016076695 | Filing Date: 2016-11-04 | Inventor： Schrank, Franz Mehrl, David Bodner, Thomas Etschmaier, Harald Toschkoff, Gregor | Assignee: AMS AG | IPC: H01L25/16 | Abstract: An optical package is proposed comprising a carrier (4) | |||
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94 | US2016343757A1 |
SEMICONDUCTOR DEVICE FOR OPTICAL APPLICATIONS AND METHOD OF PRODUCING SUCH A SEMICONDUCTOR DEVICE
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Publication/Patent Number: US2016343757A1 | Publication Date: 2016-11-24 | Application Number: 15/114,387 | Filing Date: 2015-01-14 | Inventor： Enichlmair, Hubert Schrank, Franz | Assignee: ams AG | IPC: H01L27/146 | Abstract: A sensor (2) is arranged at a main surface (10) of a semiconductor substrate (1), and a filter (3) is arranged above the sensor. A through-substrate via (4) penetrates the substrate outside the region of the sensor. A semiconductor body is applied above the main surface and then partially removed at least in an area above the sensor. A portion of the semiconductor body remains above the through-substrate via as a frame layer (5). The filter is on a level with the frame layer. | |||
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95 | US2016186937A1 |
LED MODULE, LED ILLUMINATION MEANS, AND LED LAMP FOR THE ENERGY-EFFICIENT REPRODUCTION OF WHITE LIGHT
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Publication/Patent Number: US2016186937A1 | Publication Date: 2016-06-30 | Application Number: 14/944,065 | Filing Date: 2015-11-17 | Inventor： Baumgartner, Erwin Schrank, Franz | Assignee: LUMITECH PRODUKTION UND ENTWICKLUNG GMBH | IPC: F21K99/00 | Abstract: An LED module, selectively comprising at least zero, one, or a plurality of LEDs from Group B and/or Group G and/or Group R and at least one or more LEDs from Group P. The concentration of phosphors/phosphor mixtures of the LEDs in Group P is selected such that the photometric efficiency (lm/W) thereof is at or near the maximum as a function of the CIE x-coordinates. | |||
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96 | EP2741322B1 |
Semiconductor device with integrated hot plate and recessed substrate and method of production
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Publication/Patent Number: EP2741322B1 | Publication Date: 2016-04-27 | Application Number: 12196321.9 | Filing Date: 2012-12-10 | Inventor： Schrank, Franz Schrems, Martin | Assignee: ams AG | IPC: H01L23/34 | Abstract: The semiconductor device comprises a substrate (1) of semiconductor material, a dielectric layer (2) on the substrate, an electrically conductive contact pad (3) arranged in the dielectric layer, a hot plate (4) arranged in the dielectric layer, a recess (9) of the substrate at the location of the hot plate, and an integrated circuit (18), which operates the hot plate. An electrically conductive layer (14) is arranged on a side of the substrate opposite the dielectric layer. The substrate is provided with a via hole (8) above the contact pad, and an electrically conductive material (12) connecting the electrically conductive layer with the contact pad is applied in the via hole. The recess (9) and the via hole (8) are formed in the same process step. | |||
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97 | EP3024029A1 |
Semiconductor device comprising an aperture array and method of producing such a semiconductor device
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Publication/Patent Number: EP3024029A1 | Publication Date: 2016-05-25 | Application Number: 14193859.7 | Filing Date: 2014-11-19 | Inventor： Siegert, Jörg Schrank, Franz Schrems, Martin | Assignee: ams AG | IPC: H01L27/146 | Abstract: A photosensor (2) is arranged in a semiconductor substrate (1) at a main surface (10), a dielectric layer (4) is arranged on or above the main surface, the dielectric layer including a metal layer (6) electrically connected with the photosensor, and an aperture layer (16) formed from an opaque or semitransparent material is arranged on or above the dielectric layer. The aperture layer is provided with an array of transparent aperture zones (18) above the photosensor, each of the aperture zones penetrating the aperture layer. | |||
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98 | US2016306042A1 |
OPTICAL SENSOR ARRANGEMENT AND METHOD OF PRODUCING AN OPTICAL SENSOR ARRANGEMENT
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Publication/Patent Number: US2016306042A1 | Publication Date: 2016-10-20 | Application Number: 15/101,893 | Filing Date: 2014-12-03 | Inventor： Schrank, Franz Dierschke, Eugene G. Schrems, Martin | Assignee: AMS AG | IPC: G01S17/02 | Abstract: An optical sensor arrangement, in particular an optical proximity sensor arrangement comprises a three-dimensional integrated circuit further comprising a first layer comprising a light-emitting device, a second layer comprising a light-detector and a driver circuit. The driver circuit is electrically connected to the light-emitting device and to the light-detector to control the operation of the light-emitting device and the light-detector. A mold layer comprising a first light-barrier between the light-emitting device and the light-detector configured to block light from being transmitted directly from the light-emitting device to the light-detector. | |||
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99 | WO2016078950A1 |
SEMICONDUCTOR DEVICE COMPRISING AN APERTURE ARRAY AND METHOD OF PRODUCING SUCH A SEMICONDUCTOR DEVICE
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Publication/Patent Number: WO2016078950A1 | Publication Date: 2016-05-26 | Application Number: 2015076063 | Filing Date: 2015-11-09 | Inventor： Schrank, Franz Schrems, Martin Siegert, JÖrg | Assignee: AMS AG | IPC: G02F1/1335 | Abstract: A photosensor (2) is arranged in a semiconductor substrate (1) at a main surface (10) | |||
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100 | EP2854167B1 |
Semiconductor device with through-substrate via covered by a solder ball and related method of production
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Publication/Patent Number: EP2854167B1 | Publication Date: 2016-01-20 | Application Number: 14176547.9 | Filing Date: 2011-11-23 | Inventor： Cassidy, Cathal Schrems, Martin Schrank, Franz | Assignee: ams AG | IPC: H01L23/00 | Abstract: The semiconductor device comprises a semiconductor substrate (10) with a metallization (111) having an upper terminal layer (22) located at a front side (20) of the substrate. The metallization forms a through-substrate via (23) from the upper terminal layer to a rear terminal layer (13) located opposite to the front side at a rear side (21) of the substrate. The through-substrate via comprises a void (101), which may be filled with air or another gas and forms an annular cavity surrounding a pillar (105). A solder ball (100) closes the void without completely filling it. A variety of interconnections for threedimensional integration is offered by this scheme. |
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