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121 | KR20150122751A |
SEMICONDUCTOR DEVICE FOR DETECTION OF RADIATION AND METHOD OF PRODUCING A SEMICONDUCTOR DEVICE FOR DETECTION OF RADIATION
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Publication/Patent Number: KR20150122751A | Publication Date: 2015-11-02 | Application Number: 20157026638 | Filing Date: 2014-02-24 | Inventor： Schrank, Franz Siegert, Joerg Enichlmair, Hubert | Assignee: AMS AG | IPC: H01L23/48 | Abstract: 방사선 검출용 반도체 장치는 | |||
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122 | EP2908335A1 |
Dicing method
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Publication/Patent Number: EP2908335A1 | Publication Date: 2015-08-19 | Application Number: 14155240.6 | Filing Date: 2014-02-14 | Inventor： Schrank, Franz Schrems, Martin Stering, Bernhard | Assignee: ams AG | IPC: H01L21/768 | Abstract: The dicing method comprises the steps of providing a substrate (1) of semiconductor material, the substrate having a main surface (10), where integrated components (3) of chips (13) are arranged, and a rear surface (11) opposite the main surface, fastening a first handling wafer above the main surface, thinning the substrate at the rear surface, and forming trenches (20) penetrating the substrate and separating the chips by a single etching step after the substrate has been thinned. | |||
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123 | EP2881983A1 |
Interposer-chip-arrangement for dense packaging of chips
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Publication/Patent Number: EP2881983A1 | Publication Date: 2015-06-10 | Application Number: 13198854.5 | Filing Date: 2013-12-20 | Inventor： Kraft, Jochen Schrank, Franz Schrems, Martin | Assignee: ams AG | IPC: H01L23/00 | Abstract: The interposer-chip-arrangement comprises an interposer (1), metal layers arranged above a main surface (10), a further metal layer arranged above a further main surface (11) opposite the main surface, an electrically conductive interconnection (7) through the interposer, the interconnection connecting one of the metal layers and the further metal layer, a chip (12) arranged at the main surface or at the further main surface, the chip having a contact pad (15), which is electrically conductively connected with the interconnection, a dielectric layer (2) arranged above the main surface with the metal layers embedded in the dielectric layer, a further dielectric layer (3) arranged above the further main surface with the further metal layer embedded in the further dielectric layer, and an integrated circuit (25) in the interposer, the integrated circuit being connected with at least one of the metal layers (5). | |||
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124 | EP2913848A1 |
Dicing method
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Publication/Patent Number: EP2913848A1 | Publication Date: 2015-09-02 | Application Number: 14157035.8 | Filing Date: 2014-02-27 | Inventor： Stering, Bernhard Schrank, Franz Schrems, Martin | Assignee: ams AG | IPC: H01L21/78 | Abstract: The dicing method comprises the steps of providing a substrate (1) of semiconductor material, which has a main surface (10), where integrated components (3) are arranged, and a rear surface (11) opposite the main surface, forming trenches (20) in the substrate from the main surface by etching, and forming rear trenches (21) in the substrate from the rear surface by sawing, according to the location of the trenches, thus dividing the substrate into chips (13). The trenches are formed with a lateral width (w) of typically less than 20 µm, the rear trenches are formed with a further lateral width (W), and the lateral width is smaller than the further lateral width. | |||
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125 | WO2015121198A1 |
DICING METHOD
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Publication/Patent Number: WO2015121198A1 | Publication Date: 2015-08-20 | Application Number: 2015052645 | Filing Date: 2015-02-09 | Inventor： Schrank, Franz Schrems, Martin Stering, Bernhard | Assignee: AMS AG | IPC: H01L21/768 | Abstract: The dicing method comprises the steps of providing a substrate (1) of semiconductor material | |||
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126 | EP2693467B1 |
A method of producing a semiconductor device having an interconnect through the substrate
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Publication/Patent Number: EP2693467B1 | Publication Date: 2015-11-18 | Application Number: 12178878.0 | Filing Date: 2012-08-01 | Inventor： Kraft, Jochen Schrems, Martin Schrank, Franz | Assignee: ams AG | IPC: H01L23/48 | Abstract: A semiconductor substrate (1) is provided on a main surface (14) with an intermetal dielectric (4) including metal planes (5) and on an opposite rear surface (15) with an insulation layer (2) and an electrically conductive connection pad (7). An etch stop layer (6) is applied on the intermetal dielectric to prevent a removal of the intermetal dielectric above the metal planes during subsequent method steps. An opening (9) having a side wall (3) and a bottom (13) is formed from the main surface through the substrate above the connection pad. A side wall spacer (10) is formed on the side wall by a production and subsequent partial removal of a dielectric layer (11). The insulation layer is removed from the bottom to uncover an area of the connection pad. A metal layer is applied in the opening and is provided for an interconnect through the substrate. | |||
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127 | WO2015082549A1 |
OPTICAL SENSOR ARRANGEMENT AND METHOD OF PRODUCING AN OPTICAL SENSOR ARRANGEMENT
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Publication/Patent Number: WO2015082549A1 | Publication Date: 2015-06-11 | Application Number: 2014076420 | Filing Date: 2014-12-03 | Inventor： Schrank, Franz Schrems, Martin Dierschke, Eugene G | Assignee: AMS AG | IPC: G01S7/481 | Abstract: An optical sensor arrangement | |||
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128 | TWI495516B |
Device for coating a wafer
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Publication/Patent Number: TWI495516B | Publication Date: 2015-08-11 | Application Number: 100137971 | Filing Date: 2011-10-19 | Inventor： Schrank, Franz Bartel, Johanna Holzleitner, Ronald Hoffmann, Raimund Teva, Jordi | Assignee: EV GROUP GMBH | IPC: B05D1/42 | Abstract: The invention relates to a device for coating a surface (2o) of a wafer (2) With a retaining system (16) for placing the wafer (2) on a retaining surface (19) | |||
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129 | KR101497848B1 |
APPARATUS FOR COATING A WAFER
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Publication/Patent Number: KR101497848B1 | Publication Date: 2015-03-04 | Application Number: 20137006971 | Filing Date: 2010-10-19 | Inventor： Schrank, Franz Holzleitner, Ronald Bartel, Johanna Hoffmann, Raimund Teva, Jordi | Assignee: EV GROUP GMBH | IPC: H01L21/02 | ||||
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130 | EP2752871B1 |
Method of application of a carrier to a device wafer
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Publication/Patent Number: EP2752871B1 | Publication Date: 2015-09-16 | Application Number: 13150530.7 | Filing Date: 2013-01-08 | Inventor： Siegert, Jörg Schrems, Martin Schrank, Franz Kraft, Jochen | Assignee: ams AG | IPC: H01L21/683 | Abstract: A device wafer (1) having a main surface (10) including an edge region (11) and a carrier (2) having a further main surface (20) including an annular surface region (21) corresponding to the edge region of the device wafer are provided. An adhesive (3) is applied in the edge region and/or in the annular surface region, but not on the remaining areas of the main surfaces. The device wafer is fastened to the carrier by the adhesive. The main surface and the further main surface are brought into contact with one another when the device wafer is fastened to the carrier, while the main surface and the further main surface are fastened to one another only in the edge region. The device wafer is removed from the carrier after further process steps, which may include the formation of through-wafer vias in the device wafer. | |||
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131 | EP2630653B1 |
APPARATUS FOR COATING A WAFER
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Publication/Patent Number: EP2630653B1 | Publication Date: 2015-04-01 | Application Number: 10770723.4 | Filing Date: 2010-10-19 | Inventor： Bartel, Johanna Holzleitner, Ronald Hoffmann, Raimund Schrank, Franz Teva, Jordi | Assignee: EV Group GmbH | IPC: H01L21/67 | ||||
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132 | EP2889901A1 |
Semiconductor device with through-substrate via and method of producing a semiconductor device with through-substrate via
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Publication/Patent Number: EP2889901A1 | Publication Date: 2015-07-01 | Application Number: 13199683.7 | Filing Date: 2013-12-27 | Inventor： Schrank, Franz Carniello, Sara Enichlmair, Hubert Kraft, Jochen Löffler, Bernhard Holzhaider, Rainer | Assignee: ams AG | IPC: H01L21/768 | Abstract: A dielectric layer (2) is arranged on the main surface (10) of a semiconductor substrate (1), and a passivation layer (6) is arranged on the dielectric layer. A metal layer (3) is embedded in the dielectric layer above an opening (12) in the substrate, and a metallization (14) is arranged in the opening. The metallization contacts the metal layer and forms a through-substrate via to a rear surface (11) of the substrate. A layer or layer sequence (7, 8, 9) comprising at least one further layer is arranged on the passivation layer above the opening. In this way the bottom of the through-substrate via is stabilized. A plug (17) may additionally be arranged in the opening without filling the opening. | |||
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133 | WO2015097002A1 |
SEMICONDUCTOR DEVICE WITH THROUGH-SUBSTRATE VIA AND CORRESPONDING METHOD OF MANUFACTURE
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Publication/Patent Number: WO2015097002A1 | Publication Date: 2015-07-02 | Application Number: 2014077587 | Filing Date: 2014-12-12 | Inventor： Schrank, Franz Kraft, Jochen Enichlmair, Hubert Carniello, Sara LÖffler, Bernhard Holzhaider, Rainer | Assignee: AMS AG | IPC: H01L21/768 | Abstract: A dielectric layer (2) is arranged on the main surface (10) of a semiconductor substrate (1) | |||
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134 | EP2741322A1 |
Semiconductor device with integrated hot plate and recessed substrate and method of production
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Publication/Patent Number: EP2741322A1 | Publication Date: 2014-06-11 | Application Number: 12196321.9 | Filing Date: 2012-12-10 | Inventor： Schrank, Franz Schrems, Martin | Assignee: ams AG | IPC: H01L23/34 | Abstract: The semiconductor device comprises a substrate (1) of semiconductor material, a dielectric layer (2) on the substrate, an electrically conductive contact pad (3) arranged in the dielectric layer, a hot plate (4) arranged in the dielectric layer, a recess (9) of the substrate at the location of the hot plate, and an integrated circuit (18), which operates the hot plate. An electrically conductive layer (14) is arranged on a side of the substrate opposite the dielectric layer. The substrate is provided with a via hole (8) above the contact pad, and an electrically conductive material (12) connecting the electrically conductive layer with the contact pad is applied in the via hole. The recess (9) and the via hole (8) are formed in the same process step. | |||
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135 | US2014021572A1 |
PHOTODIODE DEVICE AND METHOD FOR PRODUCTION THEREOF
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Publication/Patent Number: US2014021572A1 | Publication Date: 2014-01-23 | Application Number: 13/981,302 | Filing Date: 2012-01-24 | Inventor： Teva, Jordi Schrank, Franz | Assignee: ams AG | IPC: H01L31/101 | Abstract: The photodiode device has an electrically conductive cathode layer (3) at a photodiode layer (4) composed of a semiconductor material. Doped anode regions (5) are situated at a top side of the photodiode layer facing away from the cathode layer. A trench (14) subdivides the photodiode layer. A conductor layer (7) is arranged in or at the trench and electrically conductively connects the cathode layer with a cathode connection (11). Anode connections (12) are electrically conductively connected with the anode regions. | |||
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136 | WO2014090681A1 |
SEMICONDUCTOR DEVICE WITH INTEGRATED HOT PLATE AND RECESSED SUBSTRATE AND METHOD OF PRODUCTION
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Publication/Patent Number: WO2014090681A1 | Publication Date: 2014-06-19 | Application Number: 2013075665 | Filing Date: 2013-12-05 | Inventor： Schrank, Franz Schrems, Martin | Assignee: AMS AG | IPC: G01N27/14 | Abstract: The semiconductor device comprises a substrate (1) of semiconductor material | |||
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137 | WO2014072114A1 |
SEMICONDUCTOR SENSOR DEVICE AND METHOD OF PRODUCING A SEMICONDUCTOR SENSOR DEVICE
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Publication/Patent Number: WO2014072114A1 | Publication Date: 2014-05-15 | Application Number: 2013069705 | Filing Date: 2013-09-23 | Inventor： Schrank, Franz Schrems, Martin | Assignee: AMS AG | IPC: B81C1/00 | Abstract: The semiconductor device comprises a substrate (1) of semiconductor material with a front side (4) and an opposite rear side (7) | |||
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138 | EP2705544A1 |
COLOR CONVERSION ELEMENT AND LAMP
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Publication/Patent Number: EP2705544A1 | Publication Date: 2014-03-12 | Application Number: 12720116.8 | Filing Date: 2012-04-10 | Inventor： Schrank, Franz Tasch, Stefan | Assignee: Lumitech Produktion und Entwicklung GmbH | IPC: H01L33/50 | ||||
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139 | US8623762B2 |
Semiconductor device and a method for making the semiconductor device
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Publication/Patent Number: US8623762B2 | Publication Date: 2014-01-07 | Application Number: 12/621,322 | Filing Date: 2009-11-18 | Inventor： Kraft, Jochen Schrank, Franz | Assignee: AMS AG | IPC: H01L21/44 | Abstract: An opening (9) is made in the substrate (1) over a terminal pad (7). A dielectric layer (10), a metallization (11), a compensation layer (13) and a passivation layer (15) are deposited so that the passivation layer is separated from the metallization by the compensation layer at least within the opening. A material that is suitable for reducing a mechanical stress between the metallization and the passivation layer is chosen for the compensation layer. | |||
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140 | TWI435469B |
Cover for optoelectronic components
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Publication/Patent Number: TWI435469B | Publication Date: 2014-04-21 | Application Number: 96139378 | Filing Date: 2007-10-19 | Inventor： Hoschopf, Hans Schrank, Franz | Assignee: TRIDONICATCO OPTOELECTRONICS GMBH LUMITECH PRODUKTION UND ENTWICKLUNG GMBH | IPC: H01L31/0203 | Abstract: A method for manufacturing a electronic and/or optoelectronic module comprises the following steps: - mounting a electronic and/or optoelectronic chip on a board |
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