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141 | EP2731129A1 |
Molded semiconductor sensor device and method of producing the same at a wafer-level
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Publication/Patent Number: EP2731129A1 | Publication Date: 2014-05-14 | Application Number: 12191647.2 | Filing Date: 2012-11-07 | Inventor： Schrank, Franz Schrems, Martin | Assignee: ams AG | IPC: H01L23/31 | Abstract: The semiconductor device comprises a substrate (1) of semiconductor material with a front side (4) and an opposite rear side (7), a wiring layer (5) at the front side (4), a further wiring layer (8) at the rear side (7), and a through-substrate via (3) connecting the wiring layer (5) and the further wiring layer (8). A mold compound (14) is arranged on the rear side (7) above the substrate (1), a cavity (17) is formed in the mold compound (14), a sensor layer (21) is arranged in the cavity (17), and the cavity (17) is covered with a membrane (15). The mold compound (14) is applied on the wafer, and a film assisted molding process can be used. | |||
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142 | US2014339698A1 |
SEMICONDUCTOR DEVICE WITH THROUGH-SUBSTRATE VIA COVERED BY A SOLDER BALL AND RELATED METHOD OF PRODUCTION
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Publication/Patent Number: US2014339698A1 | Publication Date: 2014-11-20 | Application Number: 14/359,568 | Filing Date: 2012-11-07 | Inventor： Cassidy, Cathal Schrems, Martin Schrank, Franz | Assignee: AMS AG | IPC: H01L23/48 | Abstract: The semiconductor device comprises a semiconductor substrate (10) with a metallization (111) having an upper terminal layer (22) located at a front side (20) of the substrate. The metallization forms a through-substrate via (23) from the upper terminal layer to a rear terminal layer (13) located opposite to the front side at a rear side (21) of the substrate. The through-substrate via comprises a void (101), which may be filled with air or another gas. A solder ball (100) closes the void without completely filling it. A variety of interconnections for three dimensional integration is offered by this scheme. | |||
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143 | EP2693467A1 |
A method of producing a semiconductor device having an interconnect through the substrate
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Publication/Patent Number: EP2693467A1 | Publication Date: 2014-02-05 | Application Number: 12178878.0 | Filing Date: 2012-08-01 | Inventor： Kraft, Jochen Schrank, Franz Schrems, Martin | Assignee: ams AG | IPC: H01L21/768 | Abstract: A semiconductor substrate (1) is provided on a main surface (14) with an intermetal dielectric (4) including metal planes (5) and on an opposite rear surface (15) with an insulation layer (2) and an electrically conductive connection pad (7). An etch stop layer (6) is applied on the intermetal dielectric to prevent a removal of the intermetal dielectric above the metal planes during subsequent method steps. An opening (9) having a side wall (3) and a bottom (13) is formed from the main surface through the substrate above the connection pad. A side wall spacer (10) is formed on the side wall by a production and subsequent partial removal of a dielectric layer (11). The insulation layer is removed from the bottom to uncover an area of the connection pad. A metal layer is applied in the opening and is provided for an interconnect through the substrate. | |||
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144 | EP2597677B1 |
Semiconductor device with through-substrate via covered by a solder ball and related method of production
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Publication/Patent Number: EP2597677B1 | Publication Date: 2014-08-06 | Application Number: 11190389.4 | Filing Date: 2011-11-23 | Inventor： Cassidy, Cathal Schrems, Martin Schrank, Franz | Assignee: ams AG | IPC: H01L23/48 | Abstract: The semiconductor device comprises a semiconductor substrate (10) with a metallization (111) having an upper terminal layer (22) located at a front side (20) of the substrate. The metallization forms a through-substrate via (23) from the upper terminal layer to a rear terminal layer (13) located opposite to the front side at a rear side (21) of the substrate. The through-substrate via comprises a void (101), which may be filled with air or another gas. A solder ball (100) closes the void without completely filling it. A variety of interconnections for threedimensional integration is offered by this scheme. | |||
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145 | DE102012108522A1 |
Method for manufacturing semiconductor stack for stacking semiconductor chips with components for three-dimensional integration of electronic circuit
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Publication/Patent Number: DE102012108522A1 | Publication Date: 2014-03-13 | Application Number: 102012108522 | Filing Date: 2012-09-12 | Inventor： Schrank, Franz Schrems, Martin Kraft, Jochen Siegert, Joerg | Assignee: AMS AG | IPC: H01L21/28 | Abstract: The method involves providing electric conductors (4) with three stack components (1-3). The stack component (2) is arranged on stack component (1) and connected with stack component (1). The stack component (3) is arranged on stack component (2) and connected with stack components (1 | |||
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146 | DE112007002739B4 |
Verfahren zur Herstellung eines Halbleiterbauelements mit Isolationsgraben und Kontaktgraben
Title (English):
Fabrication of Semiconductor components with isometric Groove and contact Groove
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Publication/Patent Number: DE112007002739B4 | Publication Date: 2014-09-18 | Application Number: 112007002739 | Filing Date: 2007-10-22 | Inventor： Schrank, Franz Schrems, Martin Dr Enichlmair, Hubert Dr | Assignee: Austriamicrosystems AG | IPC: H01L21/308 | Abstract: Verfahren zur Herstellung eines Halbleiter-Bauelements | |||
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147 | EP2772939A1 |
Semiconductor device for detection of radiation and method of producing a semiconductor device for detection of radiation
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Publication/Patent Number: EP2772939A1 | Publication Date: 2014-09-03 | Application Number: 13157432.9 | Filing Date: 2013-03-01 | Inventor： Enichlmair, Hubert Schrank, Franz Siegert, Jörg | Assignee: AMS AG | IPC: H01L27/146 | Abstract: The semiconductor device for detection of radiation comprises a semiconductor substrate (1) with a main surface (11), a dielectric layer (6) comprising at least one compound of a semiconductor material, an integrated circuit (2) including at least one component sensitive to radiation (3), a wiring (4) of the integrated circuit, an electrically conductive through-substrate via (5) contacting the wiring, and a structured filter layer (7) arranged immediately on the dielectric layer above the component sensitive to radiation. | |||
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148 | WO2014131731A1 |
SEMICONDUCTOR DEVICE FOR DETECTION OF RADIATION AND METHOD OF PRODUCING A SEMICONDUCTOR DEVICE FOR DETECTION OF RADIATION
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Publication/Patent Number: WO2014131731A1 | Publication Date: 2014-09-04 | Application Number: 2014053551 | Filing Date: 2014-02-24 | Inventor： Schrank, Franz Enichlmair, Hubert Siegert, JÖrg | Assignee: AMS AG | IPC: H01L27/146 | Abstract: The semiconductor device for detection of radiation comprises a semiconductor substrate (1) with a main surface (11) | |||
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149 | DE102011013228B4 |
Method for manufacturing semiconductor component that is three-dimensionally integrated in semiconductor chip stack
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Publication/Patent Number: DE102011013228B4 | Publication Date: 2014-05-28 | Application Number: 102011013228 | Filing Date: 2011-03-07 | Inventor： Schrank, Franz LÖffler, Bernhard StÜckler, Ewald | Assignee: Austriamicrosystems AG | IPC: H01L21/283 | Abstract: The method involves attaching a lower stop layer (13) to a conductor region (23) that is formed on a major side (2) of a semiconductor substrate (1). A handling wafer i.e. silicon substrate | |||
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150 | US2014038410A1 |
METHOD OF PRODUCING A SEMICONDUCTOR DEVICE HAVING AN INTERCONNECT THROUGH THE SUBSTRATE
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Publication/Patent Number: US2014038410A1 | Publication Date: 2014-02-06 | Application Number: 13/956,274 | Filing Date: 2013-07-31 | Inventor： Kraft, Jochen Schrank, Franz Schrems, Martin | Assignee: ams AG | IPC: H01L21/768 | Abstract: A semiconductor substrate (1) is provided on a main surface (14) with an intermetal dielectric (4) including metal planes (5) and on an opposite rear surface (15) with an insulation layer (2) and an electrically conductive connection pad (7). An etch stop layer (6) is applied on the intermetal dielectric to prevent a removal of the intermetal dielectric above the metal planes during subsequent method steps. An opening (9) having a side wall (3) and a bottom (13) is formed from the main surface through the substrate above the connection pad. A side wall spacer (10) is formed on the side wall by a production and subsequent partial removal of a dielectric layer (11). The insulation layer is removed from the bottom to uncover an area of the connection pad. A metal layer is applied in the opening and is provided for an interconnect through the substrate. | |||
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151 | WO2014108442A1 |
METHOD OF APPLICATION OF A CARRIER TO A DEVICE WAFER
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Publication/Patent Number: WO2014108442A1 | Publication Date: 2014-07-17 | Application Number: 2014050233 | Filing Date: 2014-01-08 | Inventor： Schrank, Franz Schrems, Martin Kraft, Jochen Siegert, JÖrg | Assignee: AMS AG | IPC: H01L21/683 | Abstract: A device wafer (1) having a main surface (10) including an edge region (11) and a carrier (2) having a further main surface (20) including an annular surface region (21) corresponding to the edge region of the device wafer are provided. An adhesive (3) is applied in the edge region and/or in the annular surface region | |||
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152 | EP2752871A1 |
Method of application of a carrier to a device wafer
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Publication/Patent Number: EP2752871A1 | Publication Date: 2014-07-09 | Application Number: 13150530.7 | Filing Date: 2013-01-08 | Inventor： Siegert, Jörg Schrems, Martin Schrank, Franz Kraft, Jochen | Assignee: ams AG | IPC: H01L21/683 | Abstract: A device wafer (1) having a main surface (10) including an edge region (11) and a carrier (2) having a further main surface (20) including an annular surface region (21) corresponding to the edge region of the device wafer are provided. An adhesive (3) is applied in the edge region and/or in the annular surface region, but not on the remaining areas of the main surfaces. The device wafer is fastened to the carrier by the adhesive. The main surface and the further main surface are brought into contact with one another when the device wafer is fastened to the carrier, while the main surface and the further main surface are fastened to one another only in the edge region. The device wafer is removed from the carrier after further process steps, which may include the formation of through-wafer vias in the device wafer. | |||
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153 | US8658534B2 |
Method for producing a semiconductor component, and semiconductor component
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Publication/Patent Number: US8658534B2 | Publication Date: 2014-02-25 | Application Number: 13/054,614 | Filing Date: 2009-06-25 | Inventor： Schrank, Franz Koppitsch, Günther Beutl, Michael Carniello, Sara Kraft, Jochen | Assignee: AMS AG | IPC: H01L21/44 | Abstract: In an insulation layer of an SOI substrate, a connection pad is arranged. A contact hole opening above the connection pad is provided on side walls and on the connection pad with a metallization that is contacted on top side with a top metal. | |||
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154 | US8884442B2 |
Method for producing a semiconductor component with a through-contact and semiconductor component with through-contact
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Publication/Patent Number: US8884442B2 | Publication Date: 2014-11-11 | Application Number: 13/820,998 | Filing Date: 2011-08-09 | Inventor： Kraft, Jochen Jessenig, Stefan Koppitsch, Günther Schrank, Franz Teva, Jordi Löffler, Bernhard Siegert, Jörg | Assignee: ams AG | IPC: H01L21/48 | Abstract: Through the intermetal dielectric (2) and the semiconductor material of the substrate (1) a contact hole is formed, and a contact area of a connection metal plane (3) that faces the substrate is exposed in the contact hole. A metallization (11) is applied, which forms a connection contact (12) on the contact area, a through-contact (13) in the contact hole and a connection contact (20) on a contact area facing away from the substrate and/or on a vertical conductive connection (15) of the upper metal plane (24). | |||
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155 | DE102006047203B4 |
Microphone arrangement for use in e.g. portable radio communication device
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Publication/Patent Number: DE102006047203B4 | Publication Date: 2013-01-31 | Application Number: 102006047203 | Filing Date: 2006-10-05 | Inventor： Schrank, Franz | Assignee: Austriamicrosystems AG | IPC: B81B7/02 | Abstract: The microphone arrangement has a pile arrangement (1) with a semiconductor body (10) comprising a microphone structure (13) | |||
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156 | US8531041B2 |
Semiconductor component having a plated through-hole and method for the production thereof
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Publication/Patent Number: US8531041B2 | Publication Date: 2013-09-10 | Application Number: 13/501,399 | Filing Date: 2010-09-22 | Inventor： Schrank, Franz | Assignee: AMS AG | IPC: H01L23/48 | Abstract: A connection contact layer (4) is disposed between semiconductor bodies (1,2). In the second semiconductor body (2), a recess is provided. A connection layer (7) on the top face extends as far as the recess, in which a metallization (10) is present that conductively connects the connection contact layer (4) to the connection layer (7) in an electrical manner. A polymer (8) or a further metallization is present in the recess. | |||
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157 | EP2584598A1 |
Method of producing a semiconductor device comprising a through-substrate via and a capping layer and corresponding semiconductor device
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Publication/Patent Number: EP2584598A1 | Publication Date: 2013-04-24 | Application Number: 11185999.7 | Filing Date: 2011-10-20 | Inventor： Schrank, Franz Cassidy, Cathal | Assignee: austriamicrosystems AG | IPC: H01L21/768 | Abstract: The method of producing a semiconductor device comprises the steps of providing a semiconductor substrate (1) with an electrically conductive structure (11), forming a hole (4) through the substrate in a direction normal to its main surface (10), and forming a through-substrate via (5) in the hole by introducing an electrically conductive material without filling the hole. A capping layer (6) is applied above the main surface in such a way that the capping layer closes the remaining inner volume (14) of the through-substrate via without filling the hole or at least partially covers an annular cavity surrounding the through-substrate via. The capping layer is structured, so that the electrically conductive structure is not completely covered by the capping layer. | |||
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158 | DE102004058879B4 |
MEMS-Mikrophon und Verfahren zur Herstellung
Title (English):
The Claimant stated that, however, it could also be said that,
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Publication/Patent Number: DE102004058879B4 | Publication Date: 2013-11-07 | Application Number: 102004058879 | Filing Date: 2004-12-06 | Inventor： Schrank, Franz Schrems, Martin Dr | Assignee: Austriamicrosystems AG | IPC: B81B7/02 | Abstract: Mikrophon in MEMS-Bauweise | |||
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159 | TWM456497U |
LED module
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Publication/Patent Number: TWM456497U | Publication Date: 2013-07-01 | Application Number: 101212117 | Filing Date: 2007-10-19 | Inventor： Hoschopf, Hans Schrank, Franz | Assignee: LUMITECH PRODUKTION UND ENTWICKLUNG GMBH TRIDONICATCO OPTOELECTRONICSGMBH | IPC: G02B5/00 | Abstract: An LED module comprising: an LED chip and a cover mounted on a board | |||
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160 | EP2188851B1 |
LED MODULE, LED ILLUMINATION MEANS, AND LED LAMP FOR THE ENERGY-EFFICIENT REPRODUCTION OF WHITE LIGHT
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Publication/Patent Number: EP2188851B1 | Publication Date: 2013-03-13 | Application Number: 08801969.0 | Filing Date: 2008-09-10 | Inventor： Baumgartner, Erwin Schrank, Franz | Assignee: Lumitech Produktion und Entwicklung GmbH | IPC: F21K99/00 |
3.Current Quota