Country
Full text data for US,EP,CN
Type
Legal Validity
Legal Status
Filing Date
Publication Date
Inventor
Assignee
Click to expand
IPC(Section)
IPC(Class)
IPC(Subclass)
IPC(Group)
IPC(Subgroup)
Agent
Agency
Claims Number
Figures Number
Citation Number of Times
Assignee Number
No. Publication Number Title Publication/Patent Number Publication/Patent Number Publication Date Publication Date
Application Number Application Number Filing Date Filing Date
Inventor Inventor Assignee Assignee IPC IPC
181
KR20110123520A
PLANER MEMBER FOR TOUCH PANEL
Publication/Patent Number: KR20110123520A Publication Date: 2011-11-15 Application Number: 20100043042 Filing Date: 2010-05-07 Inventor: Kim, Byung Soo   Lee, Yong In   Seo, Chung Won   Jo, Ji Won   Lee, Keun Sik   Hong, Hyuk Jin   Assignee: LG INNOTEK CO., LTD.   IPC: G06F3/041 Abstract: PURPOSE: An in-plane member for touch panel is provided to prevent the secession of an electrode that is formed in the lower part of a transparent substrate by bonding an FPCB(Flexible Printed Circuit Board) in the upper part of a transparent substrate. CONSTITUTION: An upper transparent conductive film(214) is formed in the lower part of an upper transparent substrate. A lower transparent conductive film(224) is formed in the upper side of the lower transparent substrate. First and second electrodes(216
182
KR20110124543A
SEALED PLANER MEMBER FOR TOUCH PANEL
Publication/Patent Number: KR20110124543A Publication Date: 2011-11-17 Application Number: 20100043988 Filing Date: 2010-05-11 Inventor: Kim, Byung Soo   Lee, Yong In   Seo, Chung Won   Jo, Ji Won   Kim, Chang Je   Lee, Keun Sik   Hong, Hyuk Jin   Assignee: LG INNOTEK CO., LTD.   IPC: G06F3/041 Abstract: PURPOSE: A planar member for a sealed touch panel is provided to secure the stability of a FPCB(Flexible Printed Circuit Board) bonding unit by sealing the bonding part of the touch panel or FPCB. CONSTITUTION: An upper side transparent conductive film(214) is formed the bottom side of a transparent board(212). The bottom conductive film is formed the upper side of a bottom transparent board in which is faced with the bottom side of the transparent board. An upper side electrode is formed in the bottom side of the transparent conductive film. A bottom side electrode is formed on the upper surface of the bottom side transparent conductive film. An FPCB(230) is connected to the upper side and the bottom side electrode by inserting into between the upper side transparent board and the bottom side transparent board. Protection units(40a
183
KR20110041334A
PLANER MEMBER FOR TOUCH PANEL AND METHOD FOR MANUFACTURING SAME
Publication/Patent Number: KR20110041334A Publication Date: 2011-04-21 Application Number: 20090098438 Filing Date: 2009-10-15 Inventor: Kim, Byung Soo   Lee, Yong In   Seo, Chung Won   Jo, Ji Won   Lee, Keun Sik   Hong, Hyuk Jin   Assignee: LG INNOTEK CO., LTD.   IPC: G06F3/041 Abstract: PURPOSE: A method for manufacturing a planer member for a touch panel is provided to reduce the overall thickness of the touch panel by not using an OCA(Optical Cleared Adhesive). CONSTITUTION: A first conductive pattern(140) is formed on a transparent substrate. A first insulation layer(210) is formed on the first conductive pattern. A second conductive pattern(160) is formed on the first insulation layer. A first and a second metal electrodes(150
184
WO2011046391A3
TOUCH PANEL AND MANUFACTURING METHOD THEREOF
Publication/Patent Number: WO2011046391A3 Publication Date: 2011-07-14 Application Number: 2010007090 Filing Date: 2010-10-15 Inventor: Kim, Byung Soo   Lee, Yong In   Seo, Chung Won   Jo, Ji Won   Lee, Keun Sik   Hong, Hyuk Jin   Assignee: LG INNOTEK CO., LTD.   KIM, BYUNG SOO   LEE, YONG IN   SEO, CHUNG WON   JO, JI WON   LEE, KEUN SIK   HONG, HYUK JIN   IPC: G06F3/041 Abstract: A touch panel is provided. The touch panel includes a substrate
185
KR101082609B1
PLANER MEMBER FOR TOUCH PANEL AND METHOD FOR MANUFACTURING SAME
Publication/Patent Number: KR101082609B1 Publication Date: 2011-11-15 Application Number: 20090098822 Filing Date: 2009-10-16 Inventor: Kim, Byung Soo   Seo, Chung Won   Jo, Ji Won   Lee, Keun Sik   Hong, Hyuk Jin   Assignee: LG INNOTEK CO., LTD.   IPC: G06F3/041 Abstract: PURPOSE: An in-plane member for touch panel and manufacturing method thereof are provided to increase the durability of an intermediate transparent layer and to increase the electrical characteristic of the touch panel. CONSTITUTION: An intermediate transparent layer(220) and a conductive transparent layer(230) are successively laminated on a transparent substrate(210). The intermediate transparent layer is SiO3 or SiO4 peroxide composition. The transparent substrate is ITO(Iidium-Tin Oxide) peroxide composition. The transparent substrate is a plastic sheet or a plastic film.
186
KR20110038969A
PLANER MEMBER FOR TOUCH PANEL AND METHOD FOR MANUFACTURING SAME AND TOUCH PANEL USING THE PLANER MEMBER
Publication/Patent Number: KR20110038969A Publication Date: 2011-04-15 Application Number: 20090096194 Filing Date: 2009-10-09 Inventor: Kim, Byung Soo   Lee, Yong In   Seo, Chung Won   Jo, Ji Won   Lee, Keun Sik   Hong, Hyuk Jin   Assignee: LG INNOTEK CO., LTD.   IPC: G06F3/041 Abstract: PURPOSE: A surface member for a touch panel and a manufacturing method thereof and touch panel using the same are provided to improve surface hardness and thinning the thickness by steadily unifying an ITO thin film and a polycarbonate. CONSTITUTION: A PMMA(Polymer Methyl Methacrylate) layer(170) is formed on a single-side or both sides of a transparent base substrate(110) as a thickness of 0.1~100 micron. The base transparent substrate is a polycarbonate substrate. A conductivity transparent layer or a ITO(Indium Tin Oxide) layer is formed on the external surface of PMMA. The conductivity transparent layer or the ITO layer is patterned.
187
WO2011043612A3
PLATE MEMBER FOR TOUCH PANEL AND METHOD OF MANUFACTURING THE SAME
Publication/Patent Number: WO2011043612A3 Publication Date: 2011-07-07 Application Number: 2010006872 Filing Date: 2010-10-07 Inventor: Kim, Byung Soo   Seo, Chung Won   Jo, Ji Won   Lee, Keun Sik   Hong, Hyuk Jin   Assignee: LG INNOTEK CO., LTD.   KIM, BYUNG SOO   SEO, CHUNG WON   JO, JI WON   LEE, KEUN SIK   HONG, HYUK JIN   IPC: G06F3/041 Abstract: A plate member for touch panel and a method of manufacturing the same
188
KR101082610B1
PLANER MEMBER FOR TOUCH PANEL AND METHOD FOR MANUFACTURING SAME
Publication/Patent Number: KR101082610B1 Publication Date: 2011-11-10 Application Number: 20090098438 Filing Date: 2009-10-15 Inventor: Kim, Byung Soo   Lee, Yong In   Seo, Chung Won   Jo, Ji Won   Lee, Keun Sik   Hong, Hyuk Jin   Assignee: LG INNOTEK CO., LTD.   IPC: G06F3/041 Abstract: PURPOSE: A method for manufacturing a planer member for a touch panel is provided to reduce the overall thickness of the touch panel by not using an OCA(Optical Cleared Adhesive). CONSTITUTION: A first conductive pattern(140) is formed on a transparent substrate. A first insulation layer(210) is formed on the first conductive pattern. A second conductive pattern(160) is formed on the first insulation layer. A first and a second metal electrodes(150
189
TW201124890A
Touch panel and manufacturing method thereof
Publication/Patent Number: TW201124890A Publication Date: 2011-07-16 Application Number: 99135290 Filing Date: 2010-10-15 Inventor: Kim, Byung Soo   Lee, Yong In   Seo, Chung Won   Jo, Ji Won   Lee, Keun Sik   Hong, Hyuk Jin   Assignee: LG INNOTEK CO., LTD.   IPC: G06F3/041 Abstract: A touch panel is provided. The touch panel includes a substrate
190
TW201127623A
Plate member for touch panel and method of manufacturing the same
Publication/Patent Number: TW201127623A Publication Date: 2011-08-16 Application Number: 99135284 Filing Date: 2010-10-15 Inventor: Kim, Byung-soo   Jo, Ji-won   Hong, Hyuk-jin   Lee, Keun-sik   Seo chung won   Assignee: LG INNOTEK CO., LTD.   IPC: B32B27/06 Abstract: A plate member for touch panel and a method of manufacturing the same are provided. The plate member for touch panel includes: a transparent substrate; an intermediate transparent layer on the transparent substrate; and a conductive transparent layer on the intermediate transparent layer
191
KR100846364B1
Method for fabricating embedded Ferroelectric memory device with hydrogen diffusion barrier
Publication/Patent Number: KR100846364B1 Publication Date: 2008-07-15 Application Number: 20020023019 Filing Date: 2002-04-26 Inventor: Kang, Eung Yeol   Seo, Chung Won   Assignee: Hynix Semiconductor Inc.   IPC: H01L27/105 Abstract: PURPOSE: A method for fabricating an embedded ferroelectric memory device including a hydrogen diffusion barrier layer is provided to increase a hydrogen annealing effect and protect a ferroelectric by eliminating an Al2O3 hydrogen diffusion barrier layer formed in a region except a memory cell block without an additional process. CONSTITUTION: A lower electrode(33) is formed over a cell region of a semiconductor substrate(30) in which the cell region and a peripheral circuit region are defined. A ferroelectric layer(35) is formed on the semiconductor substrate including the lower electrode. An upper electrode(36) is formed on the ferroelectric layer over the cell region. A hydrogen diffusion barrier layer(37) is formed on the semiconductor substrate including the upper electrode. The hydrogen diffusion barrier layer and the ferroelectric layer over the peripheral circuit region are simultaneously eliminated.
192
KR100752935B1
Inspection method of a substrate damage yes or no plasma processing apparatus and plasma processing apparatus
Publication/Patent Number: KR100752935B1 Publication Date: 2007-08-30 Application Number: 20040083839 Filing Date: 2004-10-20 Inventor: Lee, Young Jong   Choi, Jun Young   Seo, Chung Won   Assignee: ADP Engineering Co., Ltd.   IPC: H01L21/3065
193
KR100622837B1
TRANSFER ROBOT
Publication/Patent Number: KR100622837B1 Publication Date: 2006-09-05 Application Number: 20050027560 Filing Date: 2005-04-01 Inventor: Lee, Young Jong   Choi, Jun Young   Seo, Chung Won   Assignee: ADP Engineering Co., Ltd.   IPC: B25J9/06
194
KR20060034837A
Inspection method of a substrate damage yes or no plasma processing apparatus and plasma processing apparatus
Publication/Patent Number: KR20060034837A Publication Date: 2006-04-26 Application Number: 20040083839 Filing Date: 2004-10-20 Inventor: Lee, Young Jong   Choi, Jun Young   Seo, Chung Won   Assignee: ADP Engineering Co., Ltd.   IPC: H01L21/3065
195
KR100635217B1
PLASMA PROCESSING APPARATUS
Publication/Patent Number: KR100635217B1 Publication Date: 2006-10-11 Application Number: 20050030293 Filing Date: 2005-04-12 Inventor: Lee, Young Jong   Nam, Chang Woo   Choi, Jun Young   Seo, Chung Won   Lee, Jeong Bin   Assignee: ADP Engineering Co., Ltd.   IPC: H01L21/3065 Abstract: A plasma processing apparatus is provided to control density and pressure of a process gas and to improve process uniformity by employing a rotational apparatus for rotating a baffle at a proper angle. An upper electrode and a lower electrode(114) are respectively prepared on an upper region and a lower region in a process chamber(110) to form an electric field. A plate shaped baffle(120) is formed to delay a process gas discharge by many partitions between the lower electrode and a wall of the process chamber. At least one rotational apparatus(140) is provided on each side of the baffle to separately rotate the baffle at a proper angle. A vertical moving apparatus(130) vertically moves the baffle every lower surface of the rotational apparatus.
196
KR100465832B1
FERROELECTRIC MEMORY DEVICE AND MANUFACTURING METHOD THEREFOR
Publication/Patent Number: KR100465832B1 Publication Date: 2005-01-13 Application Number: 20020037235 Filing Date: 2002-06-29 Inventor: Oh, Sang Hyeon   Seo, Chung Won   Assignee: HYNIX SEMICONDUCTOR INC.   IPC: H01L27/105 Abstract: PURPOSE: A ferroelectric memory device and a manufacturing method therefor are provided to prevent short between an upper and lower electrodes and to restrain degradation of a ferroelectric film due to attacks of impurities. CONSTITUTION: A semiconductor substrate(31) is provided with a transistor. The first insulating layer(36) is formed on the resultant structure. A storage node contact(40) is formed to contact a source/drain regions(35a
197
KR100448237B1
FERROELECTRIC MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME
Publication/Patent Number: KR100448237B1 Publication Date: 2004-09-13 Application Number: 20010087788 Filing Date: 2001-12-29 Inventor: Seo, Chung Won   Assignee: Hynix Semiconductor Inc.   IPC: H01L27/105 Abstract: PURPOSE: A ferroelectric memory device and a method for manufacturing the same are provided to be capable of preventing electric field from focusing to edge portion of an electrode and restraining the area loss of a capacitor. CONSTITUTION: The first insulating layer(39) is formed on a semiconductor substrate(31) having a transistor. The second insulating layer(41) includes a lower electrode forming groove having a negative slope so as to expose the surface of the first insulating layer(39). A lower electrode(45) is then filled into the lower electrode forming groove. A ferroelectric film(46) is formed on the entire surface of the second insulating layer including the lower electrode(45). An upper electrode(47) having a positive slope is formed on the ferroelectric film(46) corresponding to the lower electrode.
198
KR20040001901A
FERROELECTRIC MEMORY DEVICE AND MANUFACTURING METHOD THEREFOR
Publication/Patent Number: KR20040001901A Publication Date: 2004-01-07 Application Number: 20020037235 Filing Date: 2002-06-29 Inventor: Oh, Sang Hyeon   Seo, Chung Won   Assignee: HYNIX SEMICONDUCTOR INC.   IPC: H01L27/105 Abstract: PURPOSE: A ferroelectric memory device and a manufacturing method therefor are provided to prevent short between an upper and lower electrodes and to restrain degradation of a ferroelectric film due to attacks of impurities. CONSTITUTION: A semiconductor substrate(31) is provided with a transistor. The first insulating layer(36) is formed on the resultant structure. A storage node contact(40) is formed to contact a source/drain regions(35a
199
KR100427040B1
FERROELECTRIC RANDOM ACCESS MEMORY AND FABRICATION METHOD THEREOF
Publication/Patent Number: KR100427040B1 Publication Date: 2004-04-14 Application Number: 20010088713 Filing Date: 2001-12-31 Inventor: Seo, Chung Won   Sung, Jin Yong   Oh, Sang Hyeon   Assignee: Hynix Semiconductor Inc.   IPC: H01L27/105 Abstract: PURPOSE: A ferroelectric random access memory and fabrication method thereof are provided to prevent decrease of the capacitance caused by the size limit of an upper electrode and a short circuit between an upper and lower electrode. CONSTITUTION: Two neighboring transistors are formed on a semiconductor substrate(31). The first isolation layer(35) and second one(42) with openings to expose a portion of the first one are formed on the substrate. Two lower electrodes(41) are filled inside the openings. Two upper electrodes(44) are formed on a ferroelectric layer(43) with the same width as the lower ones. A portion of the upper electrodes is exposed to be connected to a plate line(47) through the third isolation layer(45). A word line(32)
200
KR20030057712A
FERROELECTRIC MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME
Publication/Patent Number: KR20030057712A Publication Date: 2003-07-07 Application Number: 20010087788 Filing Date: 2001-12-29 Inventor: Seo, Chung Won   Assignee: Hynix Semiconductor Inc.   IPC: H01L27/105 Abstract: PURPOSE: A ferroelectric memory device and a method for manufacturing the same are provided to be capable of preventing electric field from focusing to edge portion of an electrode and restraining the area loss of a capacitor. CONSTITUTION: The first insulating layer(39) is formed on a semiconductor substrate(31) having a transistor. The second insulating layer(41) includes a lower electrode forming groove having a negative slope so as to expose the surface of the first insulating layer(39). A lower electrode(45) is then filled into the lower electrode forming groove. A ferroelectric film(46) is formed on the entire surface of the second insulating layer including the lower electrode(45). An upper electrode(47) having a positive slope is formed on the ferroelectric film(46) corresponding to the lower electrode.
Total 11 pages