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No. Publication Number Title Publication/Patent Number Publication/Patent Number Publication Date Publication Date
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1
US2021090985A1
WAFER LEVEL PACKAGE UTILIZING MOLDED INTERPOSER
Publication/Patent Number: US2021090985A1 Publication Date: 2021-03-25 Application Number: 17/110,035 Filing Date: 2020-12-02 Inventor: Shih shing yih   Assignee: Micron Technology, Inc.   IPC: H01L23/498 Abstract: Semiconductor packages may include a molded interposer and semiconductor dice mounted on the molded interposer. The molded interposer may include two redistribution layer structures on opposite sides of a molding compound. Electrically conductive vias may connect the RDL structures through the molding compound, and passive devices may be embedded in the molding compound and electrically connected to one of the RDL structures. Each of the semiconductor dice may be electrically connected to, and have a footprint covering, a corresponding one of the passive devices to form a face-to-face connection between each of the semiconductor dice and the corresponding one of the passive devices.
2
US10950538B2
Semiconductor structure and manufacturing method thereof
Publication/Patent Number: US10950538B2 Publication Date: 2021-03-16 Application Number: 16/244,870 Filing Date: 2019-01-10 Inventor: Shih shing yih   Assignee: NANYA TECHNOLOGY CORPORATION   IPC: H01L23/522 Abstract: A semiconductor structure includes a substrate; a die disposed over the substrate; a molding surrounding the die; a dielectric layer disposed over the substrate and surrounding the die and the molding; a conductive via extending through the dielectric layer; and a metallic strip extending through and along the dielectric layer to at least partially surround the die.
3
US2021050327A1
MICROELECTRONIC DEVICES INCLUDING EMBEDDED BRIDGE INTERCONNECT STRUCTURES
Publication/Patent Number: US2021050327A1 Publication Date: 2021-02-18 Application Number: 17/087,867 Filing Date: 2020-11-03 Inventor: Shih shing yih   Assignee: Micron Technology, Inc.   IPC: H01L25/065 Abstract: A semiconductor package includes a resin molded package substrate comprising a resin molded core, a plurality of metal vias in the resin molded core, a front-side RDL structure, and a back-side RDL structure. A bridge TSV interconnect component is embedded in the resin molded core. The bridge TSV interconnect component has a silicon substrate portion, an RDL structure integrally constructed on the silicon substrate portion, and TSVs in the silicon substrate portion. A first semiconductor die and a second semiconductor die are mounted on the front-side RDL structure. The first semiconductor die and the second semiconductor die are coplanar.
4
US10910357B2
Semiconductor package including hybrid bonding structure and method for preparing the same
Publication/Patent Number: US10910357B2 Publication Date: 2021-02-02 Application Number: 16/360,619 Filing Date: 2019-03-21 Inventor: Shih shing yih   Assignee: NANYA TECHNOLOGY CORPORATION   IPC: H01L25/18 Abstract: The present disclosure provides a semiconductor package structure. The semiconductor package structure includes a first die, a second die and a hybrid bonding structure disposed between the first die and the second die. The first die includes a first front side and a first back side opposite to the first front side. The second die includes a second front side and a second back side opposite to the second front side. The hybrid bonding structure is disposed between the first back side of the first die and the second front side of the second die. The first die and the second die are bonded to each other by the hybrid bonding structure. The hybrid bonding structure includes an organic barrier layer and an inorganic barrier layer bonded to each other.
5
US2021035905A1
SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
Publication/Patent Number: US2021035905A1 Publication Date: 2021-02-04 Application Number: 16/528,673 Filing Date: 2019-08-01 Inventor: Shih shing yih   Assignee: NANYA TECHNOLOGY CORPORATION   IPC: H01L23/522 Abstract: The semiconductor structure includes a first die, a second die, a connecting portion, and a through-substrate via. The first die includes a first dielectric layer and a first helical conductor embedded therein. The second die includes a second dielectric layer and a second helical conductor embedded therein, wherein the second dielectric layer is bonded with the first dielectric layer, thereby forming an interface. The connecting portion extends from the first dielectric layer through the interface to the second dielectric layer and interconnects the first helical conductor with the second helical conductor. The through-substrate via extends from the first die to the second die through the interface, wherein the through-substrate via is surrounded by the first and the second helical conductors.
6
US10903110B2
Method of forming fine interconnection for a semiconductor device
Publication/Patent Number: US10903110B2 Publication Date: 2021-01-26 Application Number: 16/257,021 Filing Date: 2019-01-24 Inventor: Shih shing yih   Assignee: NANYA TECHNOLOGY CORPORATION   IPC: H01L21/768 Abstract: A method of forming fine interconnection includes: forming spacers on a first and second hard mask layer on a dielectric layer; forming a first via hole through the first hard mask layer, the second hard mask layer, and the dielectric layer; oxidizing a sidewall of the first hard mask layer that surrounding the via hole; forming a second via hole in the second hard mask layer; forming a mask to cover the first hard mask layer in the second via hole; forming a line trench in a portion of the second hard mask layer exposed by the spacers and the mask, and in the first hard mask layer and the dielectric layer that are below the portion of the second hard mask layer; and forming a conductive material in the line trench and the first via hole.
7
US2021020455A1
CONDUCTIVE VIA STRUCTURE
Publication/Patent Number: US2021020455A1 Publication Date: 2021-01-21 Application Number: 16/514,986 Filing Date: 2019-07-17 Inventor: Shih shing yih   Assignee: NANYA TECHNOLOGY CORPORATION   IPC: H01L21/48 Abstract: A conductive via structure includes a first dielectric layer, a conductive pad, a second dielectric layer, and a redistribution layer. The conductive pad is in the first dielectric layer. The second dielectric layer is disposed above the first dielectric layer and has an opening. The conductive pad is in the opening. The opening has a first width at a top surface of the second dielectric layer and a second width at a bottom surface of the second dielectric layer. A difference between the first width and the second width is in a range from about 1.5 um to about 3 um. The redistribution layer extends from the top surface of the second dielectric layer to the conductive pad.
8
US10950564B2
Methods of forming microelectronic devices having a patterned surface structure
Publication/Patent Number: US10950564B2 Publication Date: 2021-03-16 Application Number: 16/414,440 Filing Date: 2019-05-16 Inventor: Shih shing yih   Wu, Tieh-chiang   Assignee: Micron Technology, Inc.   IPC: H01L23/00 Abstract: A connector structure and a manufacturing method thereof are provided. The connector structure includes a semiconductor substrate, a metal layer, a passivation layer, and a conductive structure. The metal layer is over the semiconductor substrate. The passivation layer is over the metal layer and includes an opening. The conductive structure is in contact with the metal layer in a patterned surface structure of the conductive structure through the opening of the passivation layer.
9
US2021028053A1
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
Publication/Patent Number: US2021028053A1 Publication Date: 2021-01-28 Application Number: 16/517,903 Filing Date: 2019-07-22 Inventor: Huang, Tse-yao   Shih shing yih   Assignee: NANYA TECHNOLOGY CORPORATION   IPC: H01L21/764 Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a semiconductor substrate, a plurality of first set conductive elements separately positioned above the semiconductor substrate, a plurality of insulating blocks respectively correspondingly positioned between adjacent pairs of the plurality of first set conductive elements, a plurality of first set supporting pillars respectively correspondingly positioned between adjacent pairs of the plurality of first set conductive elements and respectively correspondingly positioned over the plurality of insulating blocks, and a plurality of spaces respectively correspondingly positioned adjacent to the plurality of first set supporting pillars and respectively correspondingly positioned over the plurality of insulating blocks.
10
US2021028103A1
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
Publication/Patent Number: US2021028103A1 Publication Date: 2021-01-28 Application Number: 16/517,998 Filing Date: 2019-07-22 Inventor: Huang, Tse-yao   Shih shing yih   Assignee: NANYA TECHNOLOGY CORPORATION   IPC: H01L23/522 Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a semiconductor substrate, a plurality of first conductive elements separately positioned above the semiconductor substrate, a plurality of first supporting pillars respectively correspondingly positioned between an adjacent pairs of the plurality of first set conductive elements, and a plurality of spaces respectively correspondingly positioned adjacent to the plurality of first set supporting pillars.
11
US10937749B2
Methods of forming microelectronic devices including dummy dice
Publication/Patent Number: US10937749B2 Publication Date: 2021-03-02 Application Number: 16/540,444 Filing Date: 2019-08-14 Inventor: Shih shing yih   Shih, Neng-tai   Assignee: Micron Technology, Inc.   IPC: H01L23/00 Abstract: A semiconductor device includes an interposer having a first side and a second side opposite to the first side, at least one active chip mounted on the first side within a chip mounting area through a plurality of first bumps, at least one dummy chip mounted on the first side within a peripheral area being adjacent to the chip mounting area, a molding compound disposed on the first side. The molding compound covers the at least one active chip and the at least one dummy chip. A plurality of solder bumps is mounted on the second side.
12
US2021028121A1
SEMICONDUCTOR STRUCTURE
Publication/Patent Number: US2021028121A1 Publication Date: 2021-01-28 Application Number: 16/520,623 Filing Date: 2019-07-24 Inventor: Shih shing yih   Huang, Tse-yao   Assignee: NANYA TECHNOLOGY CORPORATION   IPC: H01L23/552 Abstract: The present disclosure provides a semiconductor structure, including a substrate having a front surface and a back surface, at least one semiconductor device, a first TSV disposed in the substrate, an insulating layer surrounding the first TSV, a shielding layer surrounding the insulating layer, and a second TSV adjacent to the first TSV. The semiconductor device is disposed in a device region of the substrate. The first TSV is exposed by the front surface and the back surface of the substrate. The insulating layer includes an electrically insulating material. The shielding layer includes an electrically conductive material coupled to ground through a ground layer. The second TSV is exposed by the front surface and the back surface of the substrate.
13
US2021043545A1
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
Publication/Patent Number: US2021043545A1 Publication Date: 2021-02-11 Application Number: 16/535,060 Filing Date: 2019-08-07 Inventor: Huang, Sheng-fu   Shih shing yih   Assignee: NANYA TECHNOLOGY CORPORATION   IPC: H01L23/48 Abstract: A semiconductor device includes a first semiconductor wafer, a second semiconductor wafer, and a first conductive via. The first semiconductor wafer includes a first substrate and at least one first conductive layer disposed on a top surface of the first substrate. The second semiconductor wafer is disposed on the first semiconductor wafer. The second semiconductor wafer includes a second substrate and a first conductive pad disposed on a top surface of the second substrate. The first conductive via extends from the first conductive pad to the first conductive layer.
14
US2021098461A1
SEMICONDUCTOR DEVICE
Publication/Patent Number: US2021098461A1 Publication Date: 2021-04-01 Application Number: 16/583,288 Filing Date: 2019-09-26 Inventor: Shih shing yih   Huang, Tse-yao   Assignee: NANYA TECHNOLOGY CORPORATION   IPC: H01L27/108 Abstract: A semiconductor device includes a semiconductor substrate having a cell region and a dummy region surrounding the cell region, a plurality of memory pillar structures, and a supporting layer. The memory pillar structures are on the cell region. The supporting layer is over the semiconductor substrate, interconnecting the memory pillar structures, and having a plurality of first and second opening patterns on the cell region. A first number of the memory pillar structures surround each of the first opening patterns, and a second number of the memory pillar structures surround each of the second opening patterns. The first opening patterns are different from the second opening patterns, the first number is different from the second number, and at least one of the first opening patterns and at least one of the second opening patterns are on a central portion of the cell region.
15
US10553433B2
Method for preparing a semiconductor structure
Publication/Patent Number: US10553433B2 Publication Date: 2020-02-04 Application Number: 16/190,876 Filing Date: 2018-11-14 Inventor: Shih shing yih   Assignee: NANYA TECHNOLOGY CORPORATION   IPC: H01L21/033 Abstract: A method for preparing a semiconductor structure includes the following steps: providing a substrate including a first region and a second region defined thereon, forming a first mask structure over the substrate, forming a plurality of first features in the first mask structure in the first region, forming a second mask structure over the first mask structure, simultaneously forming a plurality of second features in the second mask structure in the second region and a plurality of third features in the second mask structure in the first region, and transferring the second features and the third features to the first mask structure to simultaneously form a plurality of islanding features in the first region and a plurality of line features in the second region.
16
US2020185268A1
METHOD OF FORMING FINE INTERCONNECTION FOR A SEMICONDUCTOR DEVICE
Publication/Patent Number: US2020185268A1 Publication Date: 2020-06-11 Application Number: 16/257,021 Filing Date: 2019-01-24 Inventor: Shih shing yih   Assignee: NANYA TECHNOLOGY CORPORATION   IPC: H01L21/768 Abstract: A method of forming fine interconnection includes: forming spacers on a first and second hard mask layer on a dielectric layer; forming a first via hole through the first hard mask layer, the second hard mask layer, and the dielectric layer; oxidizing a sidewall of the first hard mask layer that surrounding the via hole; forming a second via hole in the second hard mask layer; forming a mask to cover the first hard mask layer in the second via hole; forming a line trench in a portion of the second hard mask layer exposed by the spacers and the mask, and in the first hard mask layer and the dielectric layer that are below the portion of the second hard mask layer; and forming a conductive material in the line trench and the first via hole.
17
US10529586B2
Method of manufacturing semiconductor device
Publication/Patent Number: US10529586B2 Publication Date: 2020-01-07 Application Number: 15/989,194 Filing Date: 2018-05-25 Inventor: Shih shing yih   Assignee: NANYA TECHNOLOGY CORPORATION   IPC: H01L21/311 Abstract: A method of manufacturing semiconductor device is provided in the present disclosure. The method includes forming a first pattern layer on a first area of a substrate, forming a spin on layer on the first pattern layer and the substrate, forming an etch stop layer on the spin on layer, and forming a first mask layer on the etch stop layer.
18
US10529689B2
Semiconductor package with multiple coplanar interposers
Publication/Patent Number: US10529689B2 Publication Date: 2020-01-07 Application Number: 15/660,210 Filing Date: 2017-07-26 Inventor: Shih shing yih   Assignee: Micron Technology, Inc.   IPC: H01L23/48 Abstract: A semiconductor package includes a first interposer, a second interposer, and a gap between the first interposer and the second interposer. The first interposer and the second interposer are coplanar. A first die is mounted on the first interposer and the second interposer. The first die includes first connection elements connecting the first die to the first interposer or the second interposer. A redistribution layer (RDL) structure is disposed on bottom surfaces of the first and second interposers for connecting the first interposer with the second interposer. The RDL structure includes at least one bridge trace traversing the gap to electrically connect the first interposer with the second interposer.
19
US10818625B1
Electronic device
Publication/Patent Number: US10818625B1 Publication Date: 2020-10-27 Application Number: 16/446,087 Filing Date: 2019-06-19 Inventor: Shih shing yih   Assignee: Nanya Technology Corporation   IPC: H01L23/00 Abstract: An electronic device is provided. The electronic device includes a substrate, at least one contact pad disposed on the substrate, and a redistribution layer including a strip-shaped portion. The redistribution layer is electrically connected to the contact pad. The strip-shaped portion includes at least two strip-shaped steps, and each of the strip-shaped steps includes a plurality of peaks and valleys.
20
US10529570B1
Method for preparing a semiconductor structure
Publication/Patent Number: US10529570B1 Publication Date: 2020-01-07 Application Number: 16/210,842 Filing Date: 2018-12-05 Inventor: Shih shing yih   Assignee: NANYA TECHNOLOGY CORPORATION   IPC: H01L21/033 Abstract: A method for preparing a semiconductor structure includes the following steps. A target layer is formed over a substrate. A first patterned mask is formed over the target layer and includes plural first openings separate from each other. The first openings are filled with a first sacrificial layer. A patterned core layer is formed on the first sacrificial layer and includes plural closed patterns and plural second openings within the closed patterns of the patterned core layer. Plural spacers are formed on sidewalls of the patterned core layer. The spacers are removed to form a plurality of third openings over the substrate. The first sacrificial layer and the first patterned mask are etched through the third openings. The first sacrificial layer is removed to form a second patterned mask on the target layer. The target layer is etched through the second patterned mask to form a patterned target layer.
Total 14 pages