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No. Publication Number Title Publication/Patent Number Publication/Patent Number Publication Date Publication Date
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1 US10635528B2
Memory controller and method of controlling memory controller
Publication/Patent Number: US10635528B2 Publication Date: 2020-04-28 Application Number: 15/323,574 Filing Date: 2015-05-20 Inventor: Shinbashi, Tatsuo   Sakai, Lui   Ikegaya, Ryoji   Assignee: SONY CORPORATION   IPC: G11C29/52 Abstract: A utilization efficiency of a memory is improved. A codeword generation unit generates a codeword in an error detection and correction code from data to be encoded. A write control unit writes one of data obtained by inverting the codeword and the codeword into the memory cell as write data. A read data error correction unit reads out the write data from the memory cell as read data, and corrects an error in the read data. An inversion data error correction unit corrects an error in inversion data obtained by inverting the read data. A correction data output unit, when the number of errors of either only one of the read data and the inversion data does not exceed an error correction capability of the error detection and correction code, selects and outputs the one where the error is corrected as correction data. A utilization efficiency of a memory is improved. A codeword generation unit generates a codeword in an error detection and correction code from data to be encoded. A write control unit writes one of data obtained by inverting the codeword and the codeword into the memory cell ...More ...Less
2 US10545804B2
Memory controller, memory system, and memory controller control method
Publication/Patent Number: US10545804B2 Publication Date: 2020-01-28 Application Number: 15/507,413 Filing Date: 2015-07-22 Inventor: Shinbashi, Tatsuo   Tsutsui, Keiichi   Okubo, Hideaki   Sakai, Lui   Nakanishi, Kenichi   Fujinami, Yasushi   Assignee: Sony Corporation   IPC: G06F11/00 Abstract: [Object] To sufficiently reduce frequency of error occurrence in memory cells. [Solution] A reading unit reads read data from a memory cell, the read data including an information bit and reversal information for determining whether or not the information bit has been reversed. In addition, an error detection/correction unit detects the presence or absence of an error in the information bit and corrects the error. A data reversing unit reverses the information bit that has the error corrected and the reversal information. Furthermore, a writing unit writes the reversed information bit and the reversed reversal information in the memory cell. [Object] To sufficiently reduce frequency of error occurrence in memory cells. [Solution] A reading unit reads read data from a memory cell, the read data including an information bit and reversal information for determining whether or not the information bit has been reversed ...More ...Less
3 US2019056884A1
MEMORY CONTROLLER, STORAGE DEVICE, INFORMATION PROCESSING SYSTEM, AND MEMORY CONTROL METHOD
Publication/Patent Number: US2019056884A1 Publication Date: 2019-02-21 Application Number: 15/768,597 Filing Date: 2016-07-27 Inventor: Ishii, Ken   Iwaki, Hiroyuki   Nakanishi, Kenichi   Fujinami, Yasushi   Shinbashi, Tatsuo   Assignee: SONY CORPORATION   IPC: G06F3/06 Abstract: The write time is to be shortened in a storage device using memories that require different write times from each other, such as nonvolatile memories. In a memory controller including a plurality of write request holding units and a selection unit, the write request holding units holds a write request with respect to each of a plurality of memory modules that require different write times from one another. The selection unit selects one of the plurality of write request holding units in accordance with memory state information indicating whether each of the plurality of memory modules is in a busy state, and causes outputting of the write request. The write time is to be shortened in a storage device using memories that require different write times from each other, such as nonvolatile memories. In a memory controller including a plurality of write request holding units and a selection unit, the write request holding ...More ...Less
4 EP3451564A1
ERROR CORRECTION METHODS AND APPARATUS
Publication/Patent Number: EP3451564A1 Publication Date: 2019-03-06 Application Number: 18195190.6 Filing Date: 2011-11-03 Inventor: Shinbashi, Tatsuo   Funamoto, Kazuhisa   Matsumoto, Hideyuki   Shiroshita, Hiroshi   Maruko, Kenichi   Sugioka, Tatsuya   Koshisaka, Naohiro   Assignee: Sony Corporation   IPC: H04L1/00 Abstract: Disclosed herein is a transmission apparatus, including: an error correction code calculation section adapted to calculate an error correction code from data of a transmission object as an information word; a division section adapted to allocate coded data which configure a codeword obtained by adding the error correction code determined by the calculation by the error correction code calculation section to the data of the transmission object for each predetermined number of units to a plurality of transmission lines; and a plurality of transmission sections provided corresponding to the plural transmission lines and adapted to transmit the coded data allocated by the division section to a reception apparatus through the transmission lines. Disclosed herein is a transmission apparatus, including: an error correction code calculation section adapted to calculate an error correction code from data of a transmission object as an information word; a division section adapted to allocate coded data which configure a ...More ...Less
5 EP2456112B1
Error correction methods and apparatus
Publication/Patent Number: EP2456112B1 Publication Date: 2019-01-02 Application Number: 11187641.3 Filing Date: 2011-11-03 Inventor: Shinbashi, Tatsuo   Funamoto, Kazuhisa   Matsumoto, Hideyuki   Shiroshita, Hiroshi   Maruko, Kenichi   Sugioka, Tatsuya   Koshisaka, Naohiro   Assignee: Sony Corporation   IPC: H04L1/00 Abstract: Disclosed herein is a transmission apparatus, including: an error correction code calculation section adapted to calculate an error correction code from data of a transmission object as an information word; a division section adapted to allocate coded data which configure a codeword obtained by adding the error correction code determined by the calculation by the error correction code calculation section to the data of the transmission object for each predetermined number of units to a plurality of transmission lines; and a plurality of transmission sections provided corresponding to the plural transmission lines and adapted to transmit the coded data allocated by the division section to a reception apparatus through the transmission lines. Disclosed herein is a transmission apparatus, including: an error correction code calculation section adapted to calculate an error correction code from data of a transmission object as an information word; a division section adapted to allocate coded data which configure a ...More ...Less
6 US10481971B2
Encoding device, memory controller, communication system, and encoding method
Publication/Patent Number: US10481971B2 Publication Date: 2019-11-19 Application Number: 15/736,079 Filing Date: 2016-04-15 Inventor: Shinbashi, Tatsuo   Nakanishi, Kenichi   Fujinami, Yasushi   Iwaki, Hiroyuki   Ishii, Ken   Okubo, Hideaki   Assignee: Sony Corporation   IPC: G06F11/10 Abstract: A data holding characteristic of a memory cell is improved in a memory system in which data is encoded and written to a memory cell. A first candidate parity generation unit generates, as a first candidate parity, a parity for detecting an error in an information section in which a predetermined value is assigned in a predetermined variable area. A second candidate parity generation unit generates, as a second candidate parity, a parity for detecting an error in the information section in which a value different from the predetermined value is assigned in the predetermined variable area. A selection unit selects a parity that satisfies a predetermined condition from among the first and second candidate parities as a selection parity. An output unit outputs a codeword constituted by the information section corresponding to the selection parity and the selection parity. A data holding characteristic of a memory cell is improved in a memory system in which data is encoded and written to a memory cell. A first candidate parity generation unit generates, as a first candidate parity, a parity for detecting an error in an information section in ...More ...Less
7 US10177878B2
Information processing for detection of control code
Publication/Patent Number: US10177878B2 Publication Date: 2019-01-08 Application Number: 15/404,381 Filing Date: 2017-01-12 Inventor: Funamoto, Kazuhisa   Shinbashi, Tatsuo   Sugioka, Tatsuya   Maruko, Kenichi   Koshisaka, Naohiro   Takahashi, Hiroo   Assignee: SONY CORPORATION   IPC: H03M5/14 Abstract: There is provided an information processing device including an acquirer that acquires second data obtained by converting first data constituted by bit data having a first number of bits into symbols having a second number of bits greater than the first number of bits, with respect to each of the bit data, a comparator that compares a first symbol string constituted by a plurality of symbols contained in the second data prior to reverse conversion of the acquired second data into the first data, to a second symbol string representing a code targeted for detection, and a detector that detects the first symbol string as the code targeted for detection from the second data, on the basis of the result of the comparison by the comparator. There is provided an information processing device including an acquirer that acquires second data obtained by converting first data constituted by bit data having a first number of bits into symbols having a second number of bits greater than the first number of bits, with ...More ...Less
8 EP3211536B1
MEMORY CONTROLLER, MEMORY SYSTEM, AND MEMORY CONTROLLER CONTROL METHOD
Publication/Patent Number: EP3211536B1 Publication Date: 2019-09-04 Application Number: 15851846.4 Filing Date: 2015-07-22 Inventor: Shinbashi, Tatsuo   Tsutsui, Keiichi   Okubo, Hideaki   Sakai, Lui   Nakanishi, Kenichi   Fujinami, Yasushi   Assignee: Sony Corporation   IPC: G06F12/16