| No. | Publication Number | Title | Publication/Patent Number Publication/Patent Number |
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Application Number Application Number |
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Filing Date
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Inventor Inventor | Assignee Assignee |
IPC
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1 | EP3329313B1 |
LENS ATTACHED SUBSTRATE, LAYERED LENS STRUCTURE, CAMERA MODULE, MANUFACTURING APPARATUS, AND MANUFACTURING METHOD
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Publication/Patent Number: EP3329313B1 | Publication Date: 2021-02-17 | Application Number: 16751016.3 | Filing Date: 2016-07-15 | Inventor： Moriya, Yusuke Iwasaki, Masanori Oinoue, Takashi Hagimoto, Yoshiya Matsugai, Hiroyasu Itou, Hiroyuki Saito, Suguru Ohshima, Keiji Fujii, Nobutoshi Tazawa, Hiroshi Shiraiwa, Toshiaki Ishida, Minoru | Assignee: Sony Semiconductor Solutions Corporation | IPC: G02B13/00 | ||||
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2 | EP3329315B1 |
STACKED LENS STRUCTURE, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC APPARATUS
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Publication/Patent Number: EP3329315B1 | Publication Date: 2021-03-31 | Application Number: 16751020.5 | Filing Date: 2016-07-19 | Inventor： Yamamoto, Atsushi Takeuchi, Koichi Kurobe, Toshihiro Matsugai, Hiroyasu Itou, Hiroyuki Saito, Suguru Ohshima, Keiji Fujii, Nobutoshi Tazawa, Hiroshi Shiraiwa, Toshiaki Ishida, Minoru | Assignee: Sony Semiconductor Solutions Corporation | IPC: G02B13/00 | ||||
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3 | US2020335426A1 |
SEMICONDUCTOR DEVICE, MANUFACTURING METHOD FOR SEMICONDUCTOR, AND IMAGING UNIT
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Publication/Patent Number: US2020335426A1 | Publication Date: 2020-10-22 | Application Number: 16/761,716 | Filing Date: 2018-10-18 | Inventor： Shiraiwa, Toshiaki | Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION | IPC: H01L23/48 | Abstract: A semiconductor device including: a through hole forming region; an insulating wall; a semiconductor substrate; a side wall insulating film; and an electric conductor. The insulating wall has an inner peripheral surface surrounding the through hole forming region. The semiconductor substrate has the insulating wall buried in one of surfaces thereof. The semiconductor substrate has a through hole whose side wall is provided outwardly from the inner peripheral surface of the insulating wall. The side wall insulating film covers the side wall of the through hole and the inner peripheral surface of the insulating wall. The electric conductor is provided in the through hole of the semiconductor substrate via the side wall insulating film. | |||
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4 | EP3329312B1 |
LENS ATTACHED SUBSTRATE, LAYERED LENS STRUCTURE, MANUFACTURING METHOD THEREOF, AND ELECTRONIC DEVICE
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Publication/Patent Number: EP3329312B1 | Publication Date: 2020-09-23 | Application Number: 16751021.3 | Filing Date: 2016-07-19 | Inventor： Yoshioka, Hirotaka Matsugai, Hiroyasu Itou, Hiroyuki Saito, Suguru Ohshima, Keiji Fujii, Nobutoshi Tazawa, Hiroshi Shiraiwa, Toshiaki Ishida, Minoru | Assignee: Sony Semiconductor Solutions Corporation | IPC: G02B7/02 | ||||
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5 | US10534162B2 |
Lens attached substrate, layered lens structure, manufacturing method thereof, and electronic device
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Publication/Patent Number: US10534162B2 | Publication Date: 2020-01-14 | Application Number: 15/741,549 | Filing Date: 2016-07-19 | Inventor： Yoshioka, Hirotaka Matsugai, Hiroyasu Itou, Hiroyuki Saito, Suguru Ohshima, Keiji Fujii, Nobutoshi Tazawa, Hiroshi Shiraiwa, Toshiaki Ishida, Minoru | Assignee: Sony Semiconductor Solutions Corporation | IPC: G02B27/10 | Abstract: Substrates with lenses having lenses disposed therein are aligned with high accuracy. A stacked lens structure has a configuration in which substrates with lenses having a lens disposed on an inner side of a through-hole formed in the substrate are direct-bonded and stacked. In particular, one or more air grooves formed in surfaces of the substrates reduces an influence of air inside a void portion between adjacent lenses of a layered lens structure. | |||
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6 | US10690814B2 |
Lens substrate, semiconductor device, and electronic apparatus
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Publication/Patent Number: US10690814B2 | Publication Date: 2020-06-23 | Application Number: 15/747,302 | Filing Date: 2016-07-19 | Inventor： Shiraiwa, Toshiaki Okamoto, Masaki Matsugai, Hiroyasu Itou, Hiroyuki Saito, Suguru Ohshima, Keiji Fujii, Nobutoshi Tazawa, Hiroshi Ishida, Minoru | Assignee: Sony Semiconductor Solutions Corporation | IPC: G02B3/00 | Abstract: Influence of chipping in case of dicing a plurality of stacked substrates is reduced. Provided is a semiconductor device where a substrate, in which a groove surrounding a pattern configured with a predetermined circuit or part is formed, is stacked. The present technology can be applied to, for example, a stacked lens structure where through-holes are formed in each substrate and lenses are disposed in inner sides of the through-holes, a camera module where a stacked lens structure and a light-receiving device are incorporated, a solid-state imaging device where a pixel substrate and a control substrate are stacked, and the like. |
