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No. Publication Number Title Publication/Patent Number Publication/Patent Number Publication Date Publication Date
Application Number Application Number Filing Date Filing Date
Inventor Inventor Assignee Assignee IPC IPC
1
EP3301425B1
PRESSURE SENSOR DEVICE AND METHOD FOR FORMING A PRESSURE SENSOR DEVICE
Publication/Patent Number: EP3301425B1 Publication Date: 2021-01-20 Application Number: 16196616.3 Filing Date: 2016-10-31 Inventor: Siegert, Jörg   Besling, Willem Frederik Adrianus   Tak, Coenraad Cornelis   Schrems, Martin   Schrank, Franz   Assignee: Sciosense B.V.   IPC: G01L19/04
2
EP2665096B1
A METHOD OF WAFER-SCALE INTEGRATION OF SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICE
Publication/Patent Number: EP2665096B1 Publication Date: 2020-04-22 Application Number: 12168069.8 Filing Date: 2012-05-15 Inventor: Cassidy, Cathal   Siegert, Jörg   Schrank, Franz   Assignee: ams AG   IPC: H01L27/146
3
EP3671823A1
SEMICONDUCTOR DEVICE WITH THROUGH-SUBSTRATE VIA AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE WITH THROUGH-SUBSTRATE VIA
Publication/Patent Number: EP3671823A1 Publication Date: 2020-06-24 Application Number: 18215468.2 Filing Date: 2018-12-21 Inventor: Löffler, Bernhard   Bodner, Thomas   Siegert, Jörg   Assignee: ams AG   IPC: H01L21/768 Abstract: An intermetal dielectric (3) and metal layers (4) embedded in the intermetal dielectric (3) are arranged on a substrate (1) of semiconductor material. A via hole (7) is formed in the substrate, and a metallization (9) contacting a contact area (4*) of one of the metal layers (4') is applied in the via hole. The metallization (9), the metal layer (4') comprising the contact area (4*) and the intermetal dielectric (3) are partially removed at the bottom of the via hole in order to form a hole (16) penetrating the intermetal dielectric and extending the via hole. A continuous passivation (12) is arranged on sidewalls within the via hole (7) and the hole (16), and the metallization (9) contacts the contact area (4*) around the hole (16). Thus the presence of a thin membrane of layers, which is usually formed at the bottom of a hollow through-substrate via, is avoided.
4
EP3024029B1
Method of producing a semiconductor device comprising an aperture array
Publication/Patent Number: EP3024029B1 Publication Date: 2020-04-22 Application Number: 14193859.7 Filing Date: 2014-11-19 Inventor: Siegert, Jörg   Schrank, Franz   Schrems, Martin   Assignee: ams AG   IPC: H01L27/146
5
EP3660902A1
SEMICONDUCTOR DEVICE COMPRISING AN APERTURE ARRAY
Publication/Patent Number: EP3660902A1 Publication Date: 2020-06-03 Application Number: 20152454.3 Filing Date: 2014-11-19 Inventor: Siegert, Jörg   Schrank, Franz   Schrems, Martin   Assignee: AMS AG   IPC: H01L27/146 Abstract: A photosensor (2) is arranged in a semiconductor substrate (1) at a main surface (10), a dielectric layer (4) is arranged on or above the main surface, the dielectric layer including a metal layer (6) electrically connected with the photosensor, and an aperture layer (16) formed from an opaque or semitransparent material is arranged on or above the dielectric layer. The aperture layer is provided with an array of transparent aperture zones (18) above the photosensor, each of the aperture zones penetrating the aperture layer.
6
EP3193368B1
AN OPTOELECTRONIC DEVICE WITH A REFRACTIVE ELEMENT AND A METHOD OF PRODUCING SUCH AN OPTOELECTRONIC DEVICE
Publication/Patent Number: EP3193368B1 Publication Date: 2020-03-18 Application Number: 16151134.0 Filing Date: 2016-01-13 Inventor: Hofrichter, Jens   Schrank, Franz   Siegert, Jörg   Assignee: ams AG   IPC: H01L27/146
7
EP3550600B1
METHOD OF FORMING A THROUGH-SUBSTRATE VIA AND SEMICONDUCTOR DEVICE COMPRISING THE THROUGH-SUBSTRATE VIA
Publication/Patent Number: EP3550600B1 Publication Date: 2020-08-05 Application Number: 18165692.7 Filing Date: 2018-04-04 Inventor: Kraft, Jochen   Parteder, Georg   Jessenig, Stefan   Schrank, Franz   Siegert, Jörg   Assignee: ams AG   IPC: H01L21/768
8
EP3471146B1
METHOD FOR MANUFACTURING AN OPTICAL SENSOR AND OPTICAL SENSOR
Publication/Patent Number: EP3471146B1 Publication Date: 2020-09-09 Application Number: 17196609.6 Filing Date: 2017-10-16 Inventor: Toschkoff, Gregor   Bodner, Thomas   Schrank, Franz   Labodi, Miklos   Siegert, Jörg   Schrems, Martin   Assignee: ams AG   IPC: H01L27/146
9
EP3737925A1
CAPACITIVE PRESSURE SENSORS
Publication/Patent Number: EP3737925A1 Publication Date: 2020-11-18 Application Number: 19700376.7 Filing Date: 2019-01-10 Inventor: Besling, Willem Frederik   Pijnenburg, Remco Henricus   Vijayakumar, Kailash   Siegert, Jörg   Faes, Alessandro   Assignee: Sciosense B.V.   IPC: G01L9/00
10
EP3650827A1
METHOD OF MANUFACTURING A SEMICONDUCTOR TRANSDUCER DEVICE WITH MULTILAYER DIAPHRAGM AND SEMICONDUCTOR TRANSDUCER DEVICE WITH MULTILAYER DIAPHRAGM
Publication/Patent Number: EP3650827A1 Publication Date: 2020-05-13 Application Number: 18205008.8 Filing Date: 2018-11-07 Inventor: Faes, Alessandro   Siegert, Jörg   Besling, Willem Frederik Adrianus   Pijnenburg, Remco Henricus Wilhelmus   Assignee: ams International AG   IPC: G01L9/00 Abstract: A method of manufacturing a semiconductor transducer device comprises providing a semiconductor body (1), forming a sacrificial layer (5) above a surface of the semiconductor body (1), applying a diaphragm (10) on the sacrificial layer (5), and removing the sacrificial layer (5) by introducing an etchant into openings (11) of the diaphragm (10). Applying the diaphragm (10) comprises applying a first layer (7), reducing a roughness of a surface (15) of the first layer (7) to achieve a processed surface (16), and patterning and structuring the first layer (7) to form the openings (11).
11
EP3650826A1
SEMICONDUCTOR TRANSDUCER DEVICE WITH MULTILAYER DIAPHRAGM AND METHOD OF MANUFACTURING A SEMICONDUCTOR TRANSDUCER DEVICE WITH MULTILAYER DIAPHRAGM
Publication/Patent Number: EP3650826A1 Publication Date: 2020-05-13 Application Number: 18205001.3 Filing Date: 2018-11-07 Inventor: Faes, Alessandro   Siegert, Jörg   Besling, Willem Frederik Adrianus   Pijnenburg, Remco Henricus Wilhelmus   Assignee: ams International AG   IPC: G01L9/00 Abstract: The semiconductor transducer device comprises a diaphragm (10) suspended above a semiconductor body (1). A first layer (9) of the diaphragm (10) comprises a material that is resistant to an etchant comprising fluorine or a fluorine compound and covers a second layer (8) that comprises titanium and/or TiN. Thus the first layer (9) acts as protection layer and prevents production of residues like titanium fluorides during the etching of a sacrificial layer (5) using HF vapor to release the diaphragm (10).
12
EP3653567A1
METHOD FOR MANUFACTURING AN INTEGRATED MEMS TRANSDUCER DEVICE AND INTEGRATED MEMS TRANSDUCER DEVICE
Publication/Patent Number: EP3653567A1 Publication Date: 2020-05-20 Application Number: 18207101.9 Filing Date: 2018-11-19 Inventor: Vijayakumar, Kailash   Pijnenburg, Remco Henricus Wilhelmus   Besling, Willem Frederik Adrianus   Guillemin, Sophie   Siegert, Jörg   Assignee: ams International AG   IPC: B81C1/00 Abstract: A method for manufacturing an integrated micro-electromechanical systems, MEMS, transducer device, comprises providing a substrate body (1) with a surface, depositing an etch-stop layer (8), ESL, on the surface, depositing a sacrificial layer (3) on the ESL (8), depositing a diaphragm layer (6) on the sacrificial layer (3), and removing the sacrificial layer (3). Depositing the sacrificial layer (3) comprises depositing a first sub-layer (4) of a first material and depositing a second sub-layer (5) of a second material, wherein the first and the second material are different materials.
13
EP3141941B1
SEMICONDUCTOR DEVICE WITH PHOTONIC AND ELECTRONIC FUNCTIONALITY AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE
Publication/Patent Number: EP3141941B1 Publication Date: 2019-11-27 Application Number: 15184698.7 Filing Date: 2015-09-10 Inventor: Kraft, Jochen   Siegert, Jörg   Assignee: ams AG   IPC: G02B6/43
14
DE102017126259A1
Exoskelett-System, Steuereinrichtung und Verfahren
Publication/Patent Number: DE102017126259A1 Publication Date: 2019-05-09 Application Number: 102017126259 Filing Date: 2017-11-09 Inventor: Schneider, Urs   Siegert, Jörg   Assignee: UNIVERSITÄT STUTTGART   IPC: B25J11/00 Abstract: Exoskelett-System (1) aufweisend:- eine erste Exoskeletteinheit (11) zur Unterstützung eines ersten Körperteils (21);- eine zweite Exoskeletteinheit (12) zur Unterstützung eines zweiten Körperteils (22); und- eine Steuereinrichtung (30); wobei die Steuereinrichtung dazu ausgebildet ist, die erste Exoskeletteinheit (11) und/oder die zweite Exoskeletteinheit (12) basierend auf einem Regelungsmodell (31) anzusteuern, wobei das Regelungsmodell auf einem Mehrkörpersystem (32) basiert, welches- die erste Exoskeletteinheit (11);- die zweite Exoskeletteinheit (12); und- den ersten und/oder zweiten Körperteil (21, 22) modelliert; und wobei die erste Exoskeletteinheit (11) und die zweite Exoskeletteinheit (12) mechanisch voneinander entkoppelt sind.
15
DE102017126259B4
Exoskelett-System, Steuereinrichtung und Verfahren
Publication/Patent Number: DE102017126259B4 Publication Date: 2019-08-01 Application Number: 102017126259 Filing Date: 2017-11-09 Inventor: Schneider, Urs   Siegert, Jörg   Assignee: UNIVERSITÄT STUTTGART   IPC: B25J11/00 Abstract: Exoskelett-System (1) aufweisend:- eine erste Exoskeletteinheit (11) zur Unterstützung eines ersten Körperteils (21);- eine zweite Exoskeletteinheit (12) zur Unterstützung eines zweiten Körperteils (22); und- eine Steuereinrichtung (30); wobei die Steuereinrichtung dazu ausgebildet ist, die erste Exoskeletteinheit (11) und/oder die zweite Exoskeletteinheit (12) basierend auf einem Regelungsmodell (31) anzusteuern, wobei das Regelungsmodell auf einem Mehrkörpersystem (32) basiert, welches- die erste Exoskeletteinheit (11);- die zweite Exoskeletteinheit (12); und- den ersten und/oder zweiten Körperteil (21, 22) modelliert; und wobei die erste Exoskeletteinheit (11) und die zweite Exoskeletteinheit (12) mechanisch voneinander entkoppelt sind.
16
EP3168603B1
METHOD FOR MANUFACTURING A SEMICONDUCTOR COMPONENT
Publication/Patent Number: EP3168603B1 Publication Date: 2019-06-19 Application Number: 15194108.5 Filing Date: 2015-11-11 Inventor: Richter, Helene   Bodner, Thomas   Siegert, Jörg   Assignee: ams AG   IPC: G01N21/64
17
EP3569568A1
METHOD FOR MANUFACTURING AN ETCH STOP LAYER AND MEMS SENSOR COMPRISING AN ETCH STOP LAYER
Publication/Patent Number: EP3569568A1 Publication Date: 2019-11-20 Application Number: 18173267.8 Filing Date: 2018-05-18 Inventor: Faes, Alessandro   Guillemin, Sophie   Siegert, Jörg   Tuttner, Karl   Assignee: ams AG   IPC: B81C1/00 Abstract: The invention relates to a method for manufacturing a planarized etch-stop layer (13), ESL, for a hydrofluoric acid, HF, vapor phase etching process. The method comprises providing a first planarized layer (17) on top of a surface of a substrate (10), the first planarized layer (17) comprising a patterned and structured metallic material (20) and a filling material (22). The method further comprises depositing on top of the first planarized layer (17) the planarized ESL (13) of an ESL material (23) with low HF etch rate, wherein the planarized ESL (13) has a low surface roughness and a thickness of less than 150nm, in particular of less than 100nm.
18
WO2019219479A1
METHOD FOR MANUFACTURING AN ETCH STOP LAYER AND MEMS SENSOR COMPRISING AN ETCH STOP LAYER
Publication/Patent Number: WO2019219479A1 Publication Date: 2019-11-21 Application Number: 2019061823 Filing Date: 2019-05-08 Inventor: Siegert, JÖrg   Faes, Alessandro   Guillemin, Sophie   Tuttner, Karl   Assignee: AMS AG   IPC: B81C1/00 Abstract: The invention relates to a method for manufacturing a planarized etch-stop layer (13), ESL, for a hydrofluoric acid, HF, vapor phase etching process. The method comprises providing a first planarized layer (17) on top of a surface of a substrate (10), the first planarized layer (17) comprising a patterned and structured metallic material (20) and a filling material (22). The method further comprises depositing on top of the first planarized layer (17) the planarized ESL (13) of an ESL material (23) with low HF etch rate, wherein the planarized ESL (13) has a low surface roughness and a thickness of less than 150nm, in particular of less than 100nm.
19
EP2648214B1
Methods of producing a semiconductor device with a through-substrate via
Publication/Patent Number: EP2648214B1 Publication Date: 2019-06-12 Application Number: 12163391.1 Filing Date: 2012-04-05 Inventor: Löffler, Bernhard   Rohracher, Karl   Schrank, Franz   Siegert, Jörg   Kraft, Jochen   Assignee: ams AG   IPC: H01L21/768
20
WO2019193067A1
METHOD OF FORMING A THROUGH-SUBSTRATE VIA AND A SEMICONDUCTOR DEVICE COMPRISING A THROUGH-SUBSTRATE VIA
Publication/Patent Number: WO2019193067A1 Publication Date: 2019-10-10 Application Number: 2019058430 Filing Date: 2019-04-03 Inventor: Schrank, Franz   Kraft, Jochen   Jessenig, Stefan   Siegert, JÖrg   Parteder, Georg   Assignee: AMS AG   IPC: H01L23/48 Abstract: A substrate (1) is provided with a dielectric (2), a metal layer (3) embedded in the dielectric, and a metallic layer (4) arranged on the metal layer between the substrate and the metal layer. A via hole (9) is formed in the substrate and in a region of the dielectric that is between the substrate and the metal layer. An insulation layer (11) is applied in the via hole and removed from above a contact area (10) of the metal layer, and the metallic layer is completely removed from the contact area (10). A metallization (12) is applied in the via hole on the contact area.
Total 3 pages