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No. Publication Number Title Publication/Patent Number Publication/Patent Number Publication Date Publication Date
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1
US2021028290A1
Novel Structure for Metal Gate Electrode and Method of Fabrication
Publication/Patent Number: US2021028290A1 Publication Date: 2021-01-28 Application Number: 16/692,571 Filing Date: 2019-11-22 Inventor: Hsiao, Ru-shang   Su ching hwanq   Kung, Pohan   Lu, Ying Hsin   Huang, I-shan   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L29/423 Abstract: A semiconductor device includes a channel component of a transistor and a gate component disposed over the channel component. The gate component includes: a dielectric layer, a first work function metal layer disposed over the dielectric layer, a fill-metal layer disposed over the first work function metal layer, and a second work function metal layer disposed over the fill-metal layer.
2
US2021043772A1
FinFET Structures and Methods of Forming the Same
Publication/Patent Number: US2021043772A1 Publication Date: 2021-02-11 Application Number: 17/077,383 Filing Date: 2020-10-22 Inventor: Wang, Yu-sheng   Hung, Chi-cheng   Lee, Chia-ching   Wu, Chung-chiang   Su ching hwanq   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L29/78 Abstract: A method includes forming a first semiconductor fin protruding from a substrate and forming a gate stack over the first semiconductor fin. Forming the gate stack includes depositing a gate dielectric layer over the first semiconductor fin, depositing a first seed layer over the gate dielectric layer, depositing a second seed layer over the first seed layer, wherein the second seed layer has a different structure than the first seed layer, and depositing a conductive layer over the second seed layer, wherein the first seed layer, the second seed layer, and the conductive layer include the same conductive material. The method also includes forming source and drain regions adjacent the gate stack.
3
US2021057280A1
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE
Publication/Patent Number: US2021057280A1 Publication Date: 2021-02-25 Application Number: 16/549,195 Filing Date: 2019-08-23 Inventor: Wu, Chung-chiang   Chung, Hung-chin   Lee, Hsien-ming   Chen, Chien-hao   Su ching hwanq   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L21/8234 Abstract: Semiconductor devices and methods of manufacturing semiconductor devices with differing threshold voltages are provided. In embodiments the threshold voltages of individual semiconductor devices are tuned through the removal and placement of differing materials within each of the individual gate stacks within a replacement gate process, whereby the removal and placement helps keep the overall process window for a fill material large enough to allow for a complete fill.
4
US2020328299A1
Semiconductor Device and Method of Manufacture
Publication/Patent Number: US2020328299A1 Publication Date: 2020-10-15 Application Number: 16/382,777 Filing Date: 2019-04-12 Inventor: Lee, Hsin-yi   Lee, Da-yuan   Su ching hwanq   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L29/78 Abstract: Semiconductor devices and methods of manufacturing semiconductor devices are provided. In embodiments a treatment process is utilized in order to introduce silicon into a p-metal work function layer. By introducing silicon into the p-metal work function layer, subsequently deposited layers which may comprise diffusable materials such as aluminum can be prevented from diffusing through the p-metal work function layer and affect the operation of the device.
5
US2020091315A1
Semiconductor Device and Methods of Manufacture
Publication/Patent Number: US2020091315A1 Publication Date: 2020-03-19 Application Number: 16/690,455 Filing Date: 2019-11-21 Inventor: Wang, Yu-sheng   Hung, Chi-cheng   Lee, Chia-ching   Su ching hwanq   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L29/66 Abstract: A semiconductor device and method of manufacturing are provided. In an embodiment a first nucleation layer is formed within an opening for a gate-last process. The first nucleation layer is treated in order to remove undesired oxygen by exposing the first nucleation layer to a precursor that reacts with the oxygen to form a gas. A second nucleation layer is then formed, and a remainder of the opening is filled with a bulk conductive material.
6
US2020350414A1
Selective Etching to Increase Threshold Voltage Spread
Publication/Patent Number: US2020350414A1 Publication Date: 2020-11-05 Application Number: 16/398,922 Filing Date: 2019-04-30 Inventor: Lee, Hsin-yi   Li, Ya-huei   Lee, Da-yuan   Su ching hwanq   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L29/40 Abstract: A method includes forming a gate dielectric comprising a portion extending on a semiconductor region, forming a barrier layer comprising a portion extending over the portion of the gate dielectric, forming a work function tuning layer comprising a portion over the portion of the barrier layer, doping a doping element into the work function tuning layer, removing the portion of the work function tuning layer, thinning the portion of the barrier layer, and forming a work function layer over the portion of the barrier layer.
7
US10755938B2
Metal gate and manufacturing method thereof
Publication/Patent Number: US10755938B2 Publication Date: 2020-08-25 Application Number: 15/996,789 Filing Date: 2018-06-04 Inventor: Hung, Chi-cheng   Wang, Yu-sheng   Su, Ting-siang   Su ching hwanq   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.   IPC: H01L21/285 Abstract: The present disclosure provides a semiconductor structure, including an active region with a first surface; an isolated region having a second surface, surrounding the active region, the first surface being higher than the second surface; and a metal gate having a plurality of metal layers disposed over the first surface and the second surface. A ratio of a thinnest portion and a thickest portion of at least one of the plurality of metal layers is greater than about 40%.
8
US10867848B2
Semiconductor device and method
Publication/Patent Number: US10867848B2 Publication Date: 2020-12-15 Application Number: 15/967,497 Filing Date: 2018-04-30 Inventor: Wu, Chung-chiang   Tsau, Hsueh Wen   Lee, Chia-ching   Hung, Cheng-lung   Su ching hwanq   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L21/70 Abstract: A method includes forming an opening in a dielectric layer, depositing a seed layer in the opening, wherein first portions of the seed layer have a first concentration of impurities, exposing the first portions of the seed layer to a plasma, wherein after exposure to the plasma the first portions have a second concentration of impurities that is less than the first concentration of impurities, and filling the opening with a conductive material to form a conductive feature. In an embodiment, the seed layer includes tungsten, and the conductive material includes tungsten. In an embodiment, the impurities include boron.
9
US2020006157A1
Method for Patterning a Lanthanum Containing Layer
Publication/Patent Number: US2020006157A1 Publication Date: 2020-01-02 Application Number: 16/569,820 Filing Date: 2019-09-13 Inventor: Lee, Kun-yu   Chang, Huicheng   Chang, Che-hao   Su ching hwanq   Chang, Weng   Yu, Xiong-fei   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L21/8238 Abstract: Embodiments described herein relate to a method for patterning a doping layer, such as a lanthanum containing layer, used to dope a high-k dielectric layer in a gate stack of a FinFET device for threshold voltage tuning. A blocking layer may be formed between the doping layer and a hard mask layer used to pattern the doping layer. In an embodiment, the blocking layer may include or be aluminum oxide (AlOx). The blocking layer can prevent elements from the hard mask layer from diffusing into the doping layer, and thus, can improve reliability of the devices formed. The blocking layer can also improve a patterning process by reducing patterning induced defects.
10
US2020075765A1
FinFET Structures and Methods of Forming the Same
Publication/Patent Number: US2020075765A1 Publication Date: 2020-03-05 Application Number: 16/675,306 Filing Date: 2019-11-06 Inventor: Wang, Yu-sheng   Hung, Chi-cheng   Lee, Chia-ching   Wu, Chung-chiang   Su ching hwanq   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L29/78 Abstract: A method includes forming a first semiconductor fin protruding from a substrate and forming a gate stack over the first semiconductor fin. Forming the gate stack includes depositing a gate dielectric layer over the first semiconductor fin, depositing a first seed layer over the gate dielectric layer, depositing a second seed layer over the first seed layer, wherein the second seed layer has a different structure than the first seed layer, and depositing a conductive layer over the second seed layer, wherein the first seed layer, the second seed layer, and the conductive layer include the same conductive material. The method also includes forming source and drain regions adjacent the gate stack.
11
US202006157A1
Method for Patterning a Lanthanum Containing Layer
Publication/Patent Number: US202006157A1 Publication Date: 2020-01-02 Application Number: 20/191,656 Filing Date: 2019-09-13 Inventor: Chang, Weng   Yu, Xiong-fei   Lee, Kun-yu   Chang, Huicheng   Su ching hwanq   Chang, Che-hao   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L27/092 Abstract: Embodiments described herein relate to a method for patterning a doping layer, such as a lanthanum containing layer, used to dope a high-k dielectric layer in a gate stack of a FinFET device for threshold voltage tuning. A blocking layer may be formed between the doping layer and a hard mask layer used to pattern the doping layer. In an embodiment, the blocking layer may include or be aluminum oxide (AlOx). The blocking layer can prevent elements from the hard mask layer from diffusing into the doping layer, and thus, can improve reliability of the devices formed. The blocking layer can also improve a patterning process by reducing patterning induced defects.
12
US2020083115A1
Method for Patterning a Lanthanum Containing Layer
Publication/Patent Number: US2020083115A1 Publication Date: 2020-03-12 Application Number: 16/686,365 Filing Date: 2019-11-18 Inventor: Lee, Kun-yu   Chang, Huicheng   Chang, Che-hao   Su ching hwanq   Chang, Weng   Yu, Xiong-fei   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L21/8238 Abstract: Embodiments described herein relate to a method for patterning a doping layer, such as a lanthanum containing layer, used to dope a high-k dielectric layer in a gate stack of a FinFET device for threshold voltage tuning. A blocking layer may be formed between the doping layer and a hard mask layer used to pattern the doping layer. In an embodiment, the blocking layer may include or be aluminum oxide (AlOx). The blocking layer can prevent elements from the hard mask layer from diffusing into the doping layer, and thus, can improve reliability of the devices formed. The blocking layer can also improve a patterning process by reducing patterning induced defects.
13
US10833196B2
FinFET structures and methods of forming the same
Publication/Patent Number: US10833196B2 Publication Date: 2020-11-10 Application Number: 16/675,306 Filing Date: 2019-11-06 Inventor: Wang, Yu-sheng   Hung, Chi-cheng   Lee, Chia-ching   Wu, Chung-chiang   Su ching hwanq   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L29/78 Abstract: A method includes forming a first semiconductor fin protruding from a substrate and forming a gate stack over the first semiconductor fin. Forming the gate stack includes depositing a gate dielectric layer over the first semiconductor fin, depositing a first seed layer over the gate dielectric layer, depositing a second seed layer over the first seed layer, wherein the second seed layer has a different structure than the first seed layer, and depositing a conductive layer over the second seed layer, wherein the first seed layer, the second seed layer, and the conductive layer include the same conductive material. The method also includes forming source and drain regions adjacent the gate stack.
14
US10847637B2
Semiconductor device and method
Publication/Patent Number: US10847637B2 Publication Date: 2020-11-24 Application Number: 16/397,859 Filing Date: 2019-04-29 Inventor: Chiu, Shih-hang   Wu, Chung-chiang   Lee, Chia-ching   Lee, Da-yuan   Su ching hwanq   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L29/00 Abstract: A method includes forming a dummy gate structure over a semiconductor fin, forming a dielectric layer on opposing sides of the dummy gate structure, and removing the dummy gate structure to form a recess in the dielectric layer. The method further includes forming a gate dielectric layer and at least one conductive layer successively over sidewalls and a bottom of the recess, and treating the gate dielectric layer and the at least one conductive layer with a chemical containing fluoride (F).
15
US10867869B2
Method for patterning a lanthanum containing layer
Publication/Patent Number: US10867869B2 Publication Date: 2020-12-15 Application Number: 16/686,365 Filing Date: 2019-11-18 Inventor: Lee, Kun-yu   Chang, Huicheng   Chang, Che-hao   Su ching hwanq   Chang, Weng   Yu, Xiong-fei   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L21/8238 Abstract: Embodiments described herein relate to a method for patterning a doping layer, such as a lanthanum containing layer, used to dope a high-k dielectric layer in a gate stack of a FinFET device for threshold voltage tuning. A blocking layer may be formed between the doping layer and a hard mask layer used to pattern the doping layer. In an embodiment, the blocking layer may include or be aluminum oxide (AlOx). The blocking layer can prevent elements from the hard mask layer from diffusing into the doping layer, and thus, can improve reliability of the devices formed. The blocking layer can also improve a patterning process by reducing patterning induced defects.
16
US2020388616A1
Semiconductor Device and Method
Publication/Patent Number: US2020388616A1 Publication Date: 2020-12-10 Application Number: 17/000,632 Filing Date: 2020-08-24 Inventor: Wu, Chung-chiang   Chiu, Shih-hang   Hung, Chih-chang   Yang, I-wei   Ku, Shu-yuan   Hung, Cheng-lung   Lee, Da-yuan   Su ching hwanq   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L27/088 Abstract: A method includes forming a first semiconductor fin in a substrate, forming a metal gate structure over the first semiconductor fin, removing a portion of the metal gate structure to form a first recess in the metal gate structure that is laterally separated from the first semiconductor fin by a first distance, wherein the first distance is determined according to a first desired threshold voltage associated with the first semiconductor fin, and filling the recess with a dielectric material.
17
US10868013B2
Semiconductor device and method
Publication/Patent Number: US10868013B2 Publication Date: 2020-12-15 Application Number: 16/716,248 Filing Date: 2019-12-16 Inventor: Tsai, Cheng-yen   Huang, Ming-chi   Chen, Zoe   Lee, Wei-chin   Hung, Cheng-lung   Lee, Da-yuan   Chang, Weng   Su ching hwanq   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L27/092 Abstract: In an embodiment, a method includes: forming a gate dielectric layer on an interface layer; forming a doping layer on the gate dielectric layer, the doping layer including a dipole-inducing element; annealing the doping layer to drive the dipole-inducing element through the gate dielectric layer to a first side of the gate dielectric layer adjacent the interface layer; removing the doping layer; forming a sacrificial layer on the gate dielectric layer, a material of the sacrificial layer reacting with residual dipole-inducing elements at a second side of the gate dielectric layer adjacent the sacrificial layer; removing the sacrificial layer; forming a capping layer on the gate dielectric layer; and forming a gate electrode layer on the capping layer.
18
US202043781A1
Semiconductor Device and Method
Publication/Patent Number: US202043781A1 Publication Date: 2020-02-06 Application Number: 20/191,659 Filing Date: 2019-10-11 Inventor: Tsai, Ming-hsing   Wang, Yu-sheng   Hung, Chi-cheng   Su ching hwanq   Lin, Yu-ting   Ou, Yang Liang-yueh   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L29/66 Abstract: A method includes forming a first opening in a dielectric layer over a substrate, lining sidewalls and a bottom of the first opening with a conductive barrier layer, and depositing a seed layer over the conductive barrier layer. The method further includes treating the seed layer with a plasma process, and filling the first opening with a conductive material after the treating the seed layer.
19
US10756087B2
Semiconductor device and method
Publication/Patent Number: US10756087B2 Publication Date: 2020-08-25 Application Number: 16/010,366 Filing Date: 2018-06-15 Inventor: Wu, Chung-chiang   Chiu, Shih-hang   Hung, Chih-chang   Yang, I-wei   Ku, Shu-yuan   Hung, Cheng-lung   Lee, Da-yuan   Su ching hwanq   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L27/088 Abstract: A method includes forming a first semiconductor fin in a substrate, forming a metal gate structure over the first semiconductor fin, removing a portion of the metal gate structure to form a first recess in the metal gate structure that is laterally separated from the first semiconductor fin by a first distance, wherein the first distance is determined according to a first desired threshold voltage associated with the first semiconductor fin, and filling the recess with a dielectric material.
20
US2020043781A1
Semiconductor Device and Method
Publication/Patent Number: US2020043781A1 Publication Date: 2020-02-06 Application Number: 16/599,940 Filing Date: 2019-10-11 Inventor: Wang, Yu-sheng   Hung, Chi-cheng   Su ching hwanq   Ou, Yang Liang-yueh   Tsai, Ming-hsing   Lin, Yu-ting   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L21/768 Abstract: