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No. Publication Number Title Publication/Patent Number Publication/Patent Number Publication Date Publication Date
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1
US2021028234A1
SOLID STATE IMAGE SENSOR, PRODUCTION METHOD THEREOF AND ELECTRONIC DEVICE
Publication/Patent Number: US2021028234A1 Publication Date: 2021-01-28 Application Number: 17/068,398 Filing Date: 2020-10-12 Inventor: Joei, Masahiro   Takimoto, Kaori   Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION   IPC: H01L27/30 Abstract: A solid state image sensor includes a semiconductor substrate where photoelectric conversion regions for converting light into charges are arranged per pixel planarly arranged; an organic photoelectric conversion film laminated at a light irradiated side of the semiconductor substrate via an insulation film and formed at the regions where the pixels are formed; a lower electrode formed at and in contact with the organic photoelectric conversion film at a semiconductor substrate side; a first upper electrode laminated at a light irradiated side of the organic photoelectric conversion film and formed such that ends of the first upper electrode are substantially conform with ends of the organic photoelectric conversion film when the solid state image sensor is planarly viewed; and a film stress suppressor for suppressing an effect of a film stress on the organic photoelectric conversion film, the film stress being generated on the first upper electrode.
2
US10804312B2
Semiconductor device and electronic device having a chip size package (CSP)
Publication/Patent Number: US10804312B2 Publication Date: 2020-10-13 Application Number: 16/516,785 Filing Date: 2019-07-19 Inventor: Nagata, Masaya   Takimoto, Kaori   Assignee: Sony Corporation   IPC: H01L27/14 Abstract: The present disclosure relates to a semiconductor device, an electronic device, and a manufacturing method that can maintain the mounting reliability of an underfill. A chip is formed by a circuit 5 of an imaging element being produced on a Si substrate that is a first substrate and a second substrate being produced on an adhesive formed on the circuit. In this event, a photosensitive material is formed around the chip after the chip is mounted on a mounting substrate by a solder ball or in the state of the chip, then an underfill is formed, and then only the photosensitive 10 material is dissolved. The present disclosure can be applied to, for example, a CMOS solid-state imaging sensor used for an imaging device such as a camera.
3
US10840303B2
Solid state image sensor, production method thereof and electronic device
Publication/Patent Number: US10840303B2 Publication Date: 2020-11-17 Application Number: 16/378,339 Filing Date: 2019-04-08 Inventor: Joei, Masahiro   Takimoto, Kaori   Assignee: Sony Semiconductor Solutions Corporation   IPC: H01L27/30 Abstract: A solid state image sensor includes a semiconductor substrate where photoelectric conversion regions for converting light into charges are arranged per pixel planarly arranged; an organic photoelectric conversion film laminated at a light irradiated side of the semiconductor substrate via an insulation film and formed at the regions where the pixels are formed; a lower electrode formed at and in contact with the organic photoelectric conversion film at a semiconductor substrate side; a first upper electrode laminated at a light irradiated side of the organic photoelectric conversion film and formed such that ends of the first upper electrode are substantially conform with ends of the organic photoelectric conversion film when the solid state image sensor is planarly viewed; and a film stress suppressor for suppressing an effect of a film stress on the organic photoelectric conversion film, the film stress being generated on the first upper electrode.
4
US2020357838A1
LAMINATED LENS STRUCTURE, SOLID-STATE IMAGING ELEMENT, AND ELECTRONIC APPARATUS
Publication/Patent Number: US2020357838A1 Publication Date: 2020-11-12 Application Number: 16/640,898 Filing Date: 2018-08-17 Inventor: Fukuyama, Munekatsu   Yoshioka, Hirotaka   Hikichi, Kunihiko   Yamamoto, Atsushi   Takimoto, Kaori   Ishida, Minoru   Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION   IPC: H01L27/146 Abstract: Provided is a laminated lens structure capable of corresponding various optical parameters. The laminated lens structure includes at least one or more sheets of first lens-attached substrates and at least one or more sheets of second lens-attached substrates as a lens-attached substrate including a lens resin portion that forms a lens, and a carrier substrate that carries the lens resin portion. The carrier substrate of the first lens-attached substrates is constituted by laminating a plurality of sheets of carrier configuration substrates in a thickness direction, and the carrier substrate of the second lens-attached substrates is constituted by one sheet of carrier configuration substrate. For example, the present technology is applicable to a camera module and the like.
5
EP3676649A1
LAMINATED LENS STRUCTURE, SOLID-STATE IMAGING ELEMENT, AND ELECTRONIC APPARATUS
Publication/Patent Number: EP3676649A1 Publication Date: 2020-07-08 Application Number: 18762940.7 Filing Date: 2018-08-17 Inventor: Fukuyama, Munekatsu   Yoshioka, Hirotaka   Hikichi, Kunihiko   Yamamoto, Atsushi   Takimoto, Kaori   Ishida, Minoru   Assignee: Sony Semiconductor Solutions Corporation   IPC: G02B13/00
6
EP3706169A1
BACKSIDE IRRADIATION TYPE SOLID-STATE IMAGING DEVICE, METHOD FOR MANUFACTURING BACKSIDE IRRADIATION TYPE SOLID-STATE IMAGING DEVICE, IMAGING DEVICE, AND ELECTRONIC APPARATUS
Publication/Patent Number: EP3706169A1 Publication Date: 2020-09-09 Application Number: 18872679.8 Filing Date: 2018-10-16 Inventor: Takachi, Taizo   Yamamoto, Yuichi   Saito, Suguru   Wakiyama, Satoru   Ootsuka, Yoichi   Komai, Naoki   Takimoto, Kaori   Iijima, Tadashi   Haneda, Masaki   Nagata, Masaya   Assignee: Sony Semiconductor Solutions Corporation   IPC: H01L27/146 Abstract: The present disclosure relates to a backside illumination type solid-state imaging device, a manufacturing method for a backside illumination type solid-state imaging device, an imaging apparatus, and electronic equipment by which the manufacturing cost can be reduced. A singulated memory circuit and a singulated logic circuit are laid out in a horizontal direction and are embedded by an oxide film and flattened, and then are stacked so as to be contained in a plane direction under a solid-state imaging element. The present disclosure can be applied to an imaging apparatus.
7
US2020258924A1
BACKSIDE ILLUMINATION TYPE SOLID-STATE IMAGING DEVICE, MANUFACTURING METHOD FOR BACKSIDE ILLUMINATION TYPE SOLID-STATE IMAGING DEVICE, IMAGING APPARATUS AND ELECTRONIC EQUIPMENT
Publication/Patent Number: US2020258924A1 Publication Date: 2020-08-13 Application Number: 16/758,535 Filing Date: 2018-10-16 Inventor: Takachi, Taizo   Yamamoto, Yuichi   Saito, Suguru   Wakiyama, Satoru   Ootsuka, Yoichi   Komai, Naoki   Takimoto, Kaori   Iijima, Tadashi   Haneda, Masaki   Nagata, Masaya   Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION   IPC: H01L27/146 Abstract: The present disclosure relates to a backside illumination type solid-state imaging device, a manufacturing method for a backside illumination type solid-state imaging device, an imaging apparatus, and electronic equipment by which the manufacturing cost can be reduced. A singulated memory circuit and a singulated logic circuit are laid out in a horizontal direction and are embedded by an oxide film and flattened, and then are stacked so as to be contained in a plane direction under a solid-state imaging element. The present disclosure can be applied to an imaging apparatus.
8
US10403669B2
Semiconductor device and electronic device having a chip size package (CSP) stack
Publication/Patent Number: US10403669B2 Publication Date: 2019-09-03 Application Number: 15/580,552 Filing Date: 2016-06-02 Inventor: Nagata, Masaya   Takimoto, Kaori   Assignee: Sony Corporation   IPC: H01L27/14 Abstract: The present disclosure relates to a semiconductor device, an electronic device, and a manufacturing method that can maintain the mounting reliability of an underfill. A chip is formed by a circuit of an imaging element being produced on a Si substrate that is a first substrate and a second substrate being produced on an adhesive formed on the circuit. In this event, a photosensitive material is formed around the chip after the chip is mounted on a mounting substrate by a solder ball or in the state of the chip, then an underfill is formed, and then only the photosensitive material is dissolved. The present disclosure can be applied to, for example, a CMOS solid-state imaging sensor used for an imaging device such as a camera.
9
US2019341417A1
SEMICONDUCTOR DEVICE, ELECTRONIC DEVICE, AND MANUFACTURING METHOD
Publication/Patent Number: US2019341417A1 Publication Date: 2019-11-07 Application Number: 16/516,785 Filing Date: 2019-07-19 Inventor: Nagata, Masaya   Takimoto, Kaori   Assignee: Sony Corporation   IPC: H01L27/146 Abstract: The present disclosure relates to a semiconductor device, an electronic device, and a manufacturing method that can maintain the mounting reliability of an underfill. A chip is formed by a circuit of an imaging element being produced on a Si substrate that is a first substrate and a second substrate being produced on an adhesive formed on the circuit. In this event, a photosensitive material is formed around the chip after the chip is mounted on a mounting substrate by a solder ball or in the state of the chip, then an underfill is formed, and then only the photosensitive material is dissolved. The present disclosure can be applied to, for example, a CMOS solid-state imaging sensor used for an imaging device such as a camera.
10
KR20190105596A
적층 렌즈 구조체 및 그 제조 방법, 및 전자기기
Publication/Patent Number: KR20190105596A Publication Date: 2019-09-17 Application Number: 20197021360 Filing Date: 2018-01-16 Inventor: Yamamoto, Atsushi   Takimoto, Kaori   Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION   IPC: G02B3/00 Abstract: 적층 렌즈 구조체의 기판에 있어서의 치핑이나 크랙의 발생을 억제할 수 있다. 적층 렌즈 구조체가, 기판에 형성된 관통공의 내측에 렌즈가 배치되어 있으며 직접 접합에 의해 서로 적층되어 있는 렌즈 부착 기판을 포함하고, 상기 기판들 각각은 그 외주 근방에 당해 기판을 관통하는 관통홈을 구비한다. 본 기술은, 예를 들면, 복안 카메라 모듈 등에 적용할 수 있다.
11
US2019369299A1
LAMINATED LENS STRUCTURE AND METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC APPARATUS
Publication/Patent Number: US2019369299A1 Publication Date: 2019-12-05 Application Number: 16/478,021 Filing Date: 2018-01-16 Inventor: Yamamoto, Atsushi   Takimoto, Kaori   Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION   IPC: G02B3/00 Abstract: To make it possible to restrain generation of chipping or cracking in a substrate of a laminated lens structure. A laminated lens structure includes substrates with lens which each have a lens disposed inside a through-hole formed in the substrate and which are laminated on one another by direct bonding, in which the substrates are each provided in the vicinity of the outer circumference thereof with through grooves penetrating the substrate. The present technology is applicable, for example, to a compound eye camera module.