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1 US2020203426A1
SEMICONDUCTOR DEVICE
Publication/Patent Number: US2020203426A1 Publication Date: 2020-06-25 Application Number: 16/615,243 Filing Date: 2018-04-17 Inventor: Terada, Haruhiko   Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION   IPC: H01L27/24 Abstract: A semiconductor device according to the present disclosure includes: a plurality of first selection lines provided in a region other than a plurality of opening regions in a first region in a first selection line layer, and having a predetermined width, the plurality of first selection lines extending in a first direction and disposed side by side in a second direction, the second direction intersecting with the first direction; a first metal wiring line formed in a layer above the first selection line layer; a first through wiring line penetrating an insulating layer formed on the first selection line layer, and coupling a first line of the plurality of first selection lines and the first metal wiring line to each other; a second through wiring line provided in a first opening region of the plurality of opening regions, and penetrating the first selection line layer, the second through wiring line having one end coupled to the first metal wiring line; a first storage element having a first terminal, and a second terminal coupled to the first line; and a first drive circuit that is coupled to another end of the second through wiring line, and drives the plurality of first selection lines. A semiconductor device according to the present disclosure includes: a plurality of first selection lines provided in a region other than a plurality of opening regions in a first region in a first selection line layer, and having a predetermined width, the plurality of first ...More Less
2 US2020202931A1
SEMICONDUCTOR DEVICE
Publication/Patent Number: US2020202931A1 Publication Date: 2020-06-25 Application Number: 16/614,483 Filing Date: 2018-04-05 Inventor: Terada, Haruhiko   Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION   IPC: G11C13/00 Abstract: The semiconductor device of the present disclosure includes a plurality of first selection lines provided in a first region, extending in a first direction, and aligned in a second direction; a plurality of second selection lines provided in a second region having a portion that overlaps a portion of the first region, extending in the second direction, and aligned in the first direction; a plurality of third selection lines provided in a third region having a portion that overlaps a portion of the second region, extending in the first direction, and aligned in the second direction; a plurality of fourth selection lines provided in a fourth region having one portion that overlaps a portion of the first region and having another portion that overlaps a portion of the third region, extending in the second direction, and aligned in the first direction; a first coupling part, a first coupling part, a first coupling part, and a first coupling part coupled, respectively, to the plurality of first selection lines, the plurality of second selection lines, the plurality of third selection lines, and the plurality of fourth selection lines; a driver; and memory cells. The semiconductor device of the present disclosure includes a plurality of first selection lines provided in a first region, extending in a first direction, and aligned in a second direction; a plurality of second selection lines provided in a second region having a portion that ...More Less
3 US10664343B2
Memory controller, non-volatile memory, and method of controlling memory controller
Publication/Patent Number: US10664343B2 Publication Date: 2020-05-26 Application Number: 16/072,831 Filing Date: 2016-12-01 Inventor: Terada, Haruhiko   Assignee: Sony Corporation   IPC: G06F11/10 Abstract: To suppress an increase in a voltage drop in a non-volatile memory including a variable resistive element installed therein. A memory controller includes a voltage drop amount estimating unit and an encoding unit. The voltage drop amount estimating unit estimates a voltage drop amount from a wiring resistance of a wiring up to a memory cell and a leakage current occurring in the memory cell when original data is caused to be held in the memory cell. The encoding unit performs a predetermined encoding process on the original data in a case in which the estimated voltage drop amount exceeds a predetermined threshold value. To suppress an increase in a voltage drop in a non-volatile memory including a variable resistive element installed therein. A memory controller includes a voltage drop amount estimating unit and an encoding unit. The voltage drop amount estimating unit estimates a voltage drop ...More Less
4 US2020082881A1
STORAGE DEVICE AND CONTROL METHOD
Publication/Patent Number: US2020082881A1 Publication Date: 2020-03-12 Application Number: 16/466,388 Filing Date: 2017-11-09 Inventor: Terada, Haruhiko   Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION   IPC: G11C13/00 Abstract: A storage device according to the present disclosure includes: a first storage section that includes a plurality of first wiring lines, a plurality of second wiring lines, and a plurality of first memory cells, the plurality of first wiring lines extending in a first direction and including a plurality of first selection lines and a plurality of second selection lines, the plurality of second wiring lines extending in a second direction and including a plurality of third selection lines and a plurality of fourth selection lines; a first selection line driver that applies a first voltage to one or more selection lines of the plurality of first selection lines and applies a second voltage to one or more selection lines of the plurality of second selection lines, the first voltage being one of a first selection voltage and a second selection voltage, and the second voltage being one of the first selection voltage and the second selection voltage and being different from the first voltage; and a second selection line driver that applies a third voltage to one or more selection lines of the plurality of third selection lines and applies a fourth voltage to one or more selection lines of the plurality of fourth selection lines, the third voltage being one of the first selection voltage and the second selection voltage, and the fourth voltage being one of the first selection voltage and the second selection voltage and being different from the third voltage. A storage device according to the present disclosure includes: a first storage section that includes a plurality of first wiring lines, a plurality of second wiring lines, and a plurality of first memory cells, the plurality of first wiring lines extending in a first direction ...More Less
5 US10700130B2
Memory device and memory system
Publication/Patent Number: US10700130B2 Publication Date: 2020-06-30 Application Number: 16/402,838 Filing Date: 2019-05-03 Inventor: Terada, Haruhiko   Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION   IPC: H01L27/24 Abstract: Provided is a memory device that has a structure suitable for still higher integration while securing production easiness, and includes n memory cell units stacked, on a substrate, in order as first to n-th memory cell units in a first direction. The n memory cell units each include: one or more first electrodes; a plurality of second electrodes each provided to intersect the first electrode; a plurality of memory cells provided at respective intersections of the first electrode and the second electrodes and each coupled to both the first and second electrodes; and one or more lead lines coupled to the first electrode to form one or more coupling parts, which, in (m+1)-th memory cell unit, are located at a position where the coupling parts and m-th memory cell region surrounded by the memory cells in m-th memory cell unit overlap each other in the first direction. Provided is a memory device that has a structure suitable for still higher integration while securing production easiness, and includes n memory cell units stacked, on a substrate, in order as first to n-th memory cell units in a first direction. The n memory cell units each ...More Less
6 US10672472B2
Memory controller and memory system for suppression of fluctuation of voltage drop
Publication/Patent Number: US10672472B2 Publication Date: 2020-06-02 Application Number: 16/072,789 Filing Date: 2016-12-01 Inventor: Terada, Haruhiko   Assignee: Sony Corporation   IPC: G11C13/00 Abstract: Provided is an initialization control unit that causes a resistance value of a variable resistive element in an access restriction region to be changed to an initial value larger than a predetermined value. The resistance value is changed in a read only mode among the read only mode in which writing to the access restriction region is prohibited and a writable mode in which the writing to the access restriction region is permitted. The access restriction region is in a memory cell array in which the variable resistive elements are arranged, and the initialization control unit transitions to the writable mode. In addition, a write control unit causes a resistance value of an element corresponding to write data among the variable resistive elements in the access restriction region to be changed to a value smaller than the initial value in the writable mode, and transitions to the read only mode. Provided is an initialization control unit that causes a resistance value of a variable resistive element in an access restriction region to be changed to an initial value larger than a predetermined value. The resistance value is changed in a read only mode among the read only ...More Less
7 US2020098425A1
MEMORY APPARATUS AND METHOD OF CONTROLLING MEMORY APPARATUS
Publication/Patent Number: US2020098425A1 Publication Date: 2020-03-26 Application Number: 16/612,458 Filing Date: 2018-05-11 Inventor: Mori, Yotaro   Kitagawa, Makoto   Okuno, Jun   Terada, Haruhiko   Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION   IPC: G11C13/00 Abstract: A memory apparatus includes a memory cell disposed at an intersection of a first wiring line and a second wiring line, and including a variable resistor and a selector, the variable resistor having a resistance state that changes to a first resistance state and a second resistance state, and a drive circuit that writes data to the memory cell by changing the variable resistor from the first resistance state to the second resistance state, and erases the data stored in the memory cell by changing the variable resistor from the second resistance state to the first resistance state. When erasing the data, the drive circuit changing in a stepwise manner a voltage applied to the memory cell, and changing in a stepwise manner a current limit value that limits a magnitude of a current flowing through the memory cell. A memory apparatus includes a memory cell disposed at an intersection of a first wiring line and a second wiring line, and including a variable resistor and a selector, the variable resistor having a resistance state that changes to a first resistance state and a second ...More Less
8 US2020020411A1
STORAGE DEVICE
Publication/Patent Number: US2020020411A1 Publication Date: 2020-01-16 Application Number: 16/491,031 Filing Date: 2018-03-13 Inventor: Terada, Haruhiko   Kitagawa, Makoto   Shibahara, Yoshiyuki   Mori, Yotaro   Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION   IPC: G11C29/24 Abstract: A storage device according to the present disclosure includes: a plurality of first wiring lines extending in a first direction and including a plurality of first selection lines and a plurality of second selection lines; a plurality of second wiring lines extending in a second direction and including a plurality of third selection lines and a plurality of fourth selection lines, the second direction intersecting the first direction; a plurality of first memory cells; a first driver including a first selection line driver that drives the plurality of first selection lines on a basis of a first selection control signal and a second selection line driver that drives the plurality of second selection lines on a basis of the first selection control signal, the first and second selection line drivers being arranged side-by-side in the first direction; and a second driver including a third selection line driver that drives the plurality of third selection lines on a basis of a second selection control signal and a fourth selection line driver that drives the plurality of fourth selection lines on a basis of the second selection control signal, the third and fourth selection line drivers being arranged side-by-side in the second direction. A storage device according to the present disclosure includes: a plurality of first wiring lines extending in a first direction and including a plurality of first selection lines and a plurality of second selection lines; a plurality of second wiring lines extending in a second ...More Less
9 US2019035460A1
MEMORY CONTROLLER, MEMORY SYSTEM, AND MEMORY CONTROLLER CONTROL METHOD
Publication/Patent Number: US2019035460A1 Publication Date: 2019-01-31 Application Number: 16/072,789 Filing Date: 2016-12-01 Inventor: Terada, Haruhiko   Assignee: Sony Corporation   IPC: G11C13/00 Abstract: To suppress the fluctuation of the voltage drop in the non-volatile memories including the variable resistive element installed therein. An initialization control unit causes a resistance value of a variable resistive element in an access restriction region to be changed to an initial value larger than a predetermined value in a read only mode among the read only mode in which writing to the access restriction region in a memory cell array in which the variable resistive elements are arranged is prohibited and a writable mode in which the writing to the access restriction region is permitted, and transitions to the writable mode. In addition, a write control unit causes a resistance value of an element corresponding to write data among the variable resistive elements in the access restriction region to be changed to a value smaller than the initial value in the writable mode, and transitions to the read only mode. To suppress the fluctuation of the voltage drop in the non-volatile memories including the variable resistive element installed therein. An initialization control unit causes a resistance value of a variable resistive element in an access restriction region to be changed to an ...More Less
10 US2019034266A1
MEMORY CONTROLLER, NON-VOLATILE MEMORY, AND METHOD OF CONTROLLING MEMORY CONTROLLER
Publication/Patent Number: US2019034266A1 Publication Date: 2019-01-31 Application Number: 16/072,831 Filing Date: 2016-12-01 Inventor: Terada, Haruhiko   Assignee: Sony Corporation   IPC: G06F11/10 Abstract: To suppress an increase in a voltage drop in a non-volatile memory including a variable resistive element installed therein. A memory controller includes a voltage drop amount estimating unit and an encoding unit. The voltage drop amount estimating unit estimates a voltage drop amount from a wiring resistance of a wiring up to a memory cell and a leakage current occurring in the memory cell when original data is caused to be held in the memory cell. The encoding unit performs a predetermined encoding process on the original data in a case in which the estimated voltage drop amount exceeds a predetermined threshold value. To suppress an increase in a voltage drop in a non-volatile memory including a variable resistive element installed therein. A memory controller includes a voltage drop amount estimating unit and an encoding unit. The voltage drop amount estimating unit estimates a voltage drop ...More Less