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1
US10943823B2
Conductive feature formation and structure using bottom-up filling deposition
Publication/Patent Number: US10943823B2 Publication Date: 2021-03-09 Application Number: 16/654,845 Filing Date: 2019-10-16 Inventor: Chen, Pin-wen   Lai, Chia-han   Chang, Chih-wei   Fu, Mei-hui   Tsai ming hsing   Lin, Wei-jung   Wang, Yu Shih Shih   Cheng, Ya-yi   Chen, I-li   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L21/768 Abstract: The present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In some embodiments, a structure includes a first dielectric layer over a substrate, a first conductive feature through the first dielectric layer, the first conductive feature comprising a first metal, a second dielectric layer over the first dielectric layer, and a second conductive feature through the second dielectric layer having a lower convex surface extending into the first conductive feature, wherein the lower convex surface of the second conductive feature has a tip end extending laterally under a bottom boundary of the second dielectric layer.
2
KR20200006947A
CONTACT CONDUCTIVE FEATURE FORMATION AND STRUCTURE
Publication/Patent Number: KR20200006947A Publication Date: 2020-01-21 Application Number: 20190083797 Filing Date: 2019-07-11 Inventor: Tsai, Ming Hsing   Chang, Ken Yu   Tsai, Chun I   Lin, Wei Jung   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.   IPC: H01L21/768 Abstract: 일반적으로, 본 개시물은 금속 콘택트들, 비아들, 라인들 등과 같은 도전성 특징부들에 관련한 예시적인 실시형태들, 및 그들 도전성 특징부들을 형성하는 방법을 제공한다. 일 실시형태에서, 장벽층이 측벽을 따라 형성된다. 측벽을 따르는 장벽층의 부분이 습식 에칭 공정에 의해 에치 백된다. 장벽층의 부분을 에치 백한 후, 밑에 있는 유전체 웰딩층이 노출된다. 도전성 재료가 장벽층을 따라 형성된다.
3
KR102066251B1
Conductive Feature Formation and Structure
Publication/Patent Number: KR102066251B1 Publication Date: 2020-01-14 Application Number: 20180040491 Filing Date: 2018-04-06 Inventor: Wang, Yu Shih   Chang, Ken Yu   Tsai, Ming Hsing   Tsai, Chun I   Lin, Wei Jung   Mao, Shian Wei   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.   IPC: H01L21/768 Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, and the like, and methods for forming the conductive features. In an embodiment of the present disclosure, a barrier layer is formed along a sidewall. A part of the barrier layer along the sidewall is etched back. After etching back the part of the barrier layer, an upper part of the barrier layer along the sidewall is smoothed. A conductive material is formed over the smoothed upper part of the barrier layer and along the barrier layer.
4
US10580693B2
Contact conductive feature formation and structure
Publication/Patent Number: US10580693B2 Publication Date: 2020-03-03 Application Number: 16/032,416 Filing Date: 2018-07-11 Inventor: Chang, Ken-yu   Tsai, Chun-i   Tsai ming hsing   Lin, Wei-jung   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L23/52 Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back by a wet etching process. After etching back the portion of the barrier layer, an underlying dielectric welding layer is exposed. A conductive material is formed along the barrier layer.
5
US2020203222A1
Contact Conductive Feature Formation and Structure
Publication/Patent Number: US2020203222A1 Publication Date: 2020-06-25 Application Number: 16/806,931 Filing Date: 2020-03-02 Inventor: Chang, Ken-yu   Tsai, Chun-i   Tsai ming hsing   Lin, Wei-jung   Assignee: Taiwan Semiconductor Manfacturing Company, Ltd.   IPC: H01L21/768 Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back by a wet etching process. After etching back the portion of the barrier layer, an underlying dielectric welding layer is exposed. A conductive material is formed along the barrier layer.
6
US202020578A1
Contact Conductive Feature Formation and Structure
Publication/Patent Number: US202020578A1 Publication Date: 2020-01-16 Application Number: 20/181,603 Filing Date: 2018-07-11 Inventor: Tsai ming hsing   Chang, Ken-yu   Tsai, Chun-i   Lin, Wei-jung   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L21/8234 Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back by a wet etching process. After etching back the portion of the barrier layer, an underlying dielectric welding layer is exposed. A conductive material is formed along the barrier layer.
7
DE102019117005A1
Ausbildung und Struktur leitfähiger Kontaktmerkmale
Publication/Patent Number: DE102019117005A1 Publication Date: 2020-01-16 Application Number: 102019117005 Filing Date: 2019-06-25 Inventor: Lin, Wei-jung   Tsai ming hsing   Tsai, Chun-i   Chang, Ken-yu   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L29/78 Abstract: Allgemein stellt die vorliegende Offenbarung Ausführungsbeispiele, die leitfähige Merkmale, wie etwa metallische Kontakte, Durchkontaktierungen, Leitbahnen usw., betreffen, und Verfahren zum Ausbilden dieser leitfähigen Merkmale bereit. In einer Ausführungsform wird entlang einer Seitenwand eine Barriereschicht ausgebildet. Ein Abschnitt der Barriereschicht entlang der Seitenwand wird mittels eines Nassätzprozesses rückgeätzt. Nach dem Rückätzen des Abschnitts der Barriereschicht liegt eine darunterliegende dielektrische Schweißschicht frei. Entlang der Barriereschicht wird ein leitfähiges Material ausgebildet.
8
US2020020578A1
Contact Conductive Feature Formation and Structure
Publication/Patent Number: US2020020578A1 Publication Date: 2020-01-16 Application Number: 16/032,416 Filing Date: 2018-07-11 Inventor: Chang, Ken-yu   Tsai, Chun-i   Tsai ming hsing   Lin, Wei-jung   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L21/768 Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back by a wet etching process. After etching back the portion of the barrier layer, an underlying dielectric welding layer is exposed. A conductive material is formed along the barrier layer.
9
US2020388575A1
CHEMICAL DIRECT PATTERN PLATING METHOD
Publication/Patent Number: US2020388575A1 Publication Date: 2020-12-10 Application Number: 16/908,113 Filing Date: 2020-06-22 Inventor: Liu, Wen-jiun   Kao, Chen-yuan   Su, Hung-wen   Tsai ming hsing   Jang, Syun-ming   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L23/532 Abstract: A semiconductor structure with an improved metal structure is described. The semiconductor structure can include a substrate having an upper surface, an interconnect layer over the upper surface, and an additional structure deposited over the interconnect layer. The interconnect layer can include a patterned seed layer over the substrate, at least two metal lines over the seed layer, and a dielectric material between adjacent metal lines. A barrier layer can be deposited over the at least two metal lines. Methods of making the semiconductor structures are also described.
10
US10692814B2
Chemical direct pattern plating method
Publication/Patent Number: US10692814B2 Publication Date: 2020-06-23 Application Number: 15/401,470 Filing Date: 2017-01-09 Inventor: Liu, Wen-jiun   Kao, Chen-yuan   Su, Hung-wen   Tsai ming hsing   Jang, Syun-ming   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L23/532 Abstract: A semiconductor structure with an improved metal structure is described. The semiconductor structure can include a substrate having an upper surface, an interconnect layer over the upper surface, and an additional structure deposited over the interconnect layer. The interconnect layer can include a patterned seed layer over the substrate, at least two metal lines over the seed layer, and a dielectric material between adjacent metal lines. A barrier layer can be deposited over the at least two metal lines. Methods of making the semiconductor structures are also described.
11
US2020343135A1
Phase Control in Contact Formation
Publication/Patent Number: US2020343135A1 Publication Date: 2020-10-29 Application Number: 16/392,067 Filing Date: 2019-04-23 Inventor: Huang, Chun-hsien   Chen, I-li   Chen, Pin-wen   Hsu, Yuan-chen   Lin, Wei-jung   Chang, Chih-wei   Tsai ming hsing   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L21/768 Abstract: A method includes forming a first metallic feature, forming a dielectric layer over the first metallic feature, etching the dielectric layer to form an opening, with a top surface of the first metallic feature being exposed through the opening, and performing a first treatment on the top surface of the first metallic feature. The first treatment is performed through the opening, and the first treatment is performed using a first process gas. After the first treatment, a second treatment is performed through the opening, and the second treatment is performed using a second process gas different from the first process gas. A second metallic feature is deposited in the opening.
12
US10867845B2
Semiconductor device and method
Publication/Patent Number: US10867845B2 Publication Date: 2020-12-15 Application Number: 16/599,940 Filing Date: 2019-10-11 Inventor: Wang, Yu-sheng   Hung, Chi-cheng   Su, Ching-hwanq   Ou, Yang Liang-yueh   Tsai ming hsing   Lin, Yu-ting   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L21/768 Abstract: A method includes forming a first opening in a dielectric layer over a substrate, lining sidewalls and a bottom of the first opening with a conductive barrier layer, and depositing a seed layer over the conductive barrier layer. The method further includes treating the seed layer with a plasma process, and filling the first opening with a conductive material after the treating the seed layer.
13
US202043781A1
Semiconductor Device and Method
Publication/Patent Number: US202043781A1 Publication Date: 2020-02-06 Application Number: 20/191,659 Filing Date: 2019-10-11 Inventor: Tsai ming hsing   Wang, Yu-sheng   Hung, Chi-cheng   Su, Ching-hwanq   Lin, Yu-ting   Ou, Yang Liang-yueh   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L29/66 Abstract: A method includes forming a first opening in a dielectric layer over a substrate, lining sidewalls and a bottom of the first opening with a conductive barrier layer, and depositing a seed layer over the conductive barrier layer. The method further includes treating the seed layer with a plasma process, and filling the first opening with a conductive material after the treating the seed layer.
14
US2020043781A1
Semiconductor Device and Method
Publication/Patent Number: US2020043781A1 Publication Date: 2020-02-06 Application Number: 16/599,940 Filing Date: 2019-10-11 Inventor: Wang, Yu-sheng   Hung, Chi-cheng   Su, Ching-hwanq   Ou, Yang Liang-yueh   Tsai ming hsing   Lin, Yu-ting   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L21/768 Abstract: A method includes forming a first opening in a dielectric layer over a substrate, lining sidewalls and a bottom of the first opening with a conductive barrier layer, and depositing a seed layer over the conductive barrier layer. The method further includes treating the seed layer with a plasma process, and filling the first opening with a conductive material after the treating the seed layer.
15
US2020152763A1
Method of Forming a Contact with a Silicide Region
Publication/Patent Number: US2020152763A1 Publication Date: 2020-05-14 Application Number: 16/740,881 Filing Date: 2020-01-13 Inventor: Cheng, Yu-wen   Lin, Cheng-tung   Chang, Chih-wei   Lee, Hong-mao   Tsai ming hsing   Lin, Sheng-hsuan   Lin, Wei-jung   Tsai, Yan-ming   Wang, Yu-shiuan   Chen, Hung-hsu   Loh, Wei-yip   Cheng, Ya-yi   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L29/66 Abstract: Embodiments disclosed herein relate generally to forming an effective metal diffusion barrier in sidewalls of epitaxy source/drain regions. In an embodiment, a structure includes an active area having a source/drain region on a substrate, a dielectric layer over the active area and having a sidewall aligned with the sidewall of the source/drain region, and a conductive feature along the sidewall of the dielectric layer to the source/drain region. The source/drain region has a sidewall and a lateral surface extending laterally from the sidewall of the source/drain region, and the source/drain region further includes a nitrided region extending laterally from the sidewall of the source/drain region into the source/drain region. The conductive feature includes a silicide region along the lateral surface of the source/drain region and along at least a portion of the sidewall of the source/drain region.
16
US10535748B2
Method of forming a contact with a silicide region
Publication/Patent Number: US10535748B2 Publication Date: 2020-01-14 Application Number: 15/909,838 Filing Date: 2018-03-01 Inventor: Cheng, Yu-wen   Lin, Cheng-tung   Chang, Chih-wei   Lee, Hong-mao   Tsai ming hsing   Lin, Sheng-hsuan   Lin, Wei-jung   Tsai, Yan-ming   Wang, Yu-shiuan   Chen, Hung-hsu   Loh, Wei-yip   Cheng, Ya-yi   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L29/66 Abstract: Embodiments disclosed herein relate generally to forming an effective metal diffusion barrier in sidewalls of epitaxy source/drain regions. In an embodiment, a structure includes an active area having a source/drain region on a substrate, a dielectric layer over the active area and having a sidewall aligned with the sidewall of the source/drain region, and a conductive feature along the sidewall of the dielectric layer to the source/drain region. The source/drain region has a sidewall and a lateral surface extending laterally from the sidewall of the source/drain region, and the source/drain region further includes a nitrided region extending laterally from the sidewall of the source/drain region into the source/drain region. The conductive feature includes a silicide region along the lateral surface of the source/drain region and along at least a portion of the sidewall of the source/drain region.
17
US2020111739A1
METHOD FOR FORMING SEMICONDUCTOR CONTACT STRUCTURE
Publication/Patent Number: US2020111739A1 Publication Date: 2020-04-09 Application Number: 16/707,301 Filing Date: 2019-12-09 Inventor: Cheng, Yu-wen   Loh, Wei-yip   Liao, Yu-hsiang   Lin, Sheng-hsuan   Lee, Hong-mao   Tsai, Chun-i   Chang, Ken-yu   Lin, Wei-jung   Chang, Chih-wei   Tsai ming hsing   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.   IPC: H01L23/522 Abstract: A method for forming a semiconductor contact structure is provided. The method includes depositing a dielectric layer over a substrate. The method also includes etching the dielectric layer to expose a sidewall of the dielectric layer and a top surface of the substrate. In addition, the method includes forming a silicide region in the substrate. The method also includes applying a plasma treatment to the sidewall of the dielectric layer and the top surface of the substrate to form a nitridation region adjacent to a periphery of the silicide region. The method further includes depositing an adhesion layer on the dielectric layer and the silicide region.
18
US202051858A1
Conductive Feature Formation and Structure Using Bottom-Up Filling Deposition
Publication/Patent Number: US202051858A1 Publication Date: 2020-02-13 Application Number: 20/191,665 Filing Date: 2019-10-16 Inventor: Tsai ming hsing   Chang, Chih-wei   Lai, Chia-han   Lin, Wei-jung   Chen, Pin-wen   Fu, Mei-hui   Cheng, Ya-yi   Wang, Yu Shih Shih   Chen, I-li   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L21/768 Abstract: The present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In some embodiments, a structure includes a first dielectric layer over a substrate, a first conductive feature through the first dielectric layer, the first conductive feature comprising a first metal, a second dielectric layer over the first dielectric layer, and a second conductive feature through the second dielectric layer having a lower convex surface extending into the first conductive feature, wherein the lower convex surface of the second conductive feature has a tip end extending laterally under a bottom boundary of the second dielectric layer.
19
US2020051858A1
Conductive Feature Formation and Structure Using Bottom-Up Filling Deposition
Publication/Patent Number: US2020051858A1 Publication Date: 2020-02-13 Application Number: 16/654,845 Filing Date: 2019-10-16 Inventor: Chen, Pin-wen   Lai, Chia-han   Chang, Chih-wei   Fu, Mei-hui   Tsai ming hsing   Lin, Wei-jung   Wang, Yu Shih Shih   Cheng, Ya-yi   Chen, I-li   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L21/768 Abstract: The present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In some embodiments, a structure includes a first dielectric layer over a substrate, a first conductive feature through the first dielectric layer, the first conductive feature comprising a first metal, a second dielectric layer over the first dielectric layer, and a second conductive feature through the second dielectric layer having a lower convex surface extending into the first conductive feature, wherein the lower convex surface of the second conductive feature has a tip end extending laterally under a bottom boundary of the second dielectric layer.
20
US202020583A1
FORMATION METHOD OF SEMICONDUCTOR DEVICE STRUCTURE WITH METAL-SEMICONDUCTOR COMPOUND REGION
Publication/Patent Number: US202020583A1 Publication Date: 2020-01-16 Application Number: 20/181,603 Filing Date: 2018-07-13 Inventor: Chang, Chih-wei   Tsai ming hsing   Su, Ching-hwanq   Chu, Li-wei   Chao, Yi-hsiang   Hung, Min-hsiu   Li, Ya-huei   Liao, Yu-hsiang   Huang, Hung-yi   Yeh, Kuan-yu   Lin, Kan-ju   Chuang, Chi-hung   Nieh, Chun-wen   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L29/78 Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a fin structure over a semiconductor substrate and forming a gate stack over the fin structure. The method also includes forming an epitaxial structure over the fin structure, and the epitaxial structure is adjacent to the gate stack. The method further includes forming a dielectric layer over the epitaxial structure and forming an opening in the dielectric layer to expose the epitaxial structure. In addition, the method includes applying a metal-containing material on the epitaxial structure while the epitaxial structure is heated so that a portion of the epitaxial structure is transformed to form a metal-semiconductor compound region.
Total 15 pages