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No. Publication Number Title Publication/Patent Number Publication/Patent Number Publication Date Publication Date
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Inventor Inventor Assignee Assignee IPC IPC
1 US10545804B2
Memory controller, memory system, and memory controller control method
Publication/Patent Number: US10545804B2 Publication Date: 2020-01-28 Application Number: 15/507,413 Filing Date: 2015-07-22 Inventor: Shinbashi, Tatsuo   Tsutsui, Keiichi   Okubo, Hideaki   Sakai, Lui   Nakanishi, Kenichi   Fujinami, Yasushi   Assignee: Sony Corporation   IPC: G06F11/00 Abstract: [Object] To sufficiently reduce frequency of error occurrence in memory cells. [Solution] A reading unit reads read data from a memory cell, the read data including an information bit and reversal information for determining whether or not the information bit has been reversed. In addition, an error detection/correction unit detects the presence or absence of an error in the information bit and corrects the error. A data reversing unit reverses the information bit that has the error corrected and the reversal information. Furthermore, a writing unit writes the reversed information bit and the reversed reversal information in the memory cell. [Object] To sufficiently reduce frequency of error occurrence in memory cells. [Solution] A reading unit reads read data from a memory cell, the read data including an information bit and reversal information for determining whether or not the information bit has been reversed ...More ...Less
2 EP3211536B1
MEMORY CONTROLLER, MEMORY SYSTEM, AND MEMORY CONTROLLER CONTROL METHOD
Publication/Patent Number: EP3211536B1 Publication Date: 2019-09-04 Application Number: 15851846.4 Filing Date: 2015-07-22 Inventor: Shinbashi, Tatsuo   Tsutsui, Keiichi   Okubo, Hideaki   Sakai, Lui   Nakanishi, Kenichi   Fujinami, Yasushi   Assignee: Sony Corporation   IPC: G06F12/16
3 US9886399B2
Storage control device, storage device, information processing system, and storage control method therefor
Publication/Patent Number: US9886399B2 Publication Date: 2018-02-06 Application Number: 14/528,586 Filing Date: 2014-10-30 Inventor: Ikegaya, Ryoji   Tsutsui, Keiichi   Ishii, Ken   Assignee: Sony Corporation   IPC: G06F11/10 Abstract: Data are stored using a writing method according to the property of the data in a storage device. An area defining unit defines, in a second memory, a system area for storing system information causing a system to operate and a cache area temporarily storing data of a first memory. A moving processing unit moves data stored in the cache area to the first memory at a predetermined point in time. An access control unit accesses the second memory in accordance with the definition with regard to access corresponding to the system area or the cache area, and read data from the first memory with regard to read-access corresponding to those other than the system area and the cache area. Data are stored using a writing method according to the property of the data in a storage device. An area defining unit defines, in a second memory, a system area for storing system information causing a system to operate and a cache area temporarily storing data of a first ...More ...Less
4 US10031865B2
Memory system, storage device, and method for controlling memory system
Publication/Patent Number: US10031865B2 Publication Date: 2018-07-24 Application Number: 15/527,374 Filing Date: 2015-10-08 Inventor: Tsutsui, Keiichi   Okubo, Hideaki   Sakai, Lui   Terada, Haruhiko   Assignee: SONY CORPORATION   IPC: G06F11/14 Abstract: To suppress the degradation of memory cells in a non-volatile memory. A read processing unit performs a read process for reading read data from each of a plurality of memory cells on the basis of a first threshold. An error detection unit detects presence or absence of an error in the read data and specifies memory cells in which the error is present among the plurality of memory cells. A re-read processing unit performs a re-read process for reading data, as re-read data, from the specified memory cells on the basis of a second threshold different from the first threshold. A refresh processing unit rewrites, for a memory cell of which the re-read data has a different value from the read data among the specified memory cells, data with the re-read data as a refresh process. To suppress the degradation of memory cells in a non-volatile memory. A read processing unit performs a read process for reading read data from each of a plurality of memory cells on the basis of a first threshold. An error detection unit detects presence or absence of an error ...More ...Less
5 EP2800097B1
STORAGE CONTROL DEVICE, STORAGE DEVICE, INFORMATION PROCESSING SYSTEM, AND PROCESSING METHODS THEREFOR
Publication/Patent Number: EP2800097B1 Publication Date: 2018-03-21 Application Number: 12865338.3 Filing Date: 2012-12-20 Inventor: Adachi, Naohiro   Tsutsui, Keiichi   Nakanishi, Kenichi   Okubo, Hideaki   Yamamoto, Makiko   Fujinami, Yasushi   Assignee: Sony Corporation   IPC: G11C13/00 Abstract: Provided is a storage control device including a first read processing unit configured to read data having any one value of a first value or a second value based on a first threshold value in a memory cell, the data being read as first read data, a first write processing unit configured to rewrite the memory cell to the first value when write data is the first value and the first read data is the second value, a second read processing unit configured to read second read data based on a second threshold value different from the first threshold value in the memory cell, and a second write processing unit configured to rewrite the memory cell to the second value when the write data is the second value and the second read data is the first value. Provided is a storage control device including a first read processing unit configured to read data having any one value of a first value or a second value based on a first threshold value in a memory cell, the data being read as first read data, a first write processing unit ...More ...Less
6 US9817712B2
Storage control apparatus, storage apparatus, information processing system, and storage control method
Publication/Patent Number: US9817712B2 Publication Date: 2017-11-14 Application Number: 13/655,130 Filing Date: 2012-10-18 Inventor: Nakanishi, Kenichi   Tsutsui, Keiichi   Assignee: Sony Corporation   IPC: H03M13/00 Abstract: A storage control apparatus including a first error detection block and a second error detection block is provided. The first error detection block is configured to execute error detection in accordance with a first data unit read from a memory and a first error detection code corresponding to the first data unit. The second error detection block is configured, if a second error detection code corresponding to a second data unit smaller than the first data unit is held in an error detection code hold block different from the memory, to execute error detection in accordance with the second data unit read from the memory and the second error detection code held in the error detection code hold block. A storage control apparatus including a first error detection block and a second error detection block is provided. The first error detection block is configured to execute error detection in accordance with a first data unit read from a memory and a first error detection code ...More ...Less
7 US9836312B2
Storage control device, storage device, and storage control method thereof
Publication/Patent Number: US9836312B2 Publication Date: 2017-12-05 Application Number: 14/310,205 Filing Date: 2014-06-20 Inventor: Terada, Haruhiko   Tsutsui, Keiichi   Assignee: Sony Corporation   IPC: G06F9/44 Abstract: A storage control device includes: a detection unit that determines whether a preliminary process of saving data from a first memory to a second memory is necessary, where the second memory includes a suspend area and a typical area; a preliminary processing unit that writes a first value to the suspend area when the detection unit has determined that the preliminary process is necessary; and a saving processing unit that writes a second value corresponding to the data. The first value is different from the second value when the detection unit has determined that the preliminary process is necessary. A storage control device includes: a detection unit that determines whether a preliminary process of saving data from a first memory to a second memory is necessary, where the second memory includes a suspend area and a typical area; a preliminary processing unit that writes a ...More ...Less