| No. | Publication Number | Title | Publication/Patent Number Publication/Patent Number |
Publication Date
Publication Date
|
Application Number Application Number |
Filing Date
Filing Date
|
Inventor Inventor | Assignee Assignee |
IPC
IPC
|
|||||
|
1 | US10566374B2 |
Via support structure under pad areas for BSI bondability improvement
|
Publication/Patent Number: US10566374B2 | Publication Date: 2020-02-18 | Application Number: 16/167,844 | Filing Date: 2018-10-23 | Inventor： Huang, Sin-yao Wang ching chun Yaung, Dun-nian Hung, Feng-chi | Assignee: Taiwan Semiconductor Manufacturing Co., Ltd. | IPC: H01L27/146 | Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a substrate and a first interconnect wire arranged within a dielectric structure on the substrate. A bond pad contacts the first interconnect wire. A via support structure has one or more vias arranged within the dielectric structure at a location separated from the substrate by the first interconnect wire, The via support structure has a metal pattern density that is greater than or equal to approximately 19% and that is configured to mitigate damage caused by a force of a bonding process on the bond pad. | |||
|
|
2 | US2020135794A1 |
VIA SUPPORT STRUCTURE UNDER PAD AREAS FOR BSI BONDABILITY IMPROVEMENT
|
Publication/Patent Number: US2020135794A1 | Publication Date: 2020-04-30 | Application Number: 16/732,646 | Filing Date: 2020-01-02 | Inventor： Huang, Sin-yao Wang ching chun Yaung, Dun-nian Hung, Feng-chi | Assignee: Taiwan Semiconductor Manufacturing Co., Ltd. | IPC: H01L27/146 | Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first interconnect wire disposed within a dielectric structure on a substrate. A bond pad has a lower surface contacting the first interconnect wire. A via layer is vertically between the first interconnect wire and a second interconnect wire within the dielectric structure. The via layer includes a plurality of support vias having a first size and a plurality of additional vias having a second size that is smaller than the first size. The plurality of support vias extend from directly under the lower surface of the bond pad to laterally past outermost edges of the lower surface of the bond pad. | |||
|
|
3 | US2020013736A1 |
SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME
|
Publication/Patent Number: US2020013736A1 | Publication Date: 2020-01-09 | Application Number: 16/574,185 | Filing Date: 2019-09-18 | Inventor： Yang, Ming-hsien Wang ching chun Yaung, Dun-nian Hung, Feng-chi Huang, Sin-yao | Assignee: Taiwan Semiconductor Manufacturing Co., Ltd. | IPC: H01L23/00 | Abstract: A semiconductor device structure is provided, in some embodiments. The semiconductor device structure includes a semiconductor substrate having a first surface, a second surface, and sidewalls defining a recess that passes through the semiconductor substrate. The semiconductor device structure further includes an interconnect structure having one or more interconnect layers within a first dielectric structure that is disposed along the second surface. A conductive bonding structure is disposed within the recess and includes nickel. The conductive bonding structure has opposing outermost sidewalls that contact sidewalls of the interconnect structure. | |||
|
4 | US202013736A1 |
SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME
|
Publication/Patent Number: US202013736A1 | Publication Date: 2020-01-09 | Application Number: 20/191,657 | Filing Date: 2019-09-18 | Inventor： Yaung, Dun-nian Wang ching chun Hung, Feng-chi Huang, Sin-yao Yang, Ming-hsien | Assignee: Taiwan Semiconductor Manufacturing Co., Ltd. | IPC: H01L27/146 | Abstract: A semiconductor device structure is provided, in some embodiments. The semiconductor device structure includes a semiconductor substrate having a first surface, a second surface, and sidewalls defining a recess that passes through the semiconductor substrate. The semiconductor device structure further includes an interconnect structure having one or more interconnect layers within a first dielectric structure that is disposed along the second surface. A conductive bonding structure is disposed within the recess and includes nickel. The conductive bonding structure has opposing outermost sidewalls that contact sidewalls of the interconnect structure. | |||
|
|
5 | US2020127042A1 |
Apparatus for Reducing Optical Cross-Talk in Image Sensors
|
Publication/Patent Number: US2020127042A1 | Publication Date: 2020-04-23 | Application Number: 16/721,288 | Filing Date: 2019-12-19 | Inventor： Lin, Chin-min Wang ching chun Yaung, Dun-nian Su, Chun-ming Hsu, Tzu-hsuan | Assignee: Taiwan Semiconductor Manufacturing Company, Ltd. | IPC: H01L27/146 | Abstract: According to one example, a device includes a semiconductor substrate. The device further includes a plurality of color filters disposed above the semiconductor substrate. The device further includes a plurality of micro-lenses disposed above the set of color filters. The device further includes a structure that is configured to block light radiation that is traveling towards a region between adjacent micro-lenses. The structure and the color filters are level at respective top surfaces and bottom surfaces thereof. | |||
|
|
6 | US10868050B2 |
Backside illuminated image sensor with negatively charged layer
|
Publication/Patent Number: US10868050B2 | Publication Date: 2020-12-15 | Application Number: 15/590,264 | Filing Date: 2017-05-09 | Inventor： Ting, Shyh-fann Lai, Chih-yu Wu, Cheng-ta Tu, Yeur-luen Wang ching chun | Assignee: Taiwan Semiconductor Manufacturing Co., Ltd. | IPC: H01L27/146 | Abstract: The present disclosure relates to a semiconductor image sensor device. In some embodiments, the semiconductor image sensor device includes a semiconductor substrate having a first surface configured to receive incident radiation. A plurality of sensor elements are arranged within the semiconductor substrate. A first charged layer is arranged on an entirety of a second surface of the semiconductor substrate facing an opposite direction as the first surface. The second surface is between the first charged layer and the first surface of the semiconductor substrate. | |||
|
|
7 | US10833119B2 |
Pad structure for front side illuminated image sensor
|
Publication/Patent Number: US10833119B2 | Publication Date: 2020-11-10 | Application Number: 15/149,561 | Filing Date: 2016-05-09 | Inventor： Hsu, Kai-chun Wang ching chun Yaung, Dun-nian Lin, Jeng-shyan Ting, Shyh-fann | Assignee: Taiwan Semiconductor Manufacturing Co., Ltd. | IPC: H01L27/146 | Abstract: The present disclosure relates to an integrated circuit having a bond pad with a relatively flat surface topography that mitigates damage to underlying layers. In some embodiments, the integrated circuit has a plurality of metal interconnect layers within a dielectric structure over a substrate. A passivation structure is arranged over the dielectric structure. The passivation structure has a recess with sidewalls connecting a horizontal surface of the passivation structure to an upper surface of the passivation structure. A bond pad is arranged within the recess and has a lower surface overlying the horizontal surface. One or more protrusions extend outward from the lower surface through openings in the passivation structure to contact one of the metal interconnect layers. Arranging the bond pad within the recess and over the passivation structure mitigates stress to underlying layers during bonding without negatively impacting an efficiency of an image sensing element within the substrate. | |||
|
|
8 | US10811398B2 |
Semiconductor structure and method for manufacturing the same
|
Publication/Patent Number: US10811398B2 | Publication Date: 2020-10-20 | Application Number: 16/214,665 | Filing Date: 2018-12-10 | Inventor： Kao, Min-feng Yaung, Dun-nian Liu, Jen-cheng Lin, Hsing-chih Wang ching chun | Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. | IPC: H01L21/768 | Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a semiconductor substrate including a front surface and a back surface; a backside metallization layer formed over the semiconductor substrate, the backside metallization layer being closer to the back surface than to the front surface of the semiconductor substrate, at least a portion of the backside metallization layer forming an inductor structure; and an electrically non-conductive material formed in the semiconductor substrate, the electrically non-conductive material at least partially overlapping the inductor structure from a top view, and the electrically non-conductive material including a top surface, a bottom surface, and sidewalls, the top surface being adjacent to the back surface of the semiconductor substrate. A method for manufacturing a semiconductor structure is also disclosed. | |||
|
|
9 | US10790194B2 |
Inductor structure for integrated circuit
|
Publication/Patent Number: US10790194B2 | Publication Date: 2020-09-29 | Application Number: 16/584,809 | Filing Date: 2019-09-26 | Inventor： Huang, Shih-han Wang ching chun Yaung, Dun-nian Lin, Hsing-chih Liu, Jen-cheng Kao, Min-feng | Assignee: Taiwan Semiconductor Manufacturing Co., Ltd. | IPC: H01L21/822 | Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first plurality of conductive interconnect layers arranged within a first inter-level dielectric (ILD) structure disposed on a first surface of a first substrate. A second plurality of conductive interconnect layers are arranged within a second ILD structure disposed on a first surface of a second substrate. The second substrate is separated from the first substrate by the first ILD structure. The first plurality of conductive interconnect layers and the second plurality of conductive interconnect layers define an inductor having one or more turns. | |||
|
|
10 | US10804155B2 |
Inductor structure for integrated circuit
|
Publication/Patent Number: US10804155B2 | Publication Date: 2020-10-13 | Application Number: 16/584,824 | Filing Date: 2019-09-26 | Inventor： Huang, Shih-han Wang ching chun Yaung, Dun-nian Lin, Hsing-chih Liu, Jen-cheng Kao, Min-feng | Assignee: Taiwan Semiconductor Manufacturing Co., Ltd. | IPC: H01L21/822 | Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a first conductive wire within a first dielectric structure formed on a first surface of a first substrate. A through-substrate-via (TSV) is formed to extend though the first substrate. A second conductive wire is formed within a second dielectric structure formed on a second surface of the first substrate opposing the first surface. The TSV electrically couples the first conductive wire and the second conductive wire. The first conductive wire, the second conductive wire, and the TSV define an inductor that wraps around an axis. | |||
|
|
11 | US10727164B2 |
Semiconductor structure and manufacturing method for the same
|
Publication/Patent Number: US10727164B2 | Publication Date: 2020-07-28 | Application Number: 16/228,585 | Filing Date: 2018-12-20 | Inventor： Kao, Min-feng Yaung, Dun-nian Liu, Jen-cheng Wang ching chun Huang, Kuan-chieh Lin, Hsing-chih Chu, Yi-shin | Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. | IPC: H01L23/52 | Abstract: Present disclosure provides a semiconductor structure, including a semiconductor substrate having an active side, an interconnect layer in proximity to the active side of the semiconductor substrate, and a through substrate via extending from the semiconductor substrate to a first metal layer of the interconnect layer. The TSV being wider than the continuous metal feature. Present disclosure also provides a method for manufacturing the semiconductor structure described herein. | |||
|
|
12 | US2020027789A1 |
INDUCTOR STRUCTURE FOR INTEGRATED CIRCUIT
|
Publication/Patent Number: US2020027789A1 | Publication Date: 2020-01-23 | Application Number: 16/584,809 | Filing Date: 2019-09-26 | Inventor： Huang, Shih-han Wang ching chun Yaung, Dun-nian Lin, Hsing-chih Liu, Jen-cheng Kao, Min-feng | Assignee: Taiwan Semiconductor Manufacturing Co., Ltd. | IPC: H01L21/822 | Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first plurality of conductive interconnect layers arranged within a first inter-level dielectric (ILD) structure disposed on a first surface of a first substrate. A second plurality of conductive interconnect layers are arranged within a second ILD structure disposed on a first surface of a second substrate. The second substrate is separated from the first substrate by the first ILD structure. The first plurality of conductive interconnect layers and the second plurality of conductive interconnect layers define an inductor having one or more turns. | |||
|
|
13 | US2020243580A1 |
MANUFACTURING METHOD OF IMAGE SENSING DEVICE
|
Publication/Patent Number: US2020243580A1 | Publication Date: 2020-07-30 | Application Number: 16/842,909 | Filing Date: 2020-04-08 | Inventor： Wu, Wei-chuang Wang, Ming-tsong Hung, Feng-chi Wang ching chun Liu, Jen-cheng Yaung, Dun-nian | Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. | IPC: H01L27/146 | Abstract: A method for manufacturing an image sensing device includes forming an interconnection layer over a front surface of a semiconductor substrate. A trench is formed to extend from a back surface of the semiconductor substrate. An etch stop layer is formed along the trench. A buffer layer is formed over the etch stop layer. An etch process is performed for etching the buffer layer. The buffer layer and the etch stop layer include different materials. | |||
|
|
14 | US202027789A1 |
INDUCTOR STRUCTURE FOR INTEGRATED CIRCUIT
|
Publication/Patent Number: US202027789A1 | Publication Date: 2020-01-23 | Application Number: 20/191,658 | Filing Date: 2019-09-26 | Inventor： Yaung, Dun-nian Wang ching chun Liu, Jen-cheng Kao, Min-feng Lin, Hsing-chih Huang, Shih-han | Assignee: Taiwan Semiconductor Manufacturing Co., Ltd. | IPC: H01L49/02 | Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first plurality of conductive interconnect layers arranged within a first inter-level dielectric (ILD) structure disposed on a first surface of a first substrate. A second plurality of conductive interconnect layers are arranged within a second ILD structure disposed on a first surface of a second substrate. The second substrate is separated from the first substrate by the first ILD structure. The first plurality of conductive interconnect layers and the second plurality of conductive interconnect layers define an inductor having one or more turns. | |||
|
|
15 | US2020152675A1 |
BOND PAD STRUCTURE FOR BONDING IMPROVEMENT
|
Publication/Patent Number: US2020152675A1 | Publication Date: 2020-05-14 | Application Number: 16/705,376 | Filing Date: 2019-12-06 | Inventor： Huang, Sin-yao Wang ching chun Yaung, Dun-nian Hung, Feng-chi Wang, Ming-tsong Chou, Shih Pei | Assignee: Taiwan Semiconductor Manufacturing Co., Ltd. | IPC: H01L27/146 | Abstract: Some embodiments relate an integrated circuit (IC). The IC includes a first substrate including an array of photodetectors, wherein a bond pad opening extends through the first substrate and is defined by an inner sidewall of the first substrate. An interconnect structure is disposed over the first substrate and includes a plurality of metal layers stacked over one another and disposed within a dielectric structure. The bond pad opening further extends through at least a portion of the interconnect structure and is further defined by an inner sidewall of the interconnect structure. A bond pad structure directly contacts a metal layer of the plurality of metal layers in the interconnect structure and is located at an uppermost extent of the bond pad opening. | |||
|
|
16 | US202027790A1 |
INDUCTOR STRUCTURE FOR INTEGRATED CIRCUIT
|
Publication/Patent Number: US202027790A1 | Publication Date: 2020-01-23 | Application Number: 20/191,658 | Filing Date: 2019-09-26 | Inventor： Yaung, Dun-nian Wang ching chun Liu, Jen-cheng Kao, Min-feng Lin, Hsing-chih Huang, Shih-han | Assignee: Taiwan Semiconductor Manufacturing Co., Ltd. | IPC: H01L49/02 | Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a first conductive wire within a first dielectric structure formed on a first surface of a first substrate. A through-substrate-via (TSV) is formed to extend though the first substrate. A second conductive wire is formed within a second dielectric structure formed on a second surface of the first substrate opposing the first surface. The TSV electrically couples the first conductive wire and the second conductive wire. The first conductive wire, the second conductive wire, and the TSV define an inductor that wraps around an axis. | |||
|
|
17 | US10622394B2 |
Image sensing device
|
Publication/Patent Number: US10622394B2 | Publication Date: 2020-04-14 | Application Number: 15/591,244 | Filing Date: 2017-05-10 | Inventor： Wu, Wei-chuang Wang, Ming-tsong Hung, Feng-chi Wang ching chun Liu, Jen-cheng Yaung, Dun-nian | Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. | IPC: H01L27/146 | Abstract: The image sensing device includes a semiconductor substrate, an interconnection layer, a radiation-sensing region and an isolation structure. The semiconductor substrate has a front surface and a back surface. The interconnection layer is disposed over the front surface of the semiconductor substrate. The radiation-sensing region is disposed in the semiconductor substrate. The isolation structure is disposed on the back surface of the semiconductor substrate. The isolation structure includes a trench and an etch stop layer. The trench extends from the back surface of the semiconductor substrate. The etch stop layer is disposed along the trench. An etch selectivity of a silicon oxide film to the etch stop layer is greater than a predetermined value. | |||
|
|
18 | US2020027790A1 |
INDUCTOR STRUCTURE FOR INTEGRATED CIRCUIT
|
Publication/Patent Number: US2020027790A1 | Publication Date: 2020-01-23 | Application Number: 16/584,824 | Filing Date: 2019-09-26 | Inventor： Huang, Shih-han Wang ching chun Yaung, Dun-nian Lin, Hsing-chih Liu, Jen-cheng Kao, Min-feng | Assignee: Taiwan Semiconductor Manufacturing Co., Ltd. | IPC: H01L21/822 | Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a first conductive wire within a first dielectric structure formed on a first surface of a first substrate. A through-substrate-via (TSV) is formed to extend though the first substrate. A second conductive wire is formed within a second dielectric structure formed on a second surface of the first substrate opposing the first surface. The TSV electrically couples the first conductive wire and the second conductive wire. The first conductive wire, the second conductive wire, and the TSV define an inductor that wraps around an axis. | |||
|
|
19 | US2020335427A1 |
SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD FOR THE SAME
|
Publication/Patent Number: US2020335427A1 | Publication Date: 2020-10-22 | Application Number: 16/920,430 | Filing Date: 2020-07-03 | Inventor： Kao, Min-feng Yaung, Dun-nian Liu, Jen-cheng Wang ching chun Huang, Kuan-chieh Lin, Hsing-chih Chu, Yi-shin | Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. | IPC: H01L23/48 | Abstract: Present disclosure provides a semiconductor structure, including a semiconductor substrate, a first metal layer, and a through substrate via (TSV). The semiconductor substrate has an active side. The first metal layer is closest to the active side of the semiconductor substrate, and the first metal layer has a first continuous metal feature. The TSV is extending from the semiconductor substrate to the first continuous metal feature. A width of the TSV at the first metal layer is wider than a width of the first continuous metal feature. Present disclosure also provides a method for manufacturing the semiconductor structure described herein. | |||
|
|
20 | US2020058686A1 |
MULTIPLE DEEP TRENCH ISOLATION (MDTI) STRUCTURE FOR CMOS IMAGE SENSOR
|
Publication/Patent Number: US2020058686A1 | Publication Date: 2020-02-20 | Application Number: 16/661,166 | Filing Date: 2019-10-23 | Inventor： Wu, Wei Chuang Wang ching chun Yaung, Dun-nian Hung, Feng-chi Liu, Jen-cheng Chiang, Yen-ting Chen, Chun-yuan Hong, Shen-hui | Assignee: Taiwan Semiconductor Manufacturing Co., Ltd. | IPC: H01L27/146 | Abstract: The present disclosure relates to a CMOS image sensor having a multiple deep trench isolation (MDTI) structure, and an associated method of formation. In some embodiments, a plurality of photodiodes is formed from a front-side of a substrate. A plurality of boundary deep trench isolation (BDTI) trenches having a first depth and a plurality of multiple deep trench isolation (MDTI) trenches having a second depth are formed from a back-side of the substrate. A stack of dielectric layers is formed in the BDTI trenches and the MDTI trenches. A plurality of color filters is formed overlying the stack of dielectric layers corresponding to the plurality of photodiodes. |
3.Current Quota