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1
US10955517B2
Underwater ultrasonic device
Publication/Patent Number: US10955517B2 Publication Date: 2021-03-23 Application Number: 16/787,048 Filing Date: 2020-02-11 Inventor: Jiang, Fu-sheng   Wang chun chieh   Assignee: Qisda Corporation   IPC: G01S3/805 Abstract: An underwater ultrasonic device includes at least one first ultrasonic transducer and at least one second ultrasonic transducer. The first ultrasonic transducer is configured to transmit a plurality of ultrasonic signals and the second ultrasonic transducer is configured to receive a plurality of reflected signals of the ultrasonic signals. The first ultrasonic transducer and the second ultrasonic transducer are disposed with respect to each other. One of the first ultrasonic transducer and the second ultrasonic transducer is curvilinear and another one of the first ultrasonic transducer and the second ultrasonic transducer is curvilinear or straight linear.
2
US2021013033A1
Conductive Feature Formation and Structure
Publication/Patent Number: US2021013033A1 Publication Date: 2021-01-14 Application Number: 17/036,734 Filing Date: 2020-09-29 Inventor: Chang, Cheng-wei   Hung, Min-hsiu   Huang, Hung-yi   Wang, Chun Chieh   Lin, Yu-ting   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L21/02 Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.
3
US2021040332A1
FOULING-PROOF STRUCTURE
Publication/Patent Number: US2021040332A1 Publication Date: 2021-02-11 Application Number: 16/810,873 Filing Date: 2020-03-06 Inventor: Chang, Ching-hsiang   Yeh, Kuo-hsing   Wang chun chieh   Assignee: JANTEC CORP.   IPC: C09D5/16 Abstract: A fouling-proof structure is applicable to synthetic leather or fabric and it includes an alcohol-resistant layer; and a water-based fouling-proof layer disposed on the alcohol-resistant layer, wherein the alcohol-resistant layer is formed by curing an alcohol-resistant combination, and the alcohol-resistant combination comprises polyurethane resin, wherein the water-based fouling-proof layer is formed by curing a water-based fouling-proof combination, and the water-based fouling-proof combination comprises polyurethane resin, water, polymerized siloxanes, water-based PTFE and silicone oil.
4
EP3772550A1
STAIN-PROOF STRUCTURE AND PRODUCTION METHOD THEREOF
Publication/Patent Number: EP3772550A1 Publication Date: 2021-02-10 Application Number: 20170899.7 Filing Date: 2020-04-22 Inventor: Chang, Ching-hsiang   Yeh, Kuo-hsing   Wang chun chieh   Assignee: Jantec Corp.   IPC: D06N3/14 Abstract: A fouling-proof structure (10) is applicable to synthetic leather or fabric and it includes an alcohol-resistant layer (12); and a water-based fouling-proof layer (13) disposed on the alcohol-resistant layer (12), wherein the alcohol-resistant layer (12) is formed by curing an alcohol-resistant combination, and the alcohol-resistant combination comprises polyurethane resin, wherein the water-based fouling-proof layer (13) is formed by curing a water-based fouling-proof combination, and the water-based fouling-proof combination comprises polyurethane resin, water, polymerized siloxanes, water-based PTFE and silicone oil. A method of producing aforementioned fouling-proof structure (10).
5
US2021079925A1
COMPUTER READABLE MEDIUM, DATA PROCESSING METHOD AND DATA PROCESSING SYSTEM
Publication/Patent Number: US2021079925A1 Publication Date: 2021-03-18 Application Number: 16/793,020 Filing Date: 2020-02-18 Inventor: Hsu, Ming-hsiang   Wang chun chieh   Wu, Hung-tsai   Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   IPC: F04D27/00 Abstract: A data processing method is proposed, including: sensing, via at least one sensing portion, target information of a target device; receiving and processing, via an electronic device, the target information of the sensing portion to form feature information; processing, via the electronic device, the feature information into a label matrix, and establishing, via an artificial intelligence training method, a target model based on the label matrix; and after the electronic device captures real-time information of the target device, predicting, via the target model, a life limit of the target device, wherein a content of the target information is corresponding to a content of the real-time information. Thus, a good target model is constituted and is advantageous in training artificial intelligence by processing the feature information into the label matrix.
6
US10910468B2
Capacitor structure
Publication/Patent Number: US10910468B2 Publication Date: 2021-02-02 Application Number: 16/739,120 Filing Date: 2020-01-10 Inventor: Park, Cheol Soo   Chen, Ming-tang   Wang chun chieh   Assignee: Winbond Electronics Corp.   IPC: H01L49/02 Abstract: Provided is a capacitor structure including a substrate, a cup-shaped lower electrode, a top supporting layer, a capacitor dielectric layer, and an upper electrode. The cup-shaped lower electrode is located on the substrate. The top supporting layer surrounds the upper portion of the cup-shaped lower electrode. The top supporting layer includes a high-k material. Surfaces of the cup-shaped lower electrode and the top supporting layer are covered by the capacitor dielectric layer. A surface of the capacitor dielectric layer is covered by the upper electrode.
7
EP3171623B1
METHOD FOR INTERFERENCE COORDINATION, NETWORK SERVER AND COMMUNICATION SYSTEM USING THE SAME
Publication/Patent Number: EP3171623B1 Publication Date: 2021-02-24 Application Number: 15201567.3 Filing Date: 2015-12-21 Inventor: Wang chun chieh   Su, Jun-jie   Huang, Kuei-li   Assignee: Industrial Technology Research Institute   IPC: H04W16/10
8
US2021040349A1
METHOD OF PRODUCING A FOULING-PROOF STRUCTURE
Publication/Patent Number: US2021040349A1 Publication Date: 2021-02-11 Application Number: 16/810,875 Filing Date: 2020-03-06 Inventor: Chang, Ching-hsiang   Yeh, Kuo-hsing   Wang chun chieh   Assignee: JANTEC CORP.   IPC: C09D175/08 Abstract: A method of producing a fouling-proof structure, comprising steps of a) coating an alcohol-resistant combination on a substrate and then drying the alcohol-resistant combination at 80-160° C. to form an alcohol-resistant layer; and b) coating a water-based fouling-proof combination on the alcohol-resistant layer and then drying the water-based fouling-proof combination above 140° C. to form a water-based fouling-proof layer, wherein the alcohol-resistant layer is formed by curing an alcohol-resistant combination, and the alcohol-resistant combination comprises polyurethane resin, wherein the water-based fouling-proof layer is formed by curing a water-based fouling-proof combination, and the water-based fouling-proof combination comprises polyurethane resin, water, polymerized siloxanes, water-based PTFE and silicone oil.
9
US2021067062A1
ELECTRONIC DEVICE AND ELECTRIC ENERGY CONVERSION METHOD THEREOF
Publication/Patent Number: US2021067062A1 Publication Date: 2021-03-04 Application Number: 17/002,736 Filing Date: 2020-08-25 Inventor: Liu, Jui-ta   Wang chun chieh   Li, Chih-hsiang   Peng, Kuo-liang   Assignee: Coretronic Corporation   IPC: H02N2/18 Abstract: Provided is an electronic device and an electric energy conversion method. The electronic device includes at least one moving component, a transducer system, a charging and discharging system, and a power supply system. The transducer system has at least one piezoelectric membrane and a storage unit. The at least one piezoelectric membrane is disposed on the at least one moving component, and the storage unit is electrically coupled to the at least one piezoelectric membrane. The charging and discharging system is electrically coupled to the at least one moving component and the transducer system. The power supply system is electrically coupled to the at least one moving component, the transducer system, and the charging and discharging system to provide main energy. The at least one moving component starts to operate, the at least one moving component leads the at least one piezoelectric membrane to deform elastically to generate assisting charges.
10
US2021036147A1
GATE STRUCTURE, METHOD OF FORMING THE SAME, AND SEMICONDUCTOR DEVICE HAVING THE SAME
Publication/Patent Number: US2021036147A1 Publication Date: 2021-02-04 Application Number: 16/888,846 Filing Date: 2020-05-31 Inventor: Wang chun chieh   Yeh, Sheng-wei   Pai, Yueh-ching   Yang, Chi-jen   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L29/78 Abstract: Provided are a gate structure and a method of forming the same. The gate structure includes a gate dielectric layer, a metal layer, and a cluster layer. The metal layer is disposed over the gate dielectric layer. The cluster layer is sandwiched between the metal layer and the gate dielectric layer, wherein the cluster layer at least includes an amorphous silicon layer, an amorphous carbon layer, or an amorphous germanium layer. In addition, a semiconductor device including the gate structure is provided.
11
US2021096242A1
UNDERWATER ULTRASONIC DEVICE
Publication/Patent Number: US2021096242A1 Publication Date: 2021-04-01 Application Number: 17/017,724 Filing Date: 2020-09-11 Inventor: Jiang, Fu-sheng   Wang chun chieh   Chan, Yi-hsiang   Shiu, Heng-yi   Liu, Hsin-chih   Assignee: QISDA CORPORATION   IPC: G01S15/66 Abstract: An underwater ultrasonic device includes a curvilinear ultrasonic transducer and a plurality of straight linear ultrasonic transducers. The straight linear ultrasonic transducers are disposed with respect to the curvilinear ultrasonic transducer. A first angle is included between the straight linear ultrasonic transducers. One of the curvilinear ultrasonic transducer and the straight linear ultrasonic transducer is configured to transmit a plurality of ultrasonic signals. Another one of the curvilinear ultrasonic transducer and the straight linear ultrasonic transducer is configured to receive a plurality of reflected signals of the ultrasonic signals.
12
US10937910B2
Semiconductor structure with source/drain multi-layer structure and method for forming the same
Publication/Patent Number: US10937910B2 Publication Date: 2021-03-02 Application Number: 16/654,175 Filing Date: 2019-10-16 Inventor: Wang chun chieh   Lin, Yu-ting   Pai, Yueh-ching   Chang, Shih-chieh   Yang, Huai-tei   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD   IPC: H01L29/78 Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure formed over a fin structure and a gate spacer formed on a sidewall surface of the gate structure. The semiconductor structure also includes a first source/drain (S/D) epitaxial layer formed in the fin structure and adjacent to the gate spacer, and a second S/D epitaxial layer formed over the first S/D epitaxial layer. A top surface of the second S/D layer is higher than a top surface of the first S/D epitaxial layer.
13
US10928869B2
Heat dissipation module
Publication/Patent Number: US10928869B2 Publication Date: 2021-02-23 Application Number: 16/355,847 Filing Date: 2019-03-18 Inventor: Wang chun chieh   Liao, Wen-neng   Hsieh, Cheng-wen   Chen, Wei-chin   Ke, Jau-han   Assignee: Acer Incorporated   IPC: G06F1/20 Abstract: A heat dissipation module including a chamber, a first cooling member, and a barrier part is provided. The chamber has an accommodating space, at least one inlet, and at least one outlet. The at least one inlet is disposed in a first side wall of the chamber and communicates with the accommodating space. The at least one outlet is disposed in a second side wall of the chamber away from the at least one inlet and communicates with the accommodating space. The first cooling member is disposed in the accommodating space. The first cooling member has a guiding surface which extends obliquely upward. The barrier part is disposed outside the guiding surface of the first cooling member and has at least one through hole.
14
US10565745B2
Fast projection matching method for computed tomography images
Publication/Patent Number: US10565745B2 Publication Date: 2020-02-18 Application Number: 16/022,870 Filing Date: 2018-06-29 Inventor: Wang chun chieh   Assignee: NATIONAL SYNCHROTRON RADIATION RESEARCH CENTER   IPC: G06T11/00 Abstract: A fast projection matching method for computed tomography (CT) images is provided. The method mainly bases on an iterative algorithm. The algorithm simplifies a traditional issue of three-dimensional projection matching into a two-dimensional projection-matching problem by pre-correcting the Y-axis offset and ϕ shift of each projection intensity image using common-line concept, thereby making the complex CT alignment processing faster and more reliable. This majorly reduces the hardware requirements for CT and data processing, which facilitates the applications in other three dimensional tomographic techniques, such as X-ray micro-CT or electron tomography.
15
US10693950B2
Control method for network communication system including base station network management server and multi-access edge computing ecosystem device
Publication/Patent Number: US10693950B2 Publication Date: 2020-06-23 Application Number: 15/843,326 Filing Date: 2017-12-15 Inventor: Chen, Yen-chiu   Wang chun chieh   Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   IPC: H04L29/08 Abstract: A control method for network communication system including base station network management server comprises of obtaining an item of neighbor base station identification information of a neighbor base station by a first base station; providing the first base station identification information to a base station network management server by the first base station; obtaining a first base station neighbor information from the base station network management server by a first MEC platform; producing an item of first platform neighbor information by the first MEC platform; determining whether a request signal matches the first platform neighbor information after receiving the request signal from a second MEC platform; providing the first platform identification information to the second MEC platform while determining that the request signal matches the first platform neighbor information.
16
US2020326400A1
UNDERWATER ULTRASONIC DEVICE
Publication/Patent Number: US2020326400A1 Publication Date: 2020-10-15 Application Number: 16/787,048 Filing Date: 2020-02-11 Inventor: Jiang, Fu-sheng   Wang chun chieh   Assignee: QISDA CORPORATION   IPC: G01S3/805 Abstract: An underwater ultrasonic device includes at least one first ultrasonic transducer and at least one second ultrasonic transducer. The first ultrasonic transducer is configured to transmit a plurality of ultrasonic signals and the second ultrasonic transducer is configured to receive a plurality of reflected signals of the ultrasonic signals. The first ultrasonic transducer and the second ultrasonic transducer are disposed with respect to each other. One of the first ultrasonic transducer and the second ultrasonic transducer is curvilinear and another one of the first ultrasonic transducer and the second ultrasonic transducer is curvilinear or straight linear.
17
US10804097B2
Conductive feature formation and structure
Publication/Patent Number: US10804097B2 Publication Date: 2020-10-13 Application Number: 16/568,720 Filing Date: 2019-09-12 Inventor: Chang, Cheng-wei   Hung, Min-hsiu   Huang, Hung-yi   Wang, Chun Chieh   Lin, Yu-ting   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L21/02 Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.
18
US2020031049A1
3D LASER PRINTER AND OPERATION METHOD THEREOF
Publication/Patent Number: US2020031049A1 Publication Date: 2020-01-30 Application Number: 16/202,920 Filing Date: 2018-11-28 Inventor: Huang, Chien-hsing   Wang chun chieh   Din, Shih-jer   Assignee: XYZPRINTING, INC.   KINPO ELECTRONICS, INC.   IPC: B29C64/268 Abstract: Disclosed are a 3D laser printer and its operation method. The 3D laser printer includes a body, a powder paving mechanism, a mobile preheating mechanism and a laser module. The body has a chamber, a carrying platform disposed in the chamber, and a feeding machine and a construction machine capable of descending and ascending with respect to the carrying platform. The powder paving mechanism is accommodated in the chamber and capable of moving reciprocately between the feeding machine and the construction machine. The mobile preheating mechanism is accommodated in the chamber and capable of moving reciprocately in at least one of the feeding machine and construction machine. The laser module is configured to be corresponsive to the construction machine. Therefore, non-heat resistant components such as a color printer head and a motor can be installed into the chamber directly to achieve the effects of diversified function and simple installation.
19
US2020303378A1
Semiconductor Device and Method
Publication/Patent Number: US2020303378A1 Publication Date: 2020-09-24 Application Number: 16/895,035 Filing Date: 2020-06-08 Inventor: Wang chun chieh   Pai, Yueh-ching   Yang, Huai-tei   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L27/092 Abstract: A semiconductor device including a cap layer and a method for forming the same are disclosed. In an embodiment, a method includes epitaxially growing a first semiconductor layer over an N-well; etching the first semiconductor layer to form a first recess; epitaxially growing a second semiconductor layer filling the first recess; etching the second semiconductor layer, the first semiconductor layer, and the N-well to form a first fin; forming a shallow trench isolation region adjacent the first fin; and forming a cap layer over the first fin, the cap layer contacting the second semiconductor layer, forming the cap layer including performing a pre-clean process to remove a native oxide from exposed surfaces of the second semiconductor layer; performing a sublimation process to produce a first precursor; and performing a deposition process wherein material from the first precursor is deposited on the second semiconductor layer to form the cap layer.
20
US10566415B2
Capacitor structure and method of manufacturing the same
Publication/Patent Number: US10566415B2 Publication Date: 2020-02-18 Application Number: 15/986,827 Filing Date: 2018-05-23 Inventor: Park, Cheol Soo   Chen, Ming-tang   Wang chun chieh   Assignee: Winbond Electronics Corp.   IPC: H01L49/02 Abstract: Provided is a capacitor structure including a substrate, a cup-shaped lower electrode, a top supporting layer, a capacitor dielectric layer, and an upper electrode. The cup-shaped lower electrode is located on the substrate. The top supporting layer surrounds the upper portion of the cup-shaped lower electrode. The top supporting layer includes a high-k material. Surfaces of the cup-shaped lower electrode and the top supporting layer are covered by the capacitor dielectric layer. A surface of the capacitor dielectric layer is covered by the upper electrode.
Total 32 pages