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1
US202035629A1
PACKAGED SEMICONDUCTOR DEVICE AND METHOD FOR PREPARING THE SAME
Publication/Patent Number: US202035629A1 Publication Date: 2020-01-30 Application Number: 20/181,604 Filing Date: 2018-07-26 Inventor: Wang mao ying   Assignee: NANYA TECHNOLOGY CORPORATION   IPC: H01L23/00 Abstract: The present disclosure provides a packaged semiconductor device and a method for preparing the same. The packaged semiconductor device includes a chip having a conductive pad; a first insulating layer disposed on the chip; a second insulating layer disposed on the first insulating layer; a conductive film disposed on the second insulating layer, a redistribution layer disposed on the conductive film; a probe pad disposed on the redistribution layer; and a third insulating, layer disposed on the redistribution layer and the second insulating layer, wherein the third insulating layer covers a portion of the probe pad, and there is no undercut at a region between the redistribution layer and the probe pad. The size of the probe pad is not limited by the undercut, as the size of the probe pad needs to be reduced in order to meet the requirement of continuous minimization of chip size.
2
US2020035629A1
PACKAGED SEMICONDUCTOR DEVICE AND METHOD FOR PREPARING THE SAME
Publication/Patent Number: US2020035629A1 Publication Date: 2020-01-30 Application Number: 16/046,100 Filing Date: 2018-07-26 Inventor: Wang mao ying   Assignee: NANYA TECHNOLOGY CORPORATION   IPC: H01L23/00 Abstract: The present disclosure provides a packaged semiconductor device and a method for preparing the same. The packaged semiconductor device includes a chip having a conductive pad; a first insulating layer disposed on the chip; a second insulating layer disposed on the first insulating layer; a conductive film disposed on the second insulating layer, a redistribution layer disposed on the conductive film; a probe pad disposed on the redistribution layer; and a third insulating, layer disposed on the redistribution layer and the second insulating layer, wherein the third insulating layer covers a portion of the probe pad, and there is no undercut at a region between the redistribution layer and the probe pad. The size of the probe pad is not limited by the undercut, as the size of the probe pad needs to be reduced in order to meet the requirement of continuous minimization of chip size.
3
US10573602B2
Semiconductor device and method of forming the same
Publication/Patent Number: US10573602B2 Publication Date: 2020-02-25 Application Number: 16/015,559 Filing Date: 2018-06-22 Inventor: Wang mao ying   Huang, Pei-lin   Assignee: NANYA TECHNOLOGY CORPORATION   IPC: H01L23/552 Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a first die and a conductive layer. The first die is to be bonded with, in a direction, a second die external to the semiconductor device. The conductive layer, between the first die and the second die in the direction, has a reference ground.
4
US2020395242A1
SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF
Publication/Patent Number: US2020395242A1 Publication Date: 2020-12-17 Application Number: 16/439,690 Filing Date: 2019-06-12 Inventor: Shih, Shing-yih   Wang mao ying   Wu, Hung-mo   Assignee: NANYA TECHNOLOGY CORPORATION   IPC: H01L21/768 Abstract: A method of forming a semiconductor structure includes the following steps. A dielectric layer is formed over a conductive line. A photoresist layer is formed over the dielectric layer. The photoresist layer is patterned to form a mask feature and an opening is defined by the mask feature. The opening has a bottom portion and a top portion communicated to the bottom portion, and the top portion is wider than the bottom portion. The dielectric layer is etched to form a via hole in the dielectric layer using the mask feature as an etch mask, such that the via hole has a bottom portion and a tapered portion over the bottom portion. The conductive material is filled in the via hole to form a conductive via.
5
US2020286777A1
INTERCONNECT STRUCTURE AND METHOD FOR PREPARING THE SAME
Publication/Patent Number: US2020286777A1 Publication Date: 2020-09-10 Application Number: 16/389,644 Filing Date: 2019-04-19 Inventor: Wang mao ying   Shih, Shing-yih   Wu, Hung-mo   Ting, Yung-te   Lin, Yu-ting   Assignee: NANYA TECHNOLOGY CORPORATION   IPC: H01L21/768 Abstract: The present disclosure provides a method for preparing an interconnect structure. One aspect of the present disclosure provides a method for preparing an interconnect structure. The method includes the following steps. A first dielectric layer is provided over a first connecting line. A first upper via opening is formed in the first dielectric layer, wherein the first upper via opening has a first width. A first lower via opening is formed in the first dielectric layer, wherein the first lower via opening is formed under and coupled to the first upper via opening. The first lower via opening has a second width less than the first width of the first upper via opening. A connecting via is formed in the first upper via opening and the first lower via opening. A second connecting line is formed over the connecting via.
6
US2020176377A1
ELECTRONIC DEVICE AND METHOD OF MANUFACTURING THE SAME
Publication/Patent Number: US2020176377A1 Publication Date: 2020-06-04 Application Number: 16/251,858 Filing Date: 2019-01-18 Inventor: Lin, Yu-ting   Wang mao ying   Shih, Shing-yih   Wu, Hung-mo   Ting, Yung-te   Assignee: NANYA TECHNOLOGY CORPORATION   IPC: H01L23/522 Abstract: The present disclosure provides an electronic device and a method of manufacturing the same. The electronic device includes a multilayer component, at least one contact pad, a passivation layer, a dielectric layer, and a metallic layer. The contact pad is disposed on the multilayer component, the passivation layer covers the multilayer component and the contact pad, and the dielectric layer is disposed on the passivation layer. The metallic layer penetrates through the dielectric layer and the passivation layer and is connected to the contact pad, and the metallic layer discretely tapers at positions of decreasing distance from the contact pad.
7
US2020286775A1
INTERCONNECT STRUCTURE AND METHOD FOR PREPARING THE SAME
Publication/Patent Number: US2020286775A1 Publication Date: 2020-09-10 Application Number: 16/291,376 Filing Date: 2019-03-04 Inventor: Wang mao ying   Shih, Shing-yih   Wu, Hung-mo   Ting, Yung-te   Lin, Yu-ting   Assignee: NANYA TECHNOLOGY CORPORATION   IPC: H01L21/768 Abstract: The present disclosure provides an interconnect structure. The interconnect structure includes a first connecting line, a second connecting line disposed over the first connecting line, and a connecting via disposed in a dielectric structure between the first connecting line and the second connecting line, and electrically connecting the first connecting line and the second connecting line. The connecting via includes a head portion and a body portion, and a width of the head portion is greater than a width of the body portion.
8
US2019393160A1
SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME
Publication/Patent Number: US2019393160A1 Publication Date: 2019-12-26 Application Number: 16/015,559 Filing Date: 2018-06-22 Inventor: Wang mao ying   Huang, Pei-lin   Assignee: NANYA TECHNOLOGY CORPORATION   IPC: H01L23/552 Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a first die and a conductive layer. The first die is to be bonded with, in a direction, a second die external to the semiconductor device. The conductive layer, between the first die and the second die in the direction, has a reference ground.
9
US8368134B2
Nonvolatile memory device and method for fabricating the same
Publication/Patent Number: US8368134B2 Publication Date: 2013-02-05 Application Number: 12/767,639 Filing Date: 2010-04-26 Inventor: Chang, Ming-cheng   Hung, Chih-hsiung   Wang mao ying   Hsu, Wei-hui   Assignee: Nanya Technology Corporation   IPC: H01L27/108 Abstract: A nonvolatile memory device and method for fabricating the same are provided. The method for fabricating the nonvolatile memory device comprises providing a substrate. A tunnel insulating layer and a first conductive layer are formed in the substrate. A trench is formed through the first conductive layer and the tunnel insulating layer, wherein a portion of the substrate is exposed from the trench. A first insulating layer is formed in the trench. A second insulating layer is formed on sidewalls of the first insulating layer. A third insulating layer is conformably formed in the trench, covering the first insulating layer on a bottom portion of the trench and the second insulating layer on the sidewalls of the trench, wherein thickness of the third insulating layer on the sidewalls is thinner than that on the bottom of the trench. A control gate is formed on the third insulating layer in the trench.
10
US8093639B2
Method for fabricating a semiconductor device
Publication/Patent Number: US8093639B2 Publication Date: 2012-01-10 Application Number: 12/698,747 Filing Date: 2010-02-02 Inventor: Ho, Jar-ming   Wang mao ying   Assignee: Nanya Technology Corporation   IPC: H01L27/108 Abstract: An embodiment of the invention provides a method for forming a semiconductor device comprising providing a substrate with a pad layer formed thereon. The pad layer and the substrate are patterned to form a plurality of trenches. A trench top insulating layer is formed in each trench. Wherein the trench top insulating layer protrudes from the substrate and has an extension portion extending to the pad layer. The pad layer and the substrate are etched by using the trench top insulating layers and the extension portions as a mask to form a recess in the substrate. And a recess gate is formed in the recess.
11
TWI349339B
Non-volatile memory and fabricating method thereof
Publication/Patent Number: TWI349339B Publication Date: 2011-09-21 Application Number: 96132709 Filing Date: 2007-09-03 Inventor: Chang, Ming Cheng   Hsu, Wei Hui   Wang, Mao Ying   Hung, Chih Hsiung   Assignee: NANYA TECHNOLOGY CORPORATION.   IPC: H01L21/8247 Abstract: A method of fabricating a nonvolatile memory is provided. The method of fabricating the nonvolatile memory comprises providing a substrate. A tunnel insulating layer and a first conductive layer are formed in the substrate in sequence. A trench is form through the first conductive layer and the tunnel insulating layer
12
TWI349310B
Method of fabricating a semiconductor device
Publication/Patent Number: TWI349310B Publication Date: 2011-09-21 Application Number: 96124893 Filing Date: 2007-07-09 Inventor: Wu, Chang Rong   Wang, Jer Chyi   Lai, Chao Sung   Chou, Liang Pin   Su, Kuo Hui   Hsu, Wei Hui   Wang, Mao Ying   Assignee: NANYA TECHNOLOGY CORPORATION.   IPC: H01L21/314 Abstract: A method of fabricating a semiconductor device is provided. The method of fabricating the semiconductor device comprises providing a substrate. A plasma treatment is performed to fluorinate and to nitrify a surface of the substrate at an atmosphere with fluoride nitride compound at the same time. A dielectric layer is formed on the substrate.
13
US7709318B2
Method for fabricating a semiconductor device
Publication/Patent Number: US7709318B2 Publication Date: 2010-05-04 Application Number: 11/682,176 Filing Date: 2007-03-05 Inventor: Ho, Jar-ming   Wang mao ying   Assignee: Nanya Technology Corporation   IPC: H01L21/8234 Abstract: An embodiment of the invention provides a method for forming a semiconductor device comprising providing a substrate with a pad layer formed thereon. The pad layer and the substrate are patterned to form a plurality of trenches. A trench top insulating layer is formed in each trench. Wherein the trench top insulating layer protrudes from the substrate and has an extension portion extending to the pad layer. The pad layer and the substrate are etched by using the trench top insulating layers and the extension portions as a mask to form a recess in the substrate. And a recess gate is formed in the recess.
14
US2010133608A1
METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE
Publication/Patent Number: US2010133608A1 Publication Date: 2010-06-03 Application Number: 12/698,747 Filing Date: 2010-02-02 Inventor: Ho, Jar-ming   Wang mao ying   Assignee: NANYA TECHNOLOGY CORPORATION   IPC: H01L29/78 Abstract: An embodiment of the invention provides a method for forming a semiconductor device comprising providing a substrate with a pad layer formed thereon. The pad layer and the substrate are patterned to form a plurality of trenches. A trench top insulating layer is formed in each trench. Wherein the trench top insulating layer protrudes from the substrate and has an extension portion extending to the pad layer. The pad layer and the substrate are etched by using the trench top insulating layers and the extension portions as a mask to form a recess in the substrate. And a recess gate is formed in the recess.
15
US2010200903A1
NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME
Publication/Patent Number: US2010200903A1 Publication Date: 2010-08-12 Application Number: 12/767,639 Filing Date: 2010-04-26 Inventor: Chang, Ming-cheng   Hung, Chih-hsiung   Wang mao ying   Hsu, Wei-hui   Assignee: NANYA TECHNOLOGY CORPORATION   IPC: H01L29/788 Abstract: A nonvolatile memory device and method for fabricating the same are provided. The method for fabricating the nonvolatile memory device comprises providing a substrate. A tunnel insulating layer and a first conductive layer are formed in the substrate. A trench is formed through the first conductive layer and the tunnel insulating layer, wherein a portion of the substrate is exposed from the trench. A first insulating layer is formed in the trench. A second insulating layer is formed on sidewalls of the first insulating layer. A third insulating layer is conformably formed in the trench, covering the first insulating layer on a bottom portion of the trench and the second insulating layer on the sidewalls of the trench, wherein thickness of the third insulating layer on the sidewalls is thinner than that on the bottom of the trench. A control gate is formed on the third insulating layer in the trench.
16
US7754614B2
Nonvolatile memory device and method for fabricating the same
Publication/Patent Number: US7754614B2 Publication Date: 2010-07-13 Application Number: 12/016,100 Filing Date: 2008-01-17 Inventor: Chang, Ming-cheng   Hung, Chih-hsiung   Wang mao ying   Hsu, Wei-hui   Assignee: Nanya Technologies Corporation   IPC: H01L21/311 Abstract: A nonvolatile memory device and method for fabricating the same are provided. The method for fabricating the nonvolatile memory device comprises providing a substrate. A tunnel insulating layer and a first conductive layer are formed in the substrate. A trench is formed through the first conductive layer and the tunnel insulating layer, wherein a portion of the substrate is exposed from the trench. A first insulating layer is formed in the trench. A second insulating layer is formed on sidewalls of the first insulating layer. A third insulating layer is conformably formed in the trench, covering the first insulating layer on a bottom portion of the trench and the second insulating layer on the sidewalls of the trench, wherein thickness of the third insulating layer on the sidewalls is thinner than that on the bottom of the trench. A control gate is formed on the third insulating layer in the trench.
17
TW200913163A
Non-volatile memory and fabricating method thereof
Publication/Patent Number: TW200913163A Publication Date: 2009-03-16 Application Number: 96132709 Filing Date: 2007-09-03 Inventor: Chang, Ming Cheng   Hsu, Wei Hui   Wang, Mao Ying   Hung, Chih Hsiung   Assignee: NANYA TECHNOLOGY CORPORATION.   IPC: H01L21/8247 Abstract: A method of fabricating a nonvolatile memory is provided. The method of fabricating the nonvolatile memory comprises providing a substrate. A tunnel insulating layer and a first conductive layer are formed in the substrate in sequence. A trench is form through the first conductive layer and the tunnel insulating layer
18
US2009061612A1
NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME
Publication/Patent Number: US2009061612A1 Publication Date: 2009-03-05 Application Number: 12/016,100 Filing Date: 2008-01-17 Inventor: Chang, Ming-cheng   Hung, Chih-hsiung   Wang mao ying   Hsu, Wei-hui   Assignee: NANYA TECHNOLOGY CORPORATION   IPC: H01L21/3205 Abstract: A nonvolatile memory device and method for fabricating the same are provided. The method for fabricating the nonvolatile memory device comprises providing a substrate. A tunnel insulating layer and a first conductive layer are formed in the substrate. A trench is formed through the first conductive layer and the tunnel insulating layer, wherein a portion of the substrate is exposed from the trench. A first insulating layer is formed in the trench. A second insulating layer is formed on sidewalls of the first insulating layer. A third insulating layer is conformably formed in the trench, covering the first insulating layer on a bottom portion of the trench and the second insulating layer on the sidewalls of the trench, wherein thickness of the third insulating layer on the sidewalls is thinner than that on the bottom of the trench. A control gate is formed on the third insulating layer in the trench.
19
TW200903642A
Method of fabricating a semiconductor device
Publication/Patent Number: TW200903642A Publication Date: 2009-01-16 Application Number: 96124893 Filing Date: 2007-07-09 Inventor: Wu, Chang Rong   Wang, Jer Chyi   Lai, Chao Sung   Chou, Liang Pin   Su, Kuo Hui   Hsu, Wei Hui   Wang, Mao Ying   Assignee: NANYA TECHNOLOGY CORPORATION.   IPC: H01L21/314 Abstract: A method of fabricating a semiconductor device is provided. The method of fabricating the semiconductor device comprises providing a substrate. A plasma treatment is performed to fluorinate and to nitrify a surface of the substrate at an atmosphere with fluoride nitride compound at the same time. A dielectric layer is formed on the substrate.
20
US2009017604A1
METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE
Publication/Patent Number: US2009017604A1 Publication Date: 2009-01-15 Application Number: 11/933,742 Filing Date: 2007-11-01 Inventor: Wang mao ying   Wang, Jer-chyi   Hsu, Wei-hui   Chou, Liang-pin   Su, Kuo-hui   Wu, Chang-rong   Lai, Chao-sung   Assignee: NANYA TECHNOLOGY CORPORATION   IPC: H01L21/425 Abstract: A method for fabricating a semiconductor device is provided. The method for fabricating the semiconductor device comprises providing a substrate. Under an atmosphere containing a fluoride nitride compound, a plasma treatment process is performed to simultaneously fluorinate and nitrify a surface of the substrate. Thereafter, a dielectric layer is formed on the substrate.
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