Country
Full text data for US,EP,CN
Type
Legal Validity
Legal Status
Filing Date
Publication Date
Inventor
Assignee
Click to expand
IPC(Section)
IPC(Class)
IPC(Subclass)
IPC(Group)
IPC(Subgroup)
Agent
Agency
Claims Number
Figures Number
Citation Number of Times
Assignee Number
No. Publication Number Title Publication/Patent Number Publication/Patent Number Publication Date Publication Date
Application Number Application Number Filing Date Filing Date
Inventor Inventor Assignee Assignee IPC IPC
1
US2021096173A1
SYSTEM AND METHOD FOR SEMICONDUCTOR DEVICE TESTING
Publication/Patent Number: US2021096173A1 Publication Date: 2021-04-01 Application Number: 16/867,999 Filing Date: 2020-05-06 Inventor: Chen, Hao   Wang mill jer   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: G01R31/28 Abstract: A testing system includes a load board that includes a first circuit board, a first external connector attached to the first circuit board, and a thermal module configured to hold a system-on-wafer structure including a connector and a socket, a connector structure including a second circuit board, wherein the second circuit board is electrically connected to the first external connector, and a second external connector configured to connect to the connector of the system-on-wafer structure, and a test structure configured to connect to the socket of the system-on-wafer structure, the test structure including a third circuit board and pins, wherein adjacent pairs of pins of the test structure are electrically coupled through the third circuit board to form a continuous conductive path extending alternately between the system-on-wafer structure and the adjacent pairs of pins of the test structure.
2
US2021063471A1
TESTING MODULE AND TESTING METHOD USING THE SAME
Publication/Patent Number: US2021063471A1 Publication Date: 2021-03-04 Application Number: 16/805,874 Filing Date: 2020-03-02 Inventor: Chen, Hao   Wang mill jer   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: G01R31/27 Abstract: A testing module for a semiconductor wafer-form package includes a circuit board structure, first connectors, a first connecting structure, second connectors, third connectors and a first bridge connector. The circuit board structure includes two edge regions and a main region located therebetween. The first connectors are located over the edge regions and connected to the circuit board structure. The first connecting structure is located over and distant from the circuit board structure. The second connectors and third connectors are located over and connected to the first connecting structure, where the third connectors are configured to transmit electric signals for testing the semiconductor wafer-form package being placed over the main region. The first bridge connector is electrically coupling the circuit board structure and the first connecting structure by connecting the second connectors and the first connectors.
3
US2021080487A1
ELECTROMAGNETIC SHIELDING DURING WAFER STAGE TESTING
Publication/Patent Number: US2021080487A1 Publication Date: 2021-03-18 Application Number: 16/572,369 Filing Date: 2019-09-16 Inventor: Peng, Ching-nen   Wang, Hsien-tang   Wang mill jer   Lai, Chi-chang   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: G01R1/18 Abstract: A circuit probe includes a shielding probe having a base and a conductive probe ring on the base. A shielding cage is attached to the conductive probe ring and has an interior. The shielding cage is configured to be positioned to contain in the interior of the shielding cage at least one integrated circuit formed on a wafer, and to provide electromagnetic shielding of the at least one integrated circuit during testing of the at least one integrated circuit.
4
US2021057293A1
SEMICONDUCTOR DEVICE STRUCTURE WITH MAGNETIC ELEMENT IN TESTING REGION
Publication/Patent Number: US2021057293A1 Publication Date: 2021-02-25 Application Number: 16/548,183 Filing Date: 2019-08-22 Inventor: Wang mill jer   Chiu, Tang-jung   Lai, Chi-chang   Tsai, Chia-heng   Lii, Mirng-ji   Liao, Weii   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L21/66 Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate having a testing region and multiple first conductive lines over the testing region. The first conductive lines are electrically connected in series. The semiconductor device structure also includes multiple second conductive lines over the testing region. The second conductive lines are electrically connected in series, and the second conductive lines are physically separated from the first conductive lines. The semiconductor device structure further includes multiple magnetic structures wrapping around portions of the first conductive lines and wrapping around portions of the second conductive lines. The magnetic structures are arranged in a column.
5
US10634717B2
Testing apparatus and testing method
Publication/Patent Number: US10634717B2 Publication Date: 2020-04-28 Application Number: 15/884,381 Filing Date: 2018-01-31 Inventor: Chiu, Tang-jung   Lin, Hung-chih   Wang mill jer   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: G01R31/28 Abstract: A testing apparatus for testing an integrated circuit package having a plurality of electrical terminals includes a base, a socket, a plurality of conductive pins and a plurality of conductive pillars. The base includes a plurality of electrical contacts. The socket is disposed on the base and includes a bended portion bended away from the base and a plurality of through holes distributed in the socket. The conductive pins are disposed in the through holes respectively and electrically connected to the electrical contacts, wherein each of the conductive pins protrudes from an upper surface of the socket for forming temporary electrical connections with one of the electrical terminals. The conductive pillars are disposed on the base and connected to the bended portion, wherein each of the conductive pillars electrically connects one of the conductive pins and one of the electrical contacts.
6
US2020256918A1
TESTING APPARATUS AND TESTING METHOD
Publication/Patent Number: US2020256918A1 Publication Date: 2020-08-13 Application Number: 16/858,745 Filing Date: 2020-04-27 Inventor: Chiu, Tang-jung   Lin, Hung-chih   Wang mill jer   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: G01R31/28 Abstract: A testing apparatus for testing an integrated circuit package having a plurality of electrical terminals includes a base, a socket, a plurality of conductive pins and a plurality of conductive pillars. The base includes a plurality of electrical contacts. The socket is disposed on the base and includes a bended portion bended away from the base and a plurality of through holes distributed in the socket. The conductive pins are disposed in the through holes respectively and electrically connected to the electrical contacts, wherein each of the conductive pins protrudes from an upper surface of the socket for forming temporary electrical connections with one of the electrical terminals. The conductive pillars are disposed on the base and connected to the bended portion, wherein each of the conductive pillars electrically connects one of the conductive pins and one of the electrical contacts.
7
US2020245439A1
THREE DIMENSIONAL INTEGRATED CIRCUIT ELECTROSTATIC DISCHARGE PROTECTION AND PREVENTION TEST INTERFACE
Publication/Patent Number: US2020245439A1 Publication Date: 2020-07-30 Application Number: 16/851,873 Filing Date: 2020-04-17 Inventor: Wang mill jer   Peng, Ching-nen   Lin, Hung-chih   Cheng, Hao   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H05F3/02 Abstract: The present disclosure provides a system and method for providing electrostatic discharge protection. A probe card assembly is provided which is electrically connected to a plurality of input/output channels. The probe card assembly can be contacted with a secondary assembly having an interposer electrically connected to one or more wafers each wafer having a device under test. Voltage can be forced on ones of the plural input/output channels of the probe card assembly to slowly dissipate charges resident on the wafer to thereby provide electrostatic discharge protection. A socket assembly adaptable to accept a 3DIC package is also provided, the assembly having a loadboard assembly electrically connected to a plurality of input/output channels. Once the 3DIC package is placed within the socket assembly, voltage is forced on ones of the input/output channels to slowly dissipate charges resident on the 3DIC package to thereby provide electrostatic discharge protection.
8
US10652987B2
Three dimensional integrated circuit electrostatic discharge protection and prevention test interface
Publication/Patent Number: US10652987B2 Publication Date: 2020-05-12 Application Number: 15/882,256 Filing Date: 2018-01-29 Inventor: Wang mill jer   Peng, Ching-nen   Lin, Hung-chih   Cheng, Hao   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H05F3/00 Abstract: The present disclosure provides a system and method for providing electrostatic discharge protection. A probe card assembly is provided which is electrically connected to a plurality of input/output channels. The probe card assembly can be contacted with a secondary assembly having an interposer electrically connected to one or more wafers each wafer having a device under test. Voltage can be forced on ones of the plural input/output channels of the probe card assembly to slowly dissipate charges resident on the wafer to thereby provide electrostatic discharge protection. A socket assembly adaptable to accept a 3DIC package is also provided, the assembly having a loadboard assembly electrically connected to a plurality of input/output channels. Once the 3DIC package is placed within the socket assembly, voltage is forced on ones of the input/output channels to slowly dissipate charges resident on the 3DIC package to thereby provide electrostatic discharge protection.
9
US10698026B2
Testing holders for chip unit and die package
Publication/Patent Number: US10698026B2 Publication Date: 2020-06-30 Application Number: 16/119,871 Filing Date: 2018-08-31 Inventor: Wang mill jer   Liu, Kuo-chuan   Peng, Ching-nen   Lin, Hung-chih   Chen, Hao   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.   IPC: G01R31/28 Abstract: A testing holder for a chip unit, a multi site holding frame for plural chip units and a method for testing a die thereof are provided. The proposed multi site holding frame for testing plural chip units simultaneously includes a first holder frame having a plurality of testing holders. Each of the plurality of testing holders includes a holder body containing a specific one of the plural chip units, and a pressure releasing device formed on the holder body to release an insertion pressure when the specific one of the plural chip units is inserted in the holder body.
10
US10641819B2
Alignment testing for tiered semiconductor structure
Publication/Patent Number: US10641819B2 Publication Date: 2020-05-05 Application Number: 16/126,458 Filing Date: 2018-09-10 Inventor: Wang mill jer   Peng, Ching-nen   Lin, Hung-chih   Chen, Hao   Lee, Mincent   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED   IPC: G01R31/28 Abstract: Among other things, one or more techniques or systems for evaluating a tiered semiconductor structure, such as a stacked CMOS structure, for misalignment are provided. In an embodiment, a connectivity test is performed on vias between a first layer and a second layer to determine a via diameter and a via offset that are used to evaluate misalignment. In an embodiment, a connectivity test for vias within a first layer is performed to determine an alignment rotation based upon which vias are connected through a conductive arc within a second layer or which vias are connected to a conductive pattern out of a set of conductive patterns. In this way, the via diameter, the via offset, or the alignment rotation are used to evaluate the tiered semiconductor structure, such as during a stacked CMOS process, for misalignment.
11
US2020326370A1
TESTING HOLDERS FOR CHIP UNIT AND DIE PACKAGE
Publication/Patent Number: US2020326370A1 Publication Date: 2020-10-15 Application Number: 16/912,017 Filing Date: 2020-06-25 Inventor: Wang mill jer   Liu, Kuo-chuan   Peng, Ching-nen   Lin, Hung-chih   Chen, Hao   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.   IPC: G01R31/28 Abstract: A testing holder for a chip unit, a multi site holding frame for plural chip units and a method for testing a die thereof are provided. The proposed multi site holding frame for testing plural chip units simultaneously includes a first holder frame having a plurality of testing holders. Each of the plurality of testing holders includes a holder body containing a specific one of the plural chip units, and a pressure releasing device formed on the holder body to release an insertion pressure when the specific one of the plural chip units is inserted in the holder body.
12
US2020264227A1
ALIGNMENT TESTING FOR TIERED SEMICONDUCTOR STRUCTURE
Publication/Patent Number: US2020264227A1 Publication Date: 2020-08-20 Application Number: 16/865,804 Filing Date: 2020-05-04 Inventor: Wang mill jer   Peng, Ching-nen   Lin, Hung-chih   Chen, Hao   Lee, Mincent   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED   IPC: G01R31/28 Abstract: Among other things, one or more techniques or systems for evaluating a tiered semiconductor structure, such as a stacked CMOS structure, for misalignment are provided. In an embodiment, a connectivity test is performed on vias between a first layer and a second layer to determine a via diameter and a via offset that are used to evaluate misalignment. In an embodiment, a connectivity test for vias within a first layer is performed to determine an alignment rotation based upon which vias are connected through a conductive arc within a second layer or which vias are connected to a conductive pattern out of a set of conductive patterns. In this way, the via diameter, the via offset, or the alignment rotation are used to evaluate the tiered semiconductor structure, such as during a stacked CMOS process, for misalignment.
13
US10725090B2
Test circuit and method
Publication/Patent Number: US10725090B2 Publication Date: 2020-07-28 Application Number: 15/893,466 Filing Date: 2018-02-09 Inventor: Wang mill jer   Peng, Ching-nen   Lin, Hung-chih   Hsu, Sen-kuei   Wang, Chuan-ching   Chen, Hao   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.   IPC: G01R31/265 Abstract: A method that is disclosed that includes the operations outlined below. Dies are arranged on a test fixture, and each of the dies includes first antennas and at least one via array, wherein the at least one via array is formed between at least two of the first antennas to separate the first antennas. By the first antennas of the dies, test processes are sequentially performed on an under-test device including second antennas that positionally correspond to the first antennas, according to signal transmissions between the first antennas and the second antennas.
14
US2020348341A1
DEVICES FOR HIGH-DENSITY PROBING TECHNIQUES AND METHOD OF IMPLEMENTING THE SAME
Publication/Patent Number: US2020348341A1 Publication Date: 2020-11-05 Application Number: 16/933,576 Filing Date: 2020-07-20 Inventor: Wang mill jer   Peng, Ching-nen   Lin, Hung-chih   Lin, Wei-hsun   Hsu, Sen-kuei   Liu, De-jian   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: G01R1/073 Abstract: A testing apparatus with reduced warping of the probe card and a method of reducing warping of a probe card of a testing apparatus are disclosed. The testing apparatus can include a testing head and a platform opposite the testing head, where the testing head and platform move relative to one another to bring a sample into contact with probing tips of the testing apparatus. The testing head can include a probe card printed circuit board, a stiffener, a discontinuous backer and a plurality of probing tips. The stiffener can be coupled to and reinforcing the probe card. The discontinuous backer can extend from the probe card to the stiffener, and can include at least one unfilled void extending from the stiffener to the probe card. The plurality of probing tips can extend from a distal end of the testing head.
15
US2020355737A1
TEST CIRCUIT AND METHOD
Publication/Patent Number: US2020355737A1 Publication Date: 2020-11-12 Application Number: 16/939,784 Filing Date: 2020-07-27 Inventor: Wang mill jer   Peng, Ching-nen   Lin, Hung-chih   Hsu, Sen-kuei   Wang, Chuan-ching   Chen, Hao   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED   IPC: G01R31/265 Abstract: A method that is disclosed that includes the operations outlined below. Dies are arranged on a test fixture, and each of the dies includes first antennas and at least one via array, wherein the at least one via array is formed between at least two of the first antennas to separate the first antennas. By the first antennas of the dies, test processes are sequentially performed on an under-test device including second antennas that positionally correspond to the first antennas, according to signal transmissions between the first antennas and the second antennas.
16
US10718790B2
Devices for high-density probing techniques and method of implementing the same
Publication/Patent Number: US10718790B2 Publication Date: 2020-07-21 Application Number: 16/378,288 Filing Date: 2019-04-08 Inventor: Wang mill jer   Peng, Ching-nen   Lin, Hung-chih   Lin, Wei-hsun   Hsu, Sen-kuei   Liu, De-jian   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: G01R1/073 Abstract: A testing apparatus with reduced warping of the probe card and a method of reducing warping of a probe card of a testing apparatus are disclosed. The testing apparatus can include a testing head and a platform opposite the testing head, where the testing head and platform move relative to one another to bring a sample into contact with probing tips of the testing apparatus. The testing head can include a probe card printed circuit board, a stiffener, a discontinuous backer and a plurality of probing tips. The stiffener can be coupled to and reinforcing the probe card. The discontinuous backer can extend from the probe card to the stiffener, and can include at least one unfilled void extending from the stiffener to the probe card. The plurality of probing tips can extend from a distal end of the testing head.
17
US2020357785A1
SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
Publication/Patent Number: US2020357785A1 Publication Date: 2020-11-12 Application Number: 16/937,343 Filing Date: 2020-07-23 Inventor: Lu, Hsiang-tai   Chen, Shuo-mao   Wang mill jer   Hsu, Feng-cheng   Yang, Chao-hsiang   Jeng, Shin-puu   Hong, Cheng-yi   Lin, Chih-hsien   Chen, Dai-jang   Lin, Chen-hua   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.   IPC: H01L25/00 Abstract: A method of manufacturing a semiconductor structure forming a redistribution layer (RDL); forming a conductive pad over the RDL; performing a first electrical test through the conductive pad; bonding a first die over the RDL by a connector; disposing a first underfill material to surround the connector; performing a second electrical test through the conductive pad; disposing a second die over the first die and the conductive pad; and disposing a second underfill material to surround the second die, wherein the conductive pad is at least partially in contact with the second underfill material, and is protruded from the RDL during the first electrical test and the second electrical test.
18
US2020379013A1
TEST PROBING STRUCTURE
Publication/Patent Number: US2020379013A1 Publication Date: 2020-12-03 Application Number: 16/995,866 Filing Date: 2020-08-18 Inventor: Wang mill jer   Chen, Ching-fang   Goel, Sandeep Kumar   Yuan, Chung-sheng   Yeh, Chao-yang   Liu, Chin-chou   Lee, Yun-han   Lin, Hung-chih   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: G01R1/073 Abstract: A testing probe structure for wafer level testing semiconductor IC packaged devices under test (DUT). The structure includes a substrate, through substrate vias, a bump array formed on a first surface of the substrate for engaging a probe card, and at least one probing unit on a second surface of the substrate. The probing unit includes a conductive probe pad formed on one surface of the substrate and at least one microbump interconnected to the pad. The pads are electrically coupled to the bump array through the vias. Some embodiments include a plurality of microbumps associated with the pad which are configured to engage a mating array of microbumps on the DUT. In some embodiments, the DUT may be probed by applying test signals from a probe card through the bump and microbump arrays without direct probing of the DUT microbumps.
19
US10782318B2
Test probing structure
Publication/Patent Number: US10782318B2 Publication Date: 2020-09-22 Application Number: 15/789,338 Filing Date: 2017-10-20 Inventor: Wang mill jer   Chen, Ching-fang   Goel, Sandeep Kumar   Yuan, Chung-sheng   Yeh, Chao-yang   Liu, Chin-chou   Lee, Yun-han   Lin, Hung-chih   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: G01R1/073 Abstract: A testing probe structure for wafer level testing semiconductor IC packaged devices under test (DUT). The structure includes a substrate, through substrate vias, a bump array formed on a first surface of the substrate for engaging a probe card, and at least one probing unit on a second surface of the substrate. The probing unit includes a conductive probe pad formed on one surface of the substrate and at least one microbump interconnected to the pad. The pads are electrically coupled to the bump array through the vias. Some embodiments include a plurality of microbumps associated with the pad which are configured to engage a mating array of microbumps on the DUT. In some embodiments, the DUT may be probed by applying test signals from a probe card through the bump and microbump arrays without direct probing of the DUT microbumps.
20
US10741537B2
Semiconductor structure and manufacturing method thereof
Publication/Patent Number: US10741537B2 Publication Date: 2020-08-11 Application Number: 15/725,766 Filing Date: 2017-10-05 Inventor: Lu, Hsiang-tai   Chen, Shuo-mao   Wang mill jer   Hsu, Feng-cheng   Yang, Chao-hsiang   Jeng, Shin-puu   Hong, Cheng-yi   Lin, Chih-hsien   Chen, Dai-jang   Lin, Chen-hua   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COOMPANY LTD.   IPC: H01L25/00 Abstract: A method of manufacturing a semiconductor structure includes forming a redistribution layer (RDL); forming a conductive member over the RDL; performing a first electrical test through the conductive member; disposing a first die over the RDL; performing a second electrical test through the conductive member; and disposing a second die over the first die and the conductive member.
Total 7 pages