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1 | US2021043772A1 |
FinFET Structures and Methods of Forming the Same
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Publication/Patent Number: US2021043772A1 | Publication Date: 2021-02-11 | Application Number: 17/077,383 | Filing Date: 2020-10-22 | Inventor： Wang yu sheng Hung, Chi-cheng Lee, Chia-ching Wu, Chung-chiang Su, Ching-hwanq | Assignee: Taiwan Semiconductor Manufacturing Co., Ltd. | IPC: H01L29/78 | Abstract: A method includes forming a first semiconductor fin protruding from a substrate and forming a gate stack over the first semiconductor fin. Forming the gate stack includes depositing a gate dielectric layer over the first semiconductor fin, depositing a first seed layer over the gate dielectric layer, depositing a second seed layer over the first seed layer, wherein the second seed layer has a different structure than the first seed layer, and depositing a conductive layer over the second seed layer, wherein the first seed layer, the second seed layer, and the conductive layer include the same conductive material. The method also includes forming source and drain regions adjacent the gate stack. | |||
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2 | US2021005743A1 |
SEMICONDUCTOR DEVICE AND MANUFACTURING PROCESS THEREOF
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Publication/Patent Number: US2021005743A1 | Publication Date: 2021-01-07 | Application Number: 17/027,549 | Filing Date: 2020-09-21 | Inventor： Kung, Pohan Lu, Ying -jing Hung, Chi-cheng Wang yu sheng Jangjian, Shiu-ko | Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. | IPC: H01L29/78 | Abstract: A method of manufacturing a semiconductor device includes: providing a substrate; forming a gate structure on the substrate; depositing a first dielectric layer over the gate structure; depositing a conductive interconnect in a trench of the first dielectric layer thereby exposing a surface of the conductive interconnect through the first dielectric layer; depositing a conductive layer over the exposed surface of the conductive interconnect; depositing a silicon-containing layer over the conductive layer and the conductive interconnect; and forming a metal silicide layer to be a silicide form of the conductive layer by reacting the conductive layer with silicon in the silicon-containing layer. | |||
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3 | US2021043521A1 |
CMOS FinFET Structures Including Work-Function Materials Having Different Proportions of Crystalline Orientations and Methods of Forming the Same
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Publication/Patent Number: US2021043521A1 | Publication Date: 2021-02-11 | Application Number: 17/068,041 | Filing Date: 2020-10-12 | Inventor： Chiu, Ya-wen Lee, Da-yuan Lee, Hsien-ming Yang, Kai-cyuan Wang yu sheng Fan, Chih-hsiang Kuok, Kun-wa | Assignee: Taiwan Semiconductor Manufacturing Co., Ltd. | IPC: H01L21/8238 | Abstract: A method includes forming a first transistor, which includes forming a first gate dielectric layer over a first channel region in a substrate and forming a first work-function layer over the first gate dielectric layer, wherein forming the first work-function layer includes depositing a work-function material using first process conditions to form the work-function material having a first proportion of different crystalline orientations and forming a second transistor, which includes forming a second gate dielectric layer over a second channel region in the substrate and forming a second work-function layer over the second gate dielectric layer, wherein forming the second work-function layer includes depositing the work-function material using second process conditions to form the work-function material having a second proportion of different crystalline orientations. | |||
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4 | US2020119152A1 |
Low Resistant Contact Method and Structure
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Publication/Patent Number: US2020119152A1 | Publication Date: 2020-04-16 | Application Number: 16/715,927 | Filing Date: 2019-12-16 | Inventor： Wang yu sheng Lin, Yu-ting | Assignee: Taiwan Semiconductor Manufacturing Company, Ltd. | IPC: H01L29/417 | Abstract: A device includes a metal-silicide region formed in a semiconductor material in a contact opening. A concentration of a material, including chlorine, fluorine, or a combination thereof is in the metal-silicide region near an uppermost surface of the metal-silicide region. The presence of chlorine or fluorine results from a physical bombarding of the chlorine or fluorine in the contact opening. As a result of the physical bombard, the opening becomes wider at the bottom of the opening and the sidewalls of the opening are thinned. A capping layer is over the metal-silicide region and over sidewalls of a contact plug opening. A contact plug is formed over the capping layer, filling the contact plug opening. Before the contact plug is formed, a silicidation occurs to form the metal-silicide and the metal-silicide is wider than the bottom of the opening. | |||
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5 | US10755938B2 |
Metal gate and manufacturing method thereof
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Publication/Patent Number: US10755938B2 | Publication Date: 2020-08-25 | Application Number: 15/996,789 | Filing Date: 2018-06-04 | Inventor： Hung, Chi-cheng Wang yu sheng Su, Ting-siang Su, Ching-hwanq | Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. | IPC: H01L21/285 | Abstract: The present disclosure provides a semiconductor structure, including an active region with a first surface; an isolated region having a second surface, surrounding the active region, the first surface being higher than the second surface; and a metal gate having a plurality of metal layers disposed over the first surface and the second surface. A ratio of a thinnest portion and a thickest portion of at least one of the plurality of metal layers is greater than about 40%. | |||
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6 | US2020091315A1 |
Semiconductor Device and Methods of Manufacture
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Publication/Patent Number: US2020091315A1 | Publication Date: 2020-03-19 | Application Number: 16/690,455 | Filing Date: 2019-11-21 | Inventor： Wang yu sheng Hung, Chi-cheng Lee, Chia-ching Su, Ching-hwanq | Assignee: Taiwan Semiconductor Manufacturing Company, Ltd. | IPC: H01L29/66 | Abstract: A semiconductor device and method of manufacturing are provided. In an embodiment a first nucleation layer is formed within an opening for a gate-last process. The first nucleation layer is treated in order to remove undesired oxygen by exposing the first nucleation layer to a precursor that reacts with the oxygen to form a gas. A second nucleation layer is then formed, and a remainder of the opening is filled with a bulk conductive material. | |||
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7 | US10714576B2 |
Semiconductor device and method for manufacturing the same
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Publication/Patent Number: US10714576B2 | Publication Date: 2020-07-14 | Application Number: 15/954,458 | Filing Date: 2018-04-16 | Inventor： Hung, Chi-cheng Chen, Kei-wei Wang yu sheng Chung, Ming-ching Wu, Chia-yang | Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. | IPC: H01L21/768 | Abstract: A device includes an epitaxy structure having a recess therein, a dielectric layer over the epitaxy structure, the dielectric layer having a contact hole communicating with the recess, a dielectric spacer liner (DSL) layer on a sidewall of the recess, a barrier layer on the DSL layer, and a conductor. The DSL layer has an opening. The DSL layer extends further into the epitaxy structure than the barrier layer. The conductor is disposed in the contact hole and electrically connected to the epitaxy feature through the opening of the DSL layer. | |||
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8 | US2020075765A1 |
FinFET Structures and Methods of Forming the Same
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Publication/Patent Number: US2020075765A1 | Publication Date: 2020-03-05 | Application Number: 16/675,306 | Filing Date: 2019-11-06 | Inventor： Wang yu sheng Hung, Chi-cheng Lee, Chia-ching Wu, Chung-chiang Su, Ching-hwanq | Assignee: Taiwan Semiconductor Manufacturing Company, Ltd. | IPC: H01L29/78 | Abstract: A method includes forming a first semiconductor fin protruding from a substrate and forming a gate stack over the first semiconductor fin. Forming the gate stack includes depositing a gate dielectric layer over the first semiconductor fin, depositing a first seed layer over the gate dielectric layer, depositing a second seed layer over the first seed layer, wherein the second seed layer has a different structure than the first seed layer, and depositing a conductive layer over the second seed layer, wherein the first seed layer, the second seed layer, and the conductive layer include the same conductive material. The method also includes forming source and drain regions adjacent the gate stack. | |||
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9 | US2020343349A1 |
SEMICONDUCTOR DEVICE WITH DIELECTRIC SPACER LINER ON SOURCE/DRAIN CONTACT
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Publication/Patent Number: US2020343349A1 | Publication Date: 2020-10-29 | Application Number: 16/926,671 | Filing Date: 2020-07-11 | Inventor： Hung, Chi-cheng Chen, Kei-wei Wang yu sheng Chung, Ming-ching Wu, Chia-yang | Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. | IPC: H01L29/417 | Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a first source/drain region, a second source/drain region, first source/drain contact and a first dielectric spacer liner. The gate structure is over the semiconductor substrate. The first source/drain region and the second source/drain region are in the semiconductor substrate and respectively on opposite sides of the gate structure. The first source/drain contact is over the first source/drain region. The first dielectric spacer liner lines a sidewall of the first source/drain contact and extends into the first source/drain region. | |||
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10 | US10840184B2 |
Formation of copper layer structure with self anneal strain improvement
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Publication/Patent Number: US10840184B2 | Publication Date: 2020-11-17 | Application Number: 15/870,810 | Filing Date: 2018-01-12 | Inventor： Nian, Jun-nan Jangjian, Shiu-ko Hung, Chi-cheng Wang yu sheng Chen, Hung-hsu | Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. | IPC: B32B15/01 | Abstract: In a method for manufacturing an interconnect structure, a dielectric layer is removed to form a first recess and a second recess. The first recess is below the second recess. A first metal layer is deposited to fill the first recess and a first portion of the second recess. A carbon-containing layer is deposited over the first metal layer to fill a second portion of the second recess, which is over the first portion. A second metal layer is deposited over the carbon-containing layer to fill a third portion of the second recess, which is over the second portion. A carbon concentration of the carbon-containing layer is greater than a carbon concentration of the first metal layer and a carbon concentration of the second metal layer, and the carbon concentration of the first metal layer is substantially the same as the carbon concentration of the second metal layer. | |||
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11 | US10833196B2 |
FinFET structures and methods of forming the same
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Publication/Patent Number: US10833196B2 | Publication Date: 2020-11-10 | Application Number: 16/675,306 | Filing Date: 2019-11-06 | Inventor： Wang yu sheng Hung, Chi-cheng Lee, Chia-ching Wu, Chung-chiang Su, Ching-hwanq | Assignee: Taiwan Semiconductor Manufacturing Company, Ltd. | IPC: H01L29/78 | Abstract: A method includes forming a first semiconductor fin protruding from a substrate and forming a gate stack over the first semiconductor fin. Forming the gate stack includes depositing a gate dielectric layer over the first semiconductor fin, depositing a first seed layer over the gate dielectric layer, depositing a second seed layer over the first seed layer, wherein the second seed layer has a different structure than the first seed layer, and depositing a conductive layer over the second seed layer, wherein the first seed layer, the second seed layer, and the conductive layer include the same conductive material. The method also includes forming source and drain regions adjacent the gate stack. | |||
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12 | US10840330B2 |
Block layer in the metal gate of MOS devices
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Publication/Patent Number: US10840330B2 | Publication Date: 2020-11-17 | Application Number: 15/656,460 | Filing Date: 2017-07-21 | Inventor： Tsao, Jung-chih Hung, Chi-cheng Wang yu sheng Lee, Wen-hsi Chen, Kei-wei Wang, Ying-lang | Assignee: Taiwan Semiconductor Manufacturing Company, Ltd. | IPC: H01L27/146 | Abstract: A method includes method includes forming a dummy gate stack over a semiconductor substrate, wherein the semiconductor substrate is comprised in a wafer, removing the dummy gate stack to form a recess, forming a gate dielectric layer in the recess, and forming a metal layer in the recess and over the gate dielectric layer. The metal layer has an n-work function. A block layer is deposited over the metal layer using Atomic Layer Deposition (ALD). The remaining portion of the recess is filled with metallic materials, wherein the metallic materials are overlying the metal layer. | |||
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13 | US202043781A1 |
Semiconductor Device and Method
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Publication/Patent Number: US202043781A1 | Publication Date: 2020-02-06 | Application Number: 20/191,659 | Filing Date: 2019-10-11 | Inventor： Tsai, Ming-hsing Wang yu sheng Hung, Chi-cheng Su, Ching-hwanq Lin, Yu-ting Ou, Yang Liang-yueh | Assignee: Taiwan Semiconductor Manufacturing Company, Ltd. | IPC: H01L29/66 | Abstract: A method includes forming a first opening in a dielectric layer over a substrate, lining sidewalls and a bottom of the first opening with a conductive barrier layer, and depositing a seed layer over the conductive barrier layer. The method further includes treating the seed layer with a plasma process, and filling the first opening with a conductive material after the treating the seed layer. | |||
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14 | US10867845B2 |
Semiconductor device and method
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Publication/Patent Number: US10867845B2 | Publication Date: 2020-12-15 | Application Number: 16/599,940 | Filing Date: 2019-10-11 | Inventor： Wang yu sheng Hung, Chi-cheng Su, Ching-hwanq Ou, Yang Liang-yueh Tsai, Ming-hsing Lin, Yu-ting | Assignee: Taiwan Semiconductor Manufacturing Company, Ltd. | IPC: H01L21/768 | Abstract: A method includes forming a first opening in a dielectric layer over a substrate, lining sidewalls and a bottom of the first opening with a conductive barrier layer, and depositing a seed layer over the conductive barrier layer. The method further includes treating the seed layer with a plasma process, and filling the first opening with a conductive material after the treating the seed layer. | |||
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15 | US10879629B2 |
Method of electroplating metal into recessed feature and electroplating layer in recessed feature
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Publication/Patent Number: US10879629B2 | Publication Date: 2020-12-29 | Application Number: 16/205,286 | Filing Date: 2018-11-30 | Inventor： Nian, Jun-nan Wu, Jyun-ru Jangjian, Shiu-ko Peng, Yu-ren Hung, Chi-cheng Wang yu sheng | Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED | IPC: C25D5/16 | Abstract: A method of electroplating a metal into a recessed feature is provided, which includes: contacting a surface of the recessed feature with an electroplating solution comprising metal ions, an accelerator additive, a suppressor additive and a leveler additive, in which the recessed feature has at least two elongated regions and a cross region laterally between the two elongated regions, and a molar concentration ratio of the accelerator additive:the suppressor additive:the leveler additive is (8-15):(1.5-3):(0.5-2); and electroplating the metal to form an electroplating layer in the recessed feature. An electroplating layer in a recessed feature is also provided. | |||
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16 | US2020105519A1 |
PRE-CLEAN FOR CONTACTS
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Publication/Patent Number: US2020105519A1 | Publication Date: 2020-04-02 | Application Number: 16/146,529 | Filing Date: 2018-09-28 | Inventor： Lin, Yu-ting Kao, Chen-yuan Lin, Rueijer Wang yu sheng Chen, I-li Wu, Hong-ming | Assignee: Taiwan Semiconductor Manufacturing Co., Ltd. | IPC: H01L21/02 | Abstract: The present disclosure describes a method that includes forming a dielectric layer over a contact region on a substrate; etching the dielectric layer to form a contact opening to expose the contact region; and pre-cleaning the exposed contact region to remove a residual material formed by the etching. During the pre-cleaning, the first contact region is exposed to an inductively coupled radio frequency (RF) plasma. Also, during the pre-cleaning, a direct current power supply unit (DC PSU) provides a bias voltage to the substrate and a magnetic field is applied to the inductively coupled RF plasma to collimate ions. | |||
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17 | US2020075407A1 |
Methods for Forming Contact Plugs with Reduced Corrosion
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Publication/Patent Number: US2020075407A1 | Publication Date: 2020-03-05 | Application Number: 16/678,410 | Filing Date: 2019-11-08 | Inventor： Wang yu sheng Hung, Chi-cheng Kao, Chen-yuan Chiu, Yi-wei Ou, Yang Liang-yueh Pai, Yueh-ching | Assignee: Taiwan Semiconductor Manufacturing Company, Ltd. | IPC: H01L21/768 | Abstract: A method includes forming an ILD to cover a gate stack of a transistor. The ILD and the gate stack are parts of a wafer. The ILD is etched to form a contact opening, and a source/drain region of the transistor or a gate electrode in the gate stack is exposed through the contact opening. A conductive capping layer is formed to extend into the contact opening. A metal-containing material is plated on the conductive capping layer in a plating solution using electrochemical plating. The metal-containing material has a portion filling the contact opening. The plating solution has a sulfur content lower than about 100 ppm. A planarization is performed on the wafer to remove excess portions of the metal-containing material. A remaining portion of the metal-containing material and a remaining portion of the conductive capping layer in combination form a contact plug. | |||
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18 | US10714329B2 |
Pre-clean for contacts
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Publication/Patent Number: US10714329B2 | Publication Date: 2020-07-14 | Application Number: 16/146,529 | Filing Date: 2018-09-28 | Inventor： Lin, Yu-ting Kao, Chen-yuan Lin, Rueijer Wang yu sheng Chen, I-li Wu, Hong-ming | Assignee: Taiwan Semiconductor Manufacturing Co., Ltd. | IPC: H01L21/4763 | Abstract: The present disclosure describes a method that includes forming a dielectric layer over a contact region on a substrate; etching the dielectric layer to form a contact opening to expose the contact region; and pre-cleaning the exposed contact region to remove a residual material formed by the etching. During the pre-cleaning, the first contact region is exposed to an inductively coupled radio frequency (RF) plasma. Also, during the pre-cleaning, a direct current power supply unit (DC PSU) provides a bias voltage to the substrate and a magnetic field is applied to the inductively coupled RF plasma to collimate ions. | |||
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19 | US2020343087A1 |
Pre-Clean for Contacts
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Publication/Patent Number: US2020343087A1 | Publication Date: 2020-10-29 | Application Number: 16/927,638 | Filing Date: 2020-07-13 | Inventor： Lin, Yu-ting Kao, Chen-yuan Lin, Rueijer Wang yu sheng Chen, I-li Wu, Hong-ming | Assignee: Taiwan Semiconductor Manufacturing Co., Ltd. | IPC: H01L21/02 | Abstract: The present disclosure describes a method that includes forming a dielectric layer over a contact region on a substrate; etching the dielectric layer to form a contact opening to expose the contact region; and pre-cleaning the exposed contact region to remove a residual material formed by the etching. During the pre-cleaning, the contact region is exposed to an inductively coupled radio frequency (RF) plasma. Also, during the pre-cleaning, a direct current power supply unit (DC PSU) provides a bias voltage to the substrate and a magnetic field is applied to the inductively coupled RF plasma to collimate ions. | |||
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20 | US10749278B2 |
Method of electroplating metal into recessed feature and electroplating layer in recessed feature
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Publication/Patent Number: US10749278B2 | Publication Date: 2020-08-18 | Application Number: 15/132,099 | Filing Date: 2016-04-18 | Inventor： Nian, Jun-nan Wu, Jyun-ru Jangjian, Shiu-ko Peng, Yu-ren Hung, Chi-cheng Wang yu sheng | Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. | IPC: C25D7/12 | Abstract: A method of electroplating a metal into a recessed feature is provided, which includes: contacting a surface of the recessed feature with an electroplating solution comprising metal ions, an accelerator additive, a suppressor additive and a leveler additive, in which the recessed feature has at least two elongated regions and a cross region laterally between the two elongated regions, and a molar concentration ratio of the accelerator additive: the suppressor additive: the leveler additive is (8-15):(1.5-3):(0.5-2); and electroplating the metal to form an electroplating layer in the recessed feature. An electroplating layer in a recessed feature is also provided. |
3.Current Quota