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1 | US2020395242A1 |
SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF
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Publication/Patent Number: US2020395242A1 | Publication Date: 2020-12-17 | Application Number: 16/439,690 | Filing Date: 2019-06-12 | Inventor： Shih, Shing-yih Wang, Mao-ying Wu hung mo | Assignee: NANYA TECHNOLOGY CORPORATION | IPC: H01L21/768 | Abstract: A method of forming a semiconductor structure includes the following steps. A dielectric layer is formed over a conductive line. A photoresist layer is formed over the dielectric layer. The photoresist layer is patterned to form a mask feature and an opening is defined by the mask feature. The opening has a bottom portion and a top portion communicated to the bottom portion, and the top portion is wider than the bottom portion. The dielectric layer is etched to form a via hole in the dielectric layer using the mask feature as an etch mask, such that the via hole has a bottom portion and a tapered portion over the bottom portion. The conductive material is filled in the via hole to form a conductive via. | |||
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2 | US2020286777A1 |
INTERCONNECT STRUCTURE AND METHOD FOR PREPARING THE SAME
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Publication/Patent Number: US2020286777A1 | Publication Date: 2020-09-10 | Application Number: 16/389,644 | Filing Date: 2019-04-19 | Inventor： Wang, Mao-ying Shih, Shing-yih Wu hung mo Ting, Yung-te Lin, Yu-ting | Assignee: NANYA TECHNOLOGY CORPORATION | IPC: H01L21/768 | Abstract: The present disclosure provides a method for preparing an interconnect structure. One aspect of the present disclosure provides a method for preparing an interconnect structure. The method includes the following steps. A first dielectric layer is provided over a first connecting line. A first upper via opening is formed in the first dielectric layer, wherein the first upper via opening has a first width. A first lower via opening is formed in the first dielectric layer, wherein the first lower via opening is formed under and coupled to the first upper via opening. The first lower via opening has a second width less than the first width of the first upper via opening. A connecting via is formed in the first upper via opening and the first lower via opening. A second connecting line is formed over the connecting via. | |||
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3 | US2020176377A1 |
ELECTRONIC DEVICE AND METHOD OF MANUFACTURING THE SAME
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Publication/Patent Number: US2020176377A1 | Publication Date: 2020-06-04 | Application Number: 16/251,858 | Filing Date: 2019-01-18 | Inventor： Lin, Yu-ting Wang, Mao-ying Shih, Shing-yih Wu hung mo Ting, Yung-te | Assignee: NANYA TECHNOLOGY CORPORATION | IPC: H01L23/522 | Abstract: The present disclosure provides an electronic device and a method of manufacturing the same. The electronic device includes a multilayer component, at least one contact pad, a passivation layer, a dielectric layer, and a metallic layer. The contact pad is disposed on the multilayer component, the passivation layer covers the multilayer component and the contact pad, and the dielectric layer is disposed on the passivation layer. The metallic layer penetrates through the dielectric layer and the passivation layer and is connected to the contact pad, and the metallic layer discretely tapers at positions of decreasing distance from the contact pad. | |||
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4 | US2020286775A1 |
INTERCONNECT STRUCTURE AND METHOD FOR PREPARING THE SAME
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Publication/Patent Number: US2020286775A1 | Publication Date: 2020-09-10 | Application Number: 16/291,376 | Filing Date: 2019-03-04 | Inventor： Wang, Mao-ying Shih, Shing-yih Wu hung mo Ting, Yung-te Lin, Yu-ting | Assignee: NANYA TECHNOLOGY CORPORATION | IPC: H01L21/768 | Abstract: The present disclosure provides an interconnect structure. The interconnect structure includes a first connecting line, a second connecting line disposed over the first connecting line, and a connecting via disposed in a dielectric structure between the first connecting line and the second connecting line, and electrically connecting the first connecting line and the second connecting line. The connecting via includes a head portion and a body portion, and a width of the head portion is greater than a width of the body portion. | |||
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5 | US9659886B2 |
Method of fabricating semiconductor device having voids between top metal layers of metal interconnects
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Publication/Patent Number: US9659886B2 | Publication Date: 2017-05-23 | Application Number: 15/193,117 | Filing Date: 2016-06-27 | Inventor： Lin, Chung-hsin Wu, Ping-heng Lay, Chao-wen Wu hung mo Chuang, Ying-cheng | Assignee: NANYA TECHNOLOGY CORPORATION | IPC: H01L23/528 | Abstract: The invention provides a semiconductor device including a substrate, a dielectric layer, a dummy bonding pad, a bonding pad, a redistribution layer, and a metal interconnect. The substrate includes a non-device region and a device region. The dielectric layer is on the non-device region and the device region. The dummy bonding pad is on the dielectric layer of the non-device region. The metal interconnect is in the dielectric layer of the non-device region and connected to the dummy bonding pad. The bonding pad is on the dielectric layer of the device region. The buffer layer is between the bonding pad and the dielectric layer. The buffer layer includes metal, metal nitride, or a combination thereof. The redistribution layer is on the dielectric layer and connects the dummy bonding pad and the bonding pad. | |||
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6 | TWI532136B |
Semiconductor device and method of fabricating the same
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Publication/Patent Number: TWI532136B | Publication Date: 2016-05-01 | Application Number: 102142675 | Filing Date: 2013-11-22 | Inventor： Wu, Hung Mo Chuang, Ying Cheng Wu, Ping Heng Lay, Chao Wen Lin, Chung Hsin | Assignee: Nanya Technology Corporation | IPC: H01L21/60 | Abstract: The invention provides a semiconductor device including a substrate | |||
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7 | US9418949B2 |
Semiconductor device having voids between top metal layers of metal interconnects
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Publication/Patent Number: US9418949B2 | Publication Date: 2016-08-16 | Application Number: 14/028,554 | Filing Date: 2013-09-17 | Inventor： Lin, Chung-hsin Wu, Ping-heng Lay, Chao-wen Wu hung mo Chuang, Ying-cheng | Assignee: NANYA TECHNOLOGY CORPORATION | IPC: H01L23/528 | Abstract: The invention provides a semiconductor device including a substrate, a dielectric layer, a dummy bonding pad, a bonding pad, a redistribution layer, and a metal interconnect. The substrate includes a non-device region and a device region. The dielectric layer is on the non-device region and the device region. The dummy bonding pad is on the dielectric layer of the non-device region. The metal interconnect is in the dielectric layer of the non-device region and connected to the dummy bonding pad. The bonding pad is on the dielectric layer of the device region. The buffer layer is between the bonding pad and the dielectric layer. The buffer layer includes metal, metal nitride, or a combination thereof. The redistribution layer is on the dielectric layer and connects the dummy bonding pad and the bonding pad. | |||
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8 | US2016307859A1 |
SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
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Publication/Patent Number: US2016307859A1 | Publication Date: 2016-10-20 | Application Number: 15/193,117 | Filing Date: 2016-06-27 | Inventor： Lin, Chung-hsin Wu, Ping-heng Lay, Chao-wen Wu hung mo Chuang, Ying-cheng | Assignee: NANYA TECHNOLOGY CORPORATION | IPC: H01L23/00 | Abstract: The invention provides a semiconductor device including a substrate, a dielectric layer, a dummy bonding pad, a bonding pad, a redistribution layer, and a metal interconnect. The substrate includes a non-device region and a device region. The dielectric layer is on the non-device region and the device region. The dummy bonding pad is on the dielectric layer of the non-device region. The metal interconnect is in the dielectric layer of the non-device region and connected to the dummy bonding pad. The bonding pad is on the dielectric layer of the device region. The buffer layer is between the bonding pad and the dielectric layer. The buffer layer includes metal, metal nitride, or a combination thereof. The redistribution layer is on the dielectric layer and connects the dummy bonding pad and the bonding pad. | |||
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9 | TW201513284A |
Semiconductor device and method of fabricating the same
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Publication/Patent Number: TW201513284A | Publication Date: 2015-04-01 | Application Number: 102142675 | Filing Date: 2013-11-22 | Inventor： Wu, Hung Mo Chuang, Ying Cheng Wu, Ping Heng Lay, Chao Wen Lin, Chung Hsin | Assignee: Nanya Technology Corporation | IPC: H01L21/60 | Abstract: The invention provides a semiconductor device including a substrate | |||
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10 | US2015076698A1 |
SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
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Publication/Patent Number: US2015076698A1 | Publication Date: 2015-03-19 | Application Number: 14/028,554 | Filing Date: 2013-09-17 | Inventor： Lin, Chung-hsin Wu, Ping-heng Lay, Chao-wen Wu hung mo Chuang, Ying-cheng | Assignee: NANYA TECHNOLOGY CORPORATION | IPC: H01L23/00 | Abstract: The invention provides a semiconductor device including a substrate, a dielectric layer, a dummy bonding pad, a bonding pad, a redistribution layer, and a metal interconnect. The substrate includes a non-device region and a device region. The dielectric layer is on the non-device region and the device region. The dummy bonding pad is on the dielectric layer of the non-device region. The metal interconnect is in the dielectric layer of the non-device region and connected to the dummy bonding pad. The bonding pad is on the dielectric layer of the device region. The buffer layer is between the bonding pad and the dielectric layer. The buffer layer includes metal, metal nitride, or a combination thereof The redistribution layer is on the dielectric layer and connects the dummy bonding pad and the bonding pad. | |||
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11 | DE10323728A1 |
Verfahren zur Verbesserung der Gleichmäßigkeit einer Fotolackschicht
Title (English):
The method of improving uniformity of varnish coating.
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Publication/Patent Number: DE10323728A1 | Publication Date: 2004-08-26 | Application Number: 10323728 | Filing Date: 2003-05-26 | Inventor： Chen, Meng Hung Wu, Hsin Ling Wu, Hung Mo Lee, Chung Yuan | Assignee: NANYA TECHNOLOGY CORPORATION, KUEISHAN | IPC: G03F7/26 | Abstract: Ein Verfahren zur Verbesserung der Gleichmäßigkeit einer Fotolackschicht und zur Herstellung einer unteren Elektrode eines Grabenkondensators. Zuerst wird ein Substrat mit einer Vielzahl von Gräben bereitgestellt. Dann wird eine Schutzfotolackschicht auf dem Substrat gebildet | |||
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12 | TW577112B |
Method of improving uniformity of photoresist layer
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Publication/Patent Number: TW577112B | Publication Date: 2004-02-21 | Application Number: 92102762 | Filing Date: 2003-02-11 | Inventor： Lee, Chung-yuan Chen, Mong-hung Wu, Hsin-ling Wu hung mo | Assignee: Nanya Technology Corporation | IPC: G03F7/26 | Abstract: A method for improving uniformity of a photoresist layer. First | |||
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13 | TW200415699A |
Method of improving uniformity of photoresist layer
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Publication/Patent Number: TW200415699A | Publication Date: 2004-08-16 | Application Number: 92102762 | Filing Date: 2003-02-11 | Inventor： Lee, Chung-yuan Chen, Mong-hung Wu, Hsin-ling Wu hung mo | Assignee: Nanya Technology Corporation | IPC: G03F7/26 | Abstract: A method for improving uniformity of a photoresist layer. First | |||
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14 | US2004157163A1 |
Method of improving photoresist layer uniformity
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Publication/Patent Number: US2004157163A1 | Publication Date: 2004-08-12 | Application Number: 10/439,371 | Filing Date: 2003-05-16 | Inventor： Chen, Meng-hung Wu, Hsin-ling Wu hung mo Lee, Chung-yuan | Assignee: Nanya Technology Corporation | IPC: G03F007/26 | Abstract: A method for improving photoresist layer uniformity and fabricating a lower electrode of a trench capacitor. First, a substrate having a plurality of trenches is provided. Next, a protective photoresist layer is formed on the substrate to fill the trenches. Parts of the protective photoresist layer are removed to form first openings in trenches. A refill photoresist layer with a planar upper surface is blanketly formed to fill the first openings. The protective photoresist and/or the refill photoresist layer are recessed to leave a plurality of second openings with substantially equal depths in each of the trenches. |
3.Current Quota