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1
US2021079522A1
Vacuum Systems in Semiconductor Fabrication Facilities
Publication/Patent Number: US2021079522A1 Publication Date: 2021-03-18 Application Number: 16/573,235 Filing Date: 2019-09-17 Inventor: Wu, Ming-fa   Ho, Wen-lung   Yang huai tei   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: C23C16/44 Abstract: Methods and devices are provided wherein rotational gas-flow is generated by vortex generators to decontaminate dirty gas (e.g., gas contaminated by solid particles) in pumping lines of vacuum systems suitable for use at a semiconductor integrated circuit fabrication facility. The vacuum systems use filterless particle decontamination units wherein rotational gas-flow is applied to separate and trap solid particles from gas prior to the gas-flow entering a vacuum pump. Methods are also described whereby solid deposits along portions of pumping lines may be dislodged and removed and portions of pumping lines may be self-cleaning.
2
US10923355B2
Methods and systems for dopant activation using microwave radiation
Publication/Patent Number: US10923355B2 Publication Date: 2021-02-16 Application Number: 16/726,438 Filing Date: 2019-12-24 Inventor: Tsai, Chun-hsiung   Yang huai tei   Yu, Kuo-feng   Chen, Kei-wei   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD   IPC: H01L21/268 Abstract: A semiconductor structure includes a substrate, a source/drain (S/D) junction, and an S/D contact. The S/D junction is associated with the substrate and includes a trench-defining wall, a semiconductor layer, and a semiconductor material. The trench-defining wall defines a trench. The semiconductor layer is formed over the trench-defining wall, partially fills the trench, substantially covers the trench-defining wall, and includes germanium. The semiconductor material is formed over the semiconductor layer and includes germanium, a percentage composition of which is greater than a percentage composition of the germanium of the semiconductor layer. The S/D contact is formed over the S/D junction.
3
US2021050433A1
SEMICONDUCTOR STRUCTURE WITH SOURCE/DRAIN STRUCTURE HAVING MODIFIED SHAPE
Publication/Patent Number: US2021050433A1 Publication Date: 2021-02-18 Application Number: 17/089,138 Filing Date: 2020-11-04 Inventor: More, Shahaji B.   Chang, Shih-chieh   Lee, Cheng-han   Yang huai tei   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.   IPC: H01L29/66 Abstract: Semiconductor structures and method for forming the same are provide. The semiconductor structure includes a fin structure protruding from a substrate and a gate structure formed across the fin structure. The semiconductor structure further includes an Arsenic-doped region formed in the fin structure and a source/drain structure formed over the Arsenic-doped region. In addition, a bottommost portion of the Arsenic-doped region is lower than a bottommost portion of the source/drain structure.
4
US10937910B2
Semiconductor structure with source/drain multi-layer structure and method for forming the same
Publication/Patent Number: US10937910B2 Publication Date: 2021-03-02 Application Number: 16/654,175 Filing Date: 2019-10-16 Inventor: Wang, Chun-chieh   Lin, Yu-ting   Pai, Yueh-ching   Chang, Shih-chieh   Yang huai tei   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD   IPC: H01L29/78 Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure formed over a fin structure and a gate spacer formed on a sidewall surface of the gate structure. The semiconductor structure also includes a first source/drain (S/D) epitaxial layer formed in the fin structure and adjacent to the gate spacer, and a second S/D epitaxial layer formed over the first S/D epitaxial layer. A top surface of the second S/D layer is higher than a top surface of the first S/D epitaxial layer.
5
US2021080823A1
Pellicle and Method of Manufacturing Same
Publication/Patent Number: US2021080823A1 Publication Date: 2021-03-18 Application Number: 16/573,850 Filing Date: 2019-09-17 Inventor: Li, Po Hsuan   Lin, Yu-ting   Lin, Yun-yue   Yang huai tei   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: G03F1/62 Abstract: A pellicle comprises a stress-controlled metal layer. The stress in said metal layer may be between about 500-50 MPa. A method of manufacturing a pellicle comprising a metal layer includes deposing said metal layer by plasma physical vapor deposition. Process parameters are selected so as to produce a desired stress value in said metal layer, such as between about 500-50 MPa.
6
US10930781B2
P-type strained channel in a fin field effect transistor (FinFET) device
Publication/Patent Number: US10930781B2 Publication Date: 2021-02-23 Application Number: 16/710,156 Filing Date: 2019-12-11 Inventor: More, Shahaji B.   Yang huai tei   Chang, Shih-chieh   Kuan, Shu   Lee, Cheng-han   Assignee: Taiwan Semiconductor Manufacturing Co. Ltd.   IPC: H01L29/78 Abstract: In certain embodiments, a semiconductor device includes a substrate having an n-doped well feature and an epitaxial silicon germanium fin formed over the n-doped well feature. The epitaxial silicon germanium fin has a lower part and an upper part. The lower part has a lower germanium content than the upper part. A channel is formed from the epitaxial silicon germanium fin. A gate is formed over the epitaxial silicon germanium fin. A doped source-drain is formed proximate the channel.
7
US10950694B2
Doping for semiconductor device with conductive feature
Publication/Patent Number: US10950694B2 Publication Date: 2021-03-16 Application Number: 16/433,374 Filing Date: 2019-06-06 Inventor: Liu, Su-hao   Chang, Huicheng   Chen, Chia-cheng   Chen, Liang-yin   Chen, Kuo-ju   Wu, Chun-hung   Liu, Chang-maio   Yang huai tei   Tan, Lun-kuang   You, Wei-ming   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L29/78 Abstract: The present disclosure relates generally to doping for conductive features in a semiconductor device. In an example, a structure includes an active region of a transistor. The active region includes a source/drain region, and the source/drain region is defined at least in part by a first dopant having a first dopant concentration. The source/drain region further includes a second dopant with a concentration profile having a consistent concentration from a surface of the source/drain region into a depth of the source/drain region. The consistent concentration is greater than the first dopant concentration. The structure further includes a conductive feature contacting the source/drain region at the surface of the source/drain region.
8
US2020303378A1
Semiconductor Device and Method
Publication/Patent Number: US2020303378A1 Publication Date: 2020-09-24 Application Number: 16/895,035 Filing Date: 2020-06-08 Inventor: Wang, Chun-chieh   Pai, Yueh-ching   Yang huai tei   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L27/092 Abstract: A semiconductor device including a cap layer and a method for forming the same are disclosed. In an embodiment, a method includes epitaxially growing a first semiconductor layer over an N-well; etching the first semiconductor layer to form a first recess; epitaxially growing a second semiconductor layer filling the first recess; etching the second semiconductor layer, the first semiconductor layer, and the N-well to form a first fin; forming a shallow trench isolation region adjacent the first fin; and forming a cap layer over the first fin, the cap layer contacting the second semiconductor layer, forming the cap layer including performing a pre-clean process to remove a native oxide from exposed surfaces of the second semiconductor layer; performing a sublimation process to produce a first precursor; and performing a deposition process wherein material from the first precursor is deposited on the second semiconductor layer to form the cap layer.
9
US2020135476A1
FinFET Device and Method of Forming
Publication/Patent Number: US2020135476A1 Publication Date: 2020-04-30 Application Number: 16/728,918 Filing Date: 2019-12-27 Inventor: Huang, Yi-min   Yang huai tei   Chang, Shih-chieh   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L21/285 Abstract: A finFET device and methods of forming are provided. The method includes etching recesses in a substrate on opposite sides of a gate stack. The method also includes epitaxially growing a source/drain region in each recess, where each of the source/drain regions includes a capping layer along a top surface of the respective source/drain region, and where a concentration of a first material in each source/drain region is highest at an interface of the capping layer and an underlying epitaxy layer. The method also includes depositing a plurality of metal layers overlying and contacting each of the source/drain regions. The method also includes performing an anneal, where after the anneal a metal silicide region is formed in each of the source/drain regions, where each metal silicide region extends through the capping layer and terminates at the interface of the capping layer and the underlying epitaxy layer.
10
US10679995B2
Semiconductor device and method
Publication/Patent Number: US10679995B2 Publication Date: 2020-06-09 Application Number: 16/276,143 Filing Date: 2019-02-14 Inventor: Wang, Chun-chieh   Pai, Yueh-ching   Yang huai tei   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L29/66 Abstract: A semiconductor device including a cap layer and a method for forming the same are disclosed. In an embodiment, a method includes epitaxially growing a first semiconductor layer over an N-well; etching the first semiconductor layer to form a first recess; epitaxially growing a second semiconductor layer filling the first recess; etching the second semiconductor layer, the first semiconductor layer, and the N-well to form a first fin; forming a shallow trench isolation region adjacent the first fin; and forming a cap layer over the first fin, the cap layer contacting the second semiconductor layer, forming the cap layer including performing a pre-clean process to remove a native oxide from exposed surfaces of the second semiconductor layer; performing a sublimation process to produce a first precursor; and performing a deposition process wherein material from the first precursor is deposited on the second semiconductor layer to form the cap layer.
11
US2020043927A1
Semiconductor Device and Method
Publication/Patent Number: US2020043927A1 Publication Date: 2020-02-06 Application Number: 16/276,143 Filing Date: 2019-02-14 Inventor: Wang, Chun-chieh   Pai, Yueh-ching   Yang huai tei   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L27/092 Abstract: A semiconductor device including a cap layer and a method for forming the same are disclosed. In an embodiment, a method includes epitaxially growing a first semiconductor layer over an N-well; etching the first semiconductor layer to form a first recess; epitaxially growing a second semiconductor layer filling the first recess; etching the second semiconductor layer, the first semiconductor layer, and the N-well to form a first fin; forming a shallow trench isolation region adjacent the first fin; and forming a cap layer over the first fin, the cap layer contacting the second semiconductor layer, forming the cap layer including performing a pre-clean process to remove a native oxide from exposed surfaces of the second semiconductor layer; performing a sublimation process to produce a first precursor; and performing a deposition process wherein material from the first precursor is deposited on the second semiconductor layer to form the cap layer.
12
US202043927A1
Semiconductor Device and Method
Publication/Patent Number: US202043927A1 Publication Date: 2020-02-06 Application Number: 20/191,627 Filing Date: 2019-02-14 Inventor: Wang, Chun-chieh   Yang huai tei   Pai, Yueh-ching   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L29/10 Abstract: A semiconductor device including a cap layer and a method for forming the same are disclosed. In an embodiment, a method includes epitaxially growing a first semiconductor layer over an N-well; etching the first semiconductor layer to form a first recess; epitaxially growing a second semiconductor layer filling the first recess; etching the second semiconductor layer, the first semiconductor layer, and the N-well to form a first fin; forming a shallow trench isolation region adjacent the first fin; and forming a cap layer over the first fin, the cap layer contacting the second semiconductor layer, forming the cap layer including performing a pre-clean process to remove a native oxide from exposed surfaces of the second semiconductor layer; performing a sublimation process to produce a first precursor; and performing a deposition process wherein material from the first precursor is deposited on the second semiconductor layer to form the cap layer.
13
US2020135468A1
Methods and Systems for Dopant Activation Using Microwave Radiation
Publication/Patent Number: US2020135468A1 Publication Date: 2020-04-30 Application Number: 16/726,438 Filing Date: 2019-12-24 Inventor: Tsai, Chun-hsiung   Yang huai tei   Yu, Kuo-feng   Chen, Kei-wei   Assignee: Taiwan Semiconductor Manufacturing Company Limited   IPC: H01L21/268 Abstract: A semiconductor structure includes a substrate, a source/drain (S/D) junction, and an S/D contact. The S/D junction is associated with the substrate and includes a trench-defining wall, a semiconductor layer, and a semiconductor material. The trench-defining wall defines a trench. The semiconductor layer is formed over the trench-defining wall, partially fills the trench, substantially covers the trench-defining wall, and includes germanium. The semiconductor material is formed over the semiconductor layer and includes germanium, a percentage composition of which is greater than a percentage composition of the germanium of the semiconductor layer. The S/D contact is formed over the S/D junction.
14
US2020126797A1
Silicon Intermixing Layer for Blocking Diffusion
Publication/Patent Number: US2020126797A1 Publication Date: 2020-04-23 Application Number: 16/290,118 Filing Date: 2019-03-01 Inventor: Wang, Chun-chieh   Huang, Kuo-jung   Pai, Yueh-ching   Yang huai tei   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L21/28 Abstract: A method of forming an integrated circuit structure includes forming a gate dielectric on a wafer, forming a work function layer over the gate dielectric, depositing a capping layer over the work function layer, soaking the capping layer in a silicon-containing gas to form a silicon-containing layer, forming a blocking layer after the silicon-containing layer is formed, and forming a metal-filling region over the blocking layer.
15
US10665717B2
Semiconductor device and FinFET device
Publication/Patent Number: US10665717B2 Publication Date: 2020-05-26 Application Number: 16/112,766 Filing Date: 2018-08-26 Inventor: Tsai, Chun Hsiung   Chan, Chien-tai   Fang, Ziwei   Chen, Kei-wei   Yang huai tei   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L29/78 Abstract: A FinFET device and a method of forming the same are disclosed. In accordance with some embodiments, a FinFET device includes a substrate having at least one fin, a gate stack across the at least one fin, a strained layer aside the gate stack and a silicide layer over the strained layer. The strained layer has a boron surface concentration greater than about 2E20 atom/cm3 within a depth range of about 0-5 nm from a surface of the strained layer.
16
US2020105532A1
High-K Metal Gate Process and Device
Publication/Patent Number: US2020105532A1 Publication Date: 2020-04-02 Application Number: 16/145,382 Filing Date: 2018-09-28 Inventor: Liao, Chien-shun   Yang huai tei   Wang, Chun-chieh   Pai, Yueh-ching   Wu, Chun-i   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L21/28 Abstract: An embodiment is a method of semiconductor processing. The method includes depositing a high-k gate dielectric layer over a semiconductor fin. A barrier layer is deposited over the high-k gate dielectric layer. A silicon passivation layer is deposited over the barrier layer. A nitrogen treatment is performed on the silicon passivation layer. A capping layer is deposited over the silicon passivation layer. The capping layer is annealed.