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1
US10886320B2
Mechanisms for forming image-sensor device with epitaxial isolation feature
Publication/Patent Number: US10886320B2 Publication Date: 2021-01-05 Application Number: 16/387,989 Filing Date: 2019-04-18 Inventor: Hsu, Wen-i   Hung, Feng-chi   Chuang, Chun-chieh   Yaung dun nian   Liu, Jen-cheng   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L27/146 Abstract: An image-sensor device includes a substrate including a pixel region and a logic region. A logic transistor is disposed in the logic region and is surrounded by a logic isolation feature. A radiation-sensing region is disposed in the pixel region of the substrate. An epitaxial pixel isolation feature is disposed in the pixel region and surrounds the radiation-sensing region. A doped region with a same doping polarity as the radiation-sensing region is located between a bottom of the radiation-sensing region and the back surface of the substrate. The epitaxial pixel isolation feature is in direct contact with the doped region. The doped region extends continuously under the pixel region and the logic region. The epitaxial pixel isolation feature is in direct contact with the doped region, and the logic isolation feature is spaced apart from the doped region.
2
US2021005649A1
SEMICONDUCTOR IMAGING DEVICE HAVING IMPROVED DARK CURRENT PERFORMANCE
Publication/Patent Number: US2021005649A1 Publication Date: 2021-01-07 Application Number: 17/022,456 Filing Date: 2020-09-16 Inventor: Takahashi, Seiji   Wang, Chen-jong   Yaung dun nian   Hung, Feng-chi   Shiu, Feng-jia   Liu, Jen-cheng   Sze, Jhy-jyi   Chang, Chun-wei   Hsu, Wei-cheng   Wu, Wei Chuang   Huang, Yimin   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L27/146 Abstract: In some embodiments, a pixel sensor is provided. The pixel sensor includes a first photodetector arranged in a semiconductor substrate. A second photodetector is arranged in the semiconductor substrate, where a first substantially straight line axis intersects a center point of the first photodetector and a center point of the second photodetector. A floating diffusion node is arranged in the semiconductor substrate at a point that is a substantially equal distance from the first photodetector and the second photodetector. A pick-up well contact region is arranged in the semiconductor substrate, where a second substantially straight line axis that is substantially perpendicular to the first substantially straight line axis intersects a center point of the floating diffusion node and a center point of the pick-up well contact region.
3
US2020176500A1
DEVICE OVER PHOTODETECTOR PIXEL SENSOR
Publication/Patent Number: US2020176500A1 Publication Date: 2020-06-04 Application Number: 16/402,633 Filing Date: 2019-05-03 Inventor: Sze, Jhy-jyi   Yaung dun nian   Kalnitsky, Alexander   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L27/146 Abstract: Various embodiments of the present application are directed towards a semiconductor-on-insulator (SOI) DoP image sensor and a method for forming the SOI DoP image sensor. In some embodiments, a semiconductor substrate comprises a floating node and a collector region. A photodetector is in the semiconductor substrate and is defined in part by a collector region. A transfer transistor is over the semiconductor substrate. The collector region and the floating node respectively define source/drain regions of the transfer transistor. A semiconductor mesa is over and spaced from the semiconductor substrate. A readout transistor is on and partially defined by the semiconductor mesa. The semiconductor mesa is between the readout transistor and the semiconductor substrate. A via extends from the floating node to a gate electrode of the readout transistor.
4
US2020075556A1
Stacked Semiconductor Structure and Method
Publication/Patent Number: US2020075556A1 Publication Date: 2020-03-05 Application Number: 16/679,598 Filing Date: 2019-11-11 Inventor: Chen, Szu-ying   Wan, Meng-hsun   Yaung dun nian   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L25/065 Abstract: A device comprises a first chip comprising a first connection pad embedded in a first dielectric layer and a first bonding pad embedded in the first dielectric layer, wherein the first bonding pad comprises a first portion and a second portion, the second portion being in contact with the first connection pad and a second chip comprising a second bonding pad embedded in a second dielectric layer of the second chip, wherein the first chip and the second chip are face-to-face bonded together through the first bonding pad the second bonding pad.
5
US202043967A1
METHOD FOR FORMING SEMICONDUCTOR IMAGE SENSOR
Publication/Patent Number: US202043967A1 Publication Date: 2020-02-06 Application Number: 20/191,659 Filing Date: 2019-10-08 Inventor: Yaung dun nian   Huang, Yimin   Sze, Jhy-jyi   Assignee: Taiwan Semiconductor Manufacturing Company Ltd.   IPC: H01L27/146 Abstract: A method for forming a semiconductor image sensor includes: providing a first substrate including a first front side and a first back side opposite to the first front side, and the first substrate including a plurality of first sensing devices; bonding the first substrate to a second substrate including a second front side and a second back side opposite to the second front side with the first front side of the first substrate facing the second front side of the second substrate; disposing an insulating structure over the first back side of the first substrate, wherein the insulating structure includes a plurality of dielectric grating patterns; and bonding the first substrate to a third substrate including a third front side and a third back opposite to the third front side, and the third substrate including a plurality of second sensing devices.
6
US10868071B2
Method for forming semiconductor image sensor
Publication/Patent Number: US10868071B2 Publication Date: 2020-12-15 Application Number: 16/596,592 Filing Date: 2019-10-08 Inventor: Sze, Jhy-jyi   Huang, Yimin   Yaung dun nian   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.   IPC: H01L27/146 Abstract: A method for forming a semiconductor image sensor includes: providing a first substrate including a first front side and a first back side opposite to the first front side, and the first substrate including a plurality of first sensing devices; bonding the first substrate to a second substrate including a second front side and a second back side opposite to the second front side with the first front side of the first substrate facing the second front side of the second substrate; disposing an insulating structure over the first back side of the first substrate, wherein the insulating structure includes a plurality of dielectric grating patterns; and bonding the first substrate to a third substrate including a third front side and a third back opposite to the third front side, and the third substrate including a plurality of second sensing devices.
7
US2020043967A1
METHOD FOR FORMING SEMICONDUCTOR IMAGE SENSOR
Publication/Patent Number: US2020043967A1 Publication Date: 2020-02-06 Application Number: 16/596,592 Filing Date: 2019-10-08 Inventor: Sze, Jhy-jyi   Huang, Yimin   Yaung dun nian   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.   IPC: H01L27/146 Abstract: A method for forming a semiconductor image sensor includes: providing a first substrate including a first front side and a first back side opposite to the first front side, and the first substrate including a plurality of first sensing devices; bonding the first substrate to a second substrate including a second front side and a second back side opposite to the second front side with the first front side of the first substrate facing the second front side of the second substrate; disposing an insulating structure over the first back side of the first substrate, wherein the insulating structure includes a plurality of dielectric grating patterns; and bonding the first substrate to a third substrate including a third front side and a third back opposite to the third front side, and the third substrate including a plurality of second sensing devices.
8
US10790327B2
Semiconductor device structure with a conductive feature passing through a passivation layer
Publication/Patent Number: US10790327B2 Publication Date: 2020-09-29 Application Number: 16/861,453 Filing Date: 2020-04-29 Inventor: Kao, Min-feng   Yaung dun nian   Liu, Jen-cheng   Huang, Hsun-ying   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L21/00 Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first semiconductor die, and a second semiconductor die bonded on the first semiconductor die. A through-substrate via penetrates through a semiconductor substrate of the second semiconductor die. A passivation layer is disposed between the first semiconductor die and the second semiconductor die, wherein the passivation layer is directly bonded to the semiconductor substrate of the second semiconductor die. A conductive feature passes through the passivation layer, wherein the conductive feature is bonded to the through-substrate via. A barrier layer is disposed between the conductive feature and the passivation layer. The barrier layer covers sidewalls of the conductive feature and separates the surface of the conductive feature from a nearest neighboring surface of the first or second semiconductor die.
9
US10566374B2
Via support structure under pad areas for BSI bondability improvement
Publication/Patent Number: US10566374B2 Publication Date: 2020-02-18 Application Number: 16/167,844 Filing Date: 2018-10-23 Inventor: Huang, Sin-yao   Wang, Ching-chun   Yaung dun nian   Hung, Feng-chi   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L27/146 Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a substrate and a first interconnect wire arranged within a dielectric structure on the substrate. A bond pad contacts the first interconnect wire. A via support structure has one or more vias arranged within the dielectric structure at a location separated from the substrate by the first interconnect wire, The via support structure has a metal pattern density that is greater than or equal to approximately 19% and that is configured to mitigate damage caused by a force of a bonding process on the bond pad.
10
US2020258931A1
SEMICONDUCTOR DEVICE STRUCTURE WITH A CONDUCTIVE FEATURE PASSING THROUGH A PASSIVATION LAYER
Publication/Patent Number: US2020258931A1 Publication Date: 2020-08-13 Application Number: 16/861,453 Filing Date: 2020-04-29 Inventor: Kao, Min-feng   Yaung dun nian   Liu, Jen-cheng   Huang, Hsun-ying   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L27/146 Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first semiconductor die, and a second semiconductor die bonded on the first semiconductor die. A through-substrate via penetrates through a semiconductor substrate of the second semiconductor die. A passivation layer is disposed between the first semiconductor die and the second semiconductor die, wherein the passivation layer is directly bonded to the semiconductor substrate of the second semiconductor die. A conductive feature passes through the passivation layer, wherein the conductive feature is bonded to the through-substrate via. A barrier layer is disposed between the conductive feature and the passivation layer. The barrier layer covers sidewalls of the conductive feature and separates the surface of the conductive feature from a nearest neighboring surface of the first or second semiconductor die.
11
US2020135794A1
VIA SUPPORT STRUCTURE UNDER PAD AREAS FOR BSI BONDABILITY IMPROVEMENT
Publication/Patent Number: US2020135794A1 Publication Date: 2020-04-30 Application Number: 16/732,646 Filing Date: 2020-01-02 Inventor: Huang, Sin-yao   Wang, Ching-chun   Yaung dun nian   Hung, Feng-chi   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L27/146 Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first interconnect wire disposed within a dielectric structure on a substrate. A bond pad has a lower surface contacting the first interconnect wire. A via layer is vertically between the first interconnect wire and a second interconnect wire within the dielectric structure. The via layer includes a plurality of support vias having a first size and a plurality of additional vias having a second size that is smaller than the first size. The plurality of support vias extend from directly under the lower surface of the bond pad to laterally past outermost edges of the lower surface of the bond pad.
12
US10672819B2
Mechanisms for forming image-sensor device with deep-trench isolation structure
Publication/Patent Number: US10672819B2 Publication Date: 2020-06-02 Application Number: 16/193,159 Filing Date: 2018-11-16 Inventor: Lin, Jeng-shyan   Yaung dun nian   Liu, Jen-cheng   Hung, Feng-chi   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L27/146 Abstract: An image-sensor device is provided. The image-sensor device includes a substrate having a front side and a back side. The image-sensor device also includes a radiation-sensing region operable to detect incident radiation that enters the substrate through the back side. The image-sensor device further includes a deep-trench isolation structure extending from the back side towards the front side. The deep-trench isolation structure includes a dielectric layer, and the dielectric layer contains hafnium or aluminum.
13
US10566288B2
Structure for standard logic performance improvement having a back-side through-substrate-via
Publication/Patent Number: US10566288B2 Publication Date: 2020-02-18 Application Number: 16/176,547 Filing Date: 2018-10-31 Inventor: Kao, Min-feng   Yaung dun nian   Liu, Jen-cheng   Huang, Hsun-ying   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L23/538 Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a plurality of interconnect layers within an inter-level dielectric (ILD) structure disposed along a front-side of a substrate. A dielectric layer is arranged along a back-side of the substrate and a conductive bond pad is separated from the substrate by the dielectric layer. A back-side through-substrate-via (BTSV) extends through the substrate and the dielectric layer. A conductive bump is arranged over the conductive bond pad. The conductive bond pad has a substantially planar lower surface extending from over the BTSV to below the conductive bump. A BTSV liner separates sidewalls of the BTSV from the substrate. The sidewalls of the BTSV directly contact sides of both the BTSV liner and the dielectric layer.
14
US10680027B2
Stacked semiconductor dies with a conductive feature passing through a passivation layer
Publication/Patent Number: US10680027B2 Publication Date: 2020-06-09 Application Number: 16/395,803 Filing Date: 2019-04-26 Inventor: Kao, Min-feng   Yaung dun nian   Liu, Jen-cheng   Huang, Hsun-ying   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L31/062 Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first semiconductor die, and a second semiconductor die bonded on the first semiconductor die. A through-substrate via penetrates through a semiconductor substrate of the second semiconductor die. A passivation layer is disposed between the first semiconductor die and the second semiconductor die, wherein the passivation layer is directly bonded to the semiconductor substrate of the second semiconductor die. A conductive feature passes through the passivation layer, wherein the conductive feature is bonded to the through-substrate via. A barrier layer is disposed between the conductive feature and the passivation layer. The barrier layer covers sidewalls of the conductive feature and separates the surface of the conductive feature from a nearest neighboring surface of the first or second semiconductor die.
15
US2020411636A1
BACKSIDE CAPACITOR TECHNIQUES
Publication/Patent Number: US2020411636A1 Publication Date: 2020-12-31 Application Number: 16/853,927 Filing Date: 2020-04-21 Inventor: Kao, Min-feng   Yaung dun nian   Lin, Hsing-chih   Liu, Jen-cheng   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L49/02 Abstract: Some embodiments relate to a semiconductor structure including a semiconductor substrate having a frontside surface and a backside surface. An interconnect structure is disposed over the frontside surface. The interconnect structure includes a plurality of metal lines and vias that operably couple semiconductor transistor devices disposed in or on the frontside surface of the semiconductor substrate to one another. A trench is disposed in the backside surface of the semiconductor substrate. The trench is filled with an inner capacitor electrode, a capacitor dielectric layer overlying the inner capacitor electrode, and an outer capacitor electrode overlying the capacitor dielectric layer.
16
US2020303429A1
MECHANISMS FOR FORMING IMAGE-SENSOR DEVICE WITH DEEP-TRENCH ISOLATION STRUCTURE
Publication/Patent Number: US2020303429A1 Publication Date: 2020-09-24 Application Number: 16/889,161 Filing Date: 2020-06-01 Inventor: Lin, Jeng-shyan   Yaung dun nian   Liu, Jen-cheng   Hung, Feng-chi   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.   IPC: H01L27/146 Abstract: An image-sensor device is provided. The image-sensor device includes a semiconductor substrate and a radiation-sensing region in the semiconductor substrate. The image-sensor device also includes a doped isolation region in the semiconductor substrate and a dielectric film extending into the doped isolation region from a surface of the semiconductor substrate. A portion of the doped isolation region is between the dielectric film and the radiation-sensing region.
17
US2020161244A1
STRUCTURE FOR STANDARD LOGIC PERFORMANCE IMPROVEMENT HAVING A BACK-SIDE THROUGH-SUBSTRATE-VIA
Publication/Patent Number: US2020161244A1 Publication Date: 2020-05-21 Application Number: 16/710,271 Filing Date: 2019-12-11 Inventor: Kao, Min-feng   Yaung dun nian   Liu, Jen-cheng   Huang, Hsun-ying   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L23/538 Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a first plurality of interconnect layers within a first inter-level dielectric (ILD) structure disposed along a front-side of a first substrate. A conductive pad is arranged along a back-side of the first substrate and a first through-substrate-via (TSV) extends between an interconnect wire of the first plurality of interconnect layers and the conductive pad. A second plurality of interconnect layers are within a second ILD structure disposed along a front-side of a second substrate that is bonded to the first substrate. A second through substrate via (TSV) extends through the second substrate. The second TSV has a greater width than the first TSV.
18
US2020144244A1
SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
Publication/Patent Number: US2020144244A1 Publication Date: 2020-05-07 Application Number: 16/727,925 Filing Date: 2019-12-27 Inventor: Ho, Cheng-ying   Wang, Wen-de   Liu, Jen-cheng   Yaung dun nian   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.   IPC: H01L25/00 Abstract: A semiconductor device structure includes a first chip, second chip, a first metal structure, a second metal structure, a first via structure and a second via structure. The first chip includes n inter metal dielectric (IMD) layer, which includes different materials adjacent to generate a number of staggered portions having a zigzag configuration. The second chip bonded to the first chip generates a bonding interface. The first metal structure is disposed in the first chip and between the staggered portions and the bonding interface. The first via structure in the first chip stops at the first metal structure. The first via structure includes a first via metal and a first via dielectric layer. A surface roughness of the staggered portions is substantially greater than a surface roughness of the first via dielectric layer. The second via structure extends from the first via structure to the second metal structure.
19
US2020395398A1
SEMICONDUCTOR DEVICE STRUCTURE WITH A CONDUCTIVE FEATURE PASSING THROUGH A PASSIVATION LAYER
Publication/Patent Number: US2020395398A1 Publication Date: 2020-12-17 Application Number: 17/005,582 Filing Date: 2020-08-28 Inventor: Kao, Min-feng   Yaung dun nian   Liu, Jen-cheng   Huang, Hsun-ying   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L27/146 Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first semiconductor die, and a second semiconductor die bonded on the first semiconductor die. A through-substrate via penetrates through a semiconductor substrate of the second semiconductor die. A passivation layer is disposed between the first semiconductor die and the second semiconductor die, wherein the passivation layer is directly bonded to the semiconductor substrate of the second semiconductor die. A conductive feature passes through the passivation layer, wherein the conductive feature is bonded to the through-substrate via. A barrier layer is disposed between the conductive feature and the passivation layer. The barrier layer covers sidewalls of the conductive feature and separates the surface of the conductive feature from a nearest neighboring surface of the first or second semiconductor die.
20
US10692914B2
Implant damage free image sensor and method of the same
Publication/Patent Number: US10692914B2 Publication Date: 2020-06-23 Application Number: 16/241,582 Filing Date: 2019-01-07 Inventor: Kalnitsky, Alexander   Sze, Jhy-jyi   Yaung dun nian   Wang, Chen-jong   Huang, Yimin   Yamashita, Yuichiro   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.   IPC: H01L27/146 Abstract: An image sensor is disclosed. The image sensor includes an epitaxial layer, a plurality of plug structures and an interconnect structure. Wherein the plurality of plug structures are formed in the epitaxial layer, and each plug structure has doped sidewalls, the epitaxial layer and the doped sidewalls form a plurality of photodiodes, the plurality of plug structures are used to separate adjacent photodiodes, and the epitaxial layer and the doped sidewalls are coupled to the interconnect structure via the plug structures. An associated method of fabricating the image sensor is also disclosed. The method includes: providing a substrate having a first-type doped epitaxial substrate layer on a second-type doped epitaxial substrate layer; forming a plurality of isolation trenches in the first-type doped epitaxial substrate layer; forming a second-type doped region along sidewalls and bottoms of the plurality of isolation trenches; and filling the plurality of isolation trenches by depositing metal.