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1
US2021066363A1
IMAGING DEVICE
Publication/Patent Number: US2021066363A1 Publication Date: 2021-03-04 Application Number: 17/098,963 Filing Date: 2020-11-16 Inventor: Chou, Kuo-yu   Yeh shang fu   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.   IPC: H01L27/146 Abstract: An integrated circuit includes a comparator, a counter and a control circuit. The comparator is configured to generate a comparator output signal in response to a pixel output signal and a reference signal. The counter is coupled to the comparator, and configured to be enabled or disabled in response to the comparator output signal. The control circuit is coupled to the comparator, and configured to enable or disable the comparator by a first enable signal. The first enable signal is generated in response to at least the comparator output signal.
2
US2021084247A1
CMOS IMAGE SENSOR AND METHOD OF OPERATING PIXEL ARRAY BY CMOS IMAGE SENSOR
Publication/Patent Number: US2021084247A1 Publication Date: 2021-03-18 Application Number: 16/571,217 Filing Date: 2019-09-16 Inventor: Yin, Chin   Chou, Po-sheng   Yeh shang fu   Chao, Calvin Yi-ping   Lee, Chih-lin   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H04N5/378 Abstract: A CMOS image sensor, and a method of operating a pixel array by a CMOS image sensor is provided. The CMOS image sensor includes a sensor, and a readout circuit. The sensor is configured to generate a first voltage signal and a first reset signal. The readout circuit is configured to perform a first readout operation by reading out the first reset signal and the first voltage signal simultaneously at a first predetermined time. After the first readout operation, the readout circuit turns on a plurality of switches to obtain a common-mode signal by making the first reset signal equal to the first voltage signal and re-perform a second readout operation by reading out the common-mode signal at a second predetermined time. The first predetermined time and the second predetermined time do not overlap each other.
3
US11006064B2
CMOS image sensor and method of operating pixel array by CMOS image sensor
Publication/Patent Number: US11006064B2 Publication Date: 2021-05-11 Application Number: 16/571,217 Filing Date: 2019-09-16 Inventor: Yin, Chin   Chou, Po-sheng   Yeh shang fu   Chao, Calvin Yi-ping   Lee, Chih-lin   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H04N5/357 Abstract: A CMOS image sensor, and a method of operating a pixel array by a CMOS image sensor is provided. The CMOS image sensor includes a sensor, and a readout circuit. The sensor is configured to generate a first voltage signal and a first reset signal. The readout circuit is configured to perform a first readout operation by reading out the first reset signal and the first voltage signal simultaneously at a first predetermined time. After the first readout operation, the readout circuit turns on a plurality of switches to obtain a common-mode signal by making the first reset signal equal to the first voltage signal and re-perform a second readout operation by reading out the common-mode signal at a second predetermined time. The first predetermined time and the second predetermined time do not overlap each other.
4
US10840281B2
Imaging device
Publication/Patent Number: US10840281B2 Publication Date: 2020-11-17 Application Number: 14/963,160 Filing Date: 2015-12-08 Inventor: Chou, Kuo-yu   Yeh shang fu   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.   IPC: H01L27/146 Abstract: A device that includes an analog-to-digital converter circuit and a control circuit is disclosed. The analog-to-digital converter circuit converts at least one of analog pixel output signals from a pixel array, to at least one of digital signals. The analog-to-digital converter circuit includes a comparator which generates a comparator output signal for operatively enabling and disabling, in accordance with a reference signal and an analog pixel output signal from the pixel array, a counter generating a digital signal. The control circuit disables, in accordance with the comparator output signal, the comparator.
5
US2020243510A1
SYSTEMS AND METHODS FOR PROTECTING A SEMICONDUCTOR DEVICE
Publication/Patent Number: US2020243510A1 Publication Date: 2020-07-30 Application Number: 16/848,925 Filing Date: 2020-04-15 Inventor: Chou, Kuo-yu   Yeh shang fu   Chao, Yi-ping   Lee, Chih-lin   Assignee: Taiwan Semiconductor Manufacturing Company Limited   IPC: H01L27/02 Abstract: Circuits and methods for protecting a device are provided. A first device to be protected includes a gate dielectric of a first thickness. A second device includes a gate dielectric of a second thickness that is less than the first thickness. A gate is shared by the first device and the second device.
6
US10636782B2
Systems and methods for protecting a semiconductor device
Publication/Patent Number: US10636782B2 Publication Date: 2020-04-28 Application Number: 16/192,883 Filing Date: 2018-11-16 Inventor: Chou, Kuo-yu   Yeh shang fu   Chao, Yi-ping   Lee, Chih-lin   Assignee: Taiwan Semiconductor Manufacturing Company Limited   IPC: H01L27/02 Abstract: Circuits and methods for protecting a device are provided. A first device to be protected includes a gate dielectric of a first thickness. A second device includes a gate dielectric of a second thickness that is less than the first thickness. A gate is shared by the first device and the second device.
7
US10638078B2
Counter, counting method and apparatus for image sensing
Publication/Patent Number: US10638078B2 Publication Date: 2020-04-28 Application Number: 15/995,143 Filing Date: 2018-06-01 Inventor: Yeh shang fu   Chou, Kuo-yu   Chao, Calvin Yi-ping   Lee, Chih-lin   Yin, Chin   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H04N5/374 Abstract: A counter, a counting method and an apparatus for image sensing are introduced in the present disclosure. The counter includes a plurality of dual phase clock generators and a plurality of column counters. Each of the plurality of dual phase clock generator receives a common clock signal and generates dual phase clock signals which comprise a first clock signal and a second clock signal according to the common clock signal. Each of the plurality of column counters is coupled to one of the plurality of dual phase clock generators to receive the first clock signal and the second clock signal, and is configured to output a counting value according to the first clock signal and the second clock signal. Each of the plurality of dual phase clock generators provides the first clock signal and the second clock signal to a group of the plurality of column counters.
8
US2020174105A1
METHOD AND APPARATUS FOR A HYBRID TIME-OF-FLIGHT SENSOR WITH HIGH DYNAMIC RANGE
Publication/Patent Number: US2020174105A1 Publication Date: 2020-06-04 Application Number: 16/656,424 Filing Date: 2019-10-17 Inventor: Yin, Chin   Wu, Meng-hsiu   Lee, Chih-lin   Chao, Calvin Yi-ping   Yeh shang fu   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: G01S7/486 Abstract: Disclosed is a time-of-flight sensing apparatus and method. In one embodiment, a system for time-of-flight (TOF) sensing, comprising: a detector array comprising a plurality of single-photon avalanche detectors (SPADs); and a control circuit comprising at least two digital control arrays coupled to the detector array, a counter array coupled to the at least two digital control arrays, and a logical control unit coupled to the counter array and the at least two digital control arrays, wherein the detector array is configured to receive at least one reflected light pulse from a target, wherein a first digital control array, the counter array, and the logical control unit of the control circuit are configured to receive at least one avalanche pulses from each of the plurality of SPADs to determine a first distance between the detector array and the target in a first TOF mode, and wherein a second digital control array, the counter array, and the logical control unit of the control circuit are configured to receive the at least one avalanche pulse from the each of the plurality of SPADs to determine a second distance between the detector array and the target in a second TOF mode.
9
US202018642A1
Time-To-Digital Converter Circuit and Method for Single-Photon Avalanche Diode Based Depth Sensing
Publication/Patent Number: US202018642A1 Publication Date: 2020-01-16 Application Number: 20/191,645 Filing Date: 2019-06-27 Inventor: Chou, Kuo-yu   Yeh shang fu   Lee, Chih-lin   Yin, Chin   Chao, Calvin Yi-ping   Assignee: Taiwan Semiconductor Manufacturing Company Limited   IPC: H03L7/081 Abstract: A self-calibration time-to-digital converter (TDC) integrated circuit for single-photon avalanche diode (SPAD) based depth sensing is disclosed. The circuit includes a SPAD matrix with a plurality of SPAD pixels arranged in m rows and n columns, the SPAD pixels in each column of SPAD pixels are connected by a column bus; a global DLL unit with n buffers and n clock signals; and an image signal processing unit for receiving image signals from the column TDC array. The circuit can also include a row control unit configured to enable one SPAD pixel in each row for a transmitting signal; a circular n-way multiplexer for circularly multiplexing n clock signals in the global DLL unit; a column TDC array with n TDCs, each TDC further comprises a counter and a latch, the latch of each TDC is connected to the circular n-way multiplexer for circular multiplexing.
10
US2020408885A1
TIME-OF-LIGHT SENSING DEVICE AND METHOD THEREOF
Publication/Patent Number: US2020408885A1 Publication Date: 2020-12-31 Application Number: 16/454,091 Filing Date: 2019-06-27 Inventor: Yin, Chin   Yeh shang fu   Chao, Calvin Yi-ping   Lee, Chih-lin   Wu, Meng-hsiu   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: G01S7/486 Abstract: A sensing device that is configured to determine a depth result based on time-of-flight value is introduced. The sensing device includes a delay locked loop circuit, a plurality of time-to-digital converters, a multiplexer and a digital integrator. The delay locked loop circuit is configured to output a plurality of delay clock signals through output terminals of the delay locked loop circuit. The plurality of time-to-digital converters include a plurality of latches. The multiplexer is configured to select a sub-group of m latches among the latches of the plurality of time-to-digital converters to be connected to the output terminals of the delay locked loop circuit according to a control signal. The digital integrator is coupled to the plurality of time-to-digital converters and is configured to integrate digital outputs generated by the time-to-digital converters in each of n cycles to generate n raw data frames, wherein m and n are natural numbers, and the n raw data frames are used to generate the depth result.
11
US2020018642A1
Time-To-Digital Converter Circuit and Method for Single-Photon Avalanche Diode Based Depth Sensing
Publication/Patent Number: US2020018642A1 Publication Date: 2020-01-16 Application Number: 16/454,358 Filing Date: 2019-06-27 Inventor: Yin, Chin   Lee, Chih-lin   Yeh shang fu   Chou, Kuo-yu   Chao, Calvin Yi-ping   Assignee: Taiwan Semiconductor Manufacturing Company Limited   IPC: G01J1/44 Abstract: A self-calibration time-to-digital converter (TDC) integrated circuit for single-photon avalanche diode (SPAD) based depth sensing is disclosed. The circuit includes a SPAD matrix with a plurality of SPAD pixels arranged in m rows and n columns, the SPAD pixels in each column of SPAD pixels are connected by a column bus; a global DLL unit with n buffers and n clock signals; and an image signal processing unit for receiving image signals from the column TDC array. The circuit can also include a row control unit configured to enable one SPAD pixel in each row for a transmitting signal; a circular n-way multiplexer for circularly multiplexing n clock signals in the global DLL unit; a column TDC array with n TDCs, each TDC further comprises a counter and a latch, the latch of each TDC is connected to the circular n-way multiplexer for circular multiplexing.
12
US2020119144A1
SEMICONDUCTOR DEVICE WITH LOW RANDOM TELEGRAPH SIGNAL NOISE
Publication/Patent Number: US2020119144A1 Publication Date: 2020-04-16 Application Number: 16/716,299 Filing Date: 2019-12-16 Inventor: Chou, Kuo-yu   Takahashi, Seiji   Yeh shang fu   Lee, Chih-lin   Yin, Chin   Chao, Calvin Yi-ping   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.   IPC: H01L29/06 Abstract: A semiconductor device comprises a source/drain diffusion area, and a first doped region. The source/drain diffusion area is defined between a first isolation structure and a second isolation structure. The source/drain diffusion area includes a source region, a drain region, and a device channel. The device channel is between the source region and the drain region. The first doped region is disposed along a first junction between the device channel and the first isolation structure in a direction from the source region to the drain region. The first doped region is separated from at least one of the source region and the drain region, and has a dopant concentration higher than that of the device channel. The semiconductor device of the present disclosure has low random telegraph signal noise and fewer defects.
13
US2019123754A1
CONDITIONAL CORRELATED MULTIPLE SAMPLING SINGLE SLOPE ANALOG-TO-DIGITAL CONVERTER, AND ASSOCIATED IMAGE SENSOR SYSTEM AND METHOD
Publication/Patent Number: US2019123754A1 Publication Date: 2019-04-25 Application Number: 16/223,859 Filing Date: 2018-12-18 Inventor: Yeh shang fu   Chou, Kuo-yu   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.   IPC: H03M1/34 Abstract: A conditional correlated multiple sampling (CCMS) single slope (SS) analog-to-digital converter (ADC) is provided. The CCMS SS ADC includes a comparator, arranged to compare an analog signal with a ramp signal and generate a comparison result; and a CCMS control circuit, arranged to determine a swing of the ramp signal according to a magnitude of the analog signal. An image sensor system using the CCMS SS ADC and a method of CCMS SS analog-to-digital conversion are also disclosed.
14
US10382052B2
Conditional correlated multiple sampling single slope analog-to-digital converter, and associated image sensor system and method
Publication/Patent Number: US10382052B2 Publication Date: 2019-08-13 Application Number: 16/223,859 Filing Date: 2018-12-18 Inventor: Yeh shang fu   Chou, Kuo-yu   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.   IPC: H03M1/34 Abstract: A conditional correlated multiple sampling (CCMS) single slope (SS) analog-to-digital converter (ADC) is provided. The CCMS SS ADC includes a comparator, arranged to compare an analog signal with a ramp signal and generate a comparison result; and a CCMS control circuit, arranged to determine a swing of the ramp signal according to a magnitude of the analog signal. An image sensor system using the CCMS SS ADC and a method of CCMS SS analog-to-digital conversion are also disclosed.
15
US2019088640A1
SYSTEMS AND METHODS FOR PROTECTING A SEMICONDUCTOR DEVICE
Publication/Patent Number: US2019088640A1 Publication Date: 2019-03-21 Application Number: 16/192,883 Filing Date: 2018-11-16 Inventor: Chou, Kuo-yu   Yeh shang fu   Chao, Yi-ping   Lee, Chih-lin   Assignee: Taiwan Semiconductor Manufacturing Company Limited   IPC: H01L27/02 Abstract: Circuits and methods for protecting a device are provided. A first device to be protected includes a gate dielectric of a first thickness. A second device includes a gate dielectric of a second thickness that is less than the first thickness. A gate is shared by the first device and the second device.
16
US10270992B1
Sampling device and method for reducing noise
Publication/Patent Number: US10270992B1 Publication Date: 2019-04-23 Application Number: 15/828,292 Filing Date: 2017-11-30 Inventor: Yeh shang fu   Lee, Chih-lin   Yin, Chin   Chou, Kuo-yu   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.   IPC: H04N5/357 Abstract: A device includes a current source and sampling units. Each of the sampling units includes a transistor and a capacitor electrically coupled to a gate of the transistor. The sampling units are sequentially activated such that the capacitor samples a voltage of a column line of a pixel array and are activated together such that the transistor is turned on according to the sampled voltage of the capacitor, to drain a current from the current source through an output node to generate an output voltage thereat.
17
US201988640A1
SYSTEMS AND METHODS FOR PROTECTING A SEMICONDUCTOR DEVICE
Publication/Patent Number: US201988640A1 Publication Date: 2019-03-21 Application Number: 20/181,619 Filing Date: 2018-11-16 Inventor: Chou, Kuo-yu   Yeh shang fu   Lee, Chih-lin   Chao, Yi-ping   Assignee: Taiwan Semiconductor Manufacturing Company Limited   IPC: H01L27/02 Abstract: Circuits and methods for protecting a device are provided. A first device to be protected includes a gate dielectric of a first thickness. A second device includes a gate dielectric of a second thickness that is less than the first thickness. A gate is shared by the first device and the second device.
18
US2019373200A1
COUNTER, COUNTING METHOD AND APPARATUS FOR IMAGE SENSING
Publication/Patent Number: US2019373200A1 Publication Date: 2019-12-05 Application Number: 15/995,143 Filing Date: 2018-06-01 Inventor: Yeh shang fu   Chou, Kuo-yu   Chao, Calvin Yi-ping   Lee, Chih-lin   Yin, Chin   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H04N5/376 Abstract: A counter, a counting method and an apparatus for image sensing are introduced in the present disclosure. The counter includes a plurality of dual phase clock generators and a plurality of column counters. Each of the plurality of dual phase clock generator receives a common clock signal and generates dual phase clock signals which comprise a first clock signal and a second clock signal according to the common clock signal. Each of the plurality of column counters is coupled to one of the plurality of dual phase clock generators to receive the first clock signal and the second clock signal, and is configured to output a counting value according to the first clock signal and the second clock signal. Each of the plurality of dual phase clock generators provides the first clock signal and the second clock signal to a group of the plurality of column counters.
19
US10277849B2
System and method for high-speed down-sampled CMOS image sensor readout
Publication/Patent Number: US10277849B2 Publication Date: 2019-04-30 Application Number: 15/941,431 Filing Date: 2018-03-30 Inventor: Chao, Calvin Yi-ping   Chang, Chin-hao   Chou, Kuo-yu   Yeh shang fu   Lee, Chih-lin   Huang, Chiao-yi   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H04N5/345 Abstract: A system and method of routing multiple pixels from a single column in a CMOS (complementary metal-oxide semiconductor) image sensors (CIS) to a plurality of column analog-to-digital converters (ADCs) is disclosed. The CIS includes an array of pixel elements having a plurality of rows and a plurality of columns. A plurality of column-out signal paths is coupled to each of the plurality of columns of the array of pixel elements. A column routing matrix is coupled to each plurality of column-out signal paths for each of the plurality of columns. A plurality of analog-to-digital converters (ADCs) are coupled to the column routing matrix. The column routing matrix is configured to route at least one column-out signal path to each of the plurality of ADCs during a down-sampling read operation.
20
US2019333989A1
SEMICONDUCTOR DEVICE WITH LOW RANDOM TELEGRAPH SIGNAL NOISE
Publication/Patent Number: US2019333989A1 Publication Date: 2019-10-31 Application Number: 15/965,610 Filing Date: 2018-04-27 Inventor: Chou, Kuo-yu   Takahashi, Seiji   Yeh shang fu   Lee, Chih-lin   Yin, Chin   Chao, Calvin Yi-ping   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.   IPC: H01L29/06 Abstract: A semiconductor device comprises a source/drain diffusion area, and a first doped region. The source/drain diffusion area is defined between a first isolation structure and a second isolation structure. The source/drain diffusion area includes a source region, a drain region, and a device channel. The device channel is between the source region and the drain region. The first doped region is disposed along a first junction between the device channel and the first isolation structure in a direction from the source region to the drain region. The first doped region is separated from at least one of the source region and the drain region, and has a dopant concentration higher than that of the device channel. The semiconductor device of the present disclosure has low random telegraph signal noise and fewer defects.
Total 3 pages