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No. Publication Number Title Publication/Patent Number Publication/Patent Number Publication Date Publication Date
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1
US10916177B2
Display apparatus having a unit pixel composed of four sub-pixels
Publication/Patent Number: US10916177B2 Publication Date: 2021-02-09 Application Number: 16/714,168 Filing Date: 2019-12-13 Inventor: Kim, Young-ho   Jeong, Il-gi   Lee, Ung-gi   Park, In-cheol   Jung, Ha-na   Kim, Dong-woo   Assignee: LG Display Co., Ltd.   IPC: G06F1/00 Abstract: A display apparatus in which each unit pixel includes four sub-pixels is provided. The four sub-pixels of each unit pixel may sequentially receive a data line through single data line. Two sub-pixels disposed on a side of the data line may be connected to a reference voltage supply line by a reference connecting line intersecting the data line. Two sub-pixels disposed another side of the data line may be connected to the data line by a data connection line intersecting the reference voltage supply line. An intersection region of the reference connection line and the data line may have the same area as an intersection region of the data connection line and the reference voltage supply line. Thus, in the display apparatus, the variation in the charging rate due to the parasitic capacitance difference of the data connection line and the reference connection line may be reduced.
2
EP3768516A1
PRINTING SYSTEM AND METHOD WITH EFFICIENT MEMORY USAGE
Publication/Patent Number: EP3768516A1 Publication Date: 2021-01-27 Application Number: 19710722.0 Filing Date: 2019-03-20 Inventor: Van, Der Gucht Romain Jan Victor Paul   Goetschalckx, Marc Lodewijk Cornelia   Van, De Velde Nathan Anny Omaar Catharina Didier   Assignee: Xeikon Manufacturing N.V.   IPC: B41J2/21
3
US10951545B2
Network devices
Publication/Patent Number: US10951545B2 Publication Date: 2021-03-16 Application Number: 16/383,711 Filing Date: 2019-04-15 Inventor: Gafni, Barak   Koch, Lavi   Rechtman, Zvi   Assignee: MELLANOX TECHNOLOGIES TLV LTD.   IPC: G06F1/00 Abstract: Apparatus including a network element including an input-output port, the input-output port including an input data lane and an output data lane, wherein the input data lane is in wired connection with a network data source external to the network element, the output data lane is in wired connection with a network data destination external to the network element, and the network data source is distinct from the network data destination. Related apparatus and methods are also described.
4
US10976785B1
Packaging of vertically oriented orthogonally connected systems
Publication/Patent Number: US10976785B1 Publication Date: 2021-04-13 Application Number: 16/829,693 Filing Date: 2020-03-25 Inventor: St., Germain Ronald E.   Zheng, Fengquan   Assignee: JABIL INC.   IPC: G06F1/00 Abstract: A computing system including a chassis and a canister slidably insertable within the chassis, where the canister includes first and second angled slots. A CPU module mounted within the canister includes a plurality of first connectors and a plurality of I/O modules are positioned within the chassis and include a second connector. A plurality of riser cards including a third connector coupled to a bottom edge and a fourth connector coupled to a rear edge, where the third connector on each riser card is connected to one of the first connectors and the fourth connector on each riser card is connected to one of the second connectors. Actuation of ejector levers pivotally mounted to the bottom panel of the chassis cause pins to move in the angled slots and the canister to move relative to the chassis so as to connect and disconnect the second and fourth connectors.
5
US10884483B2
Autonomous C-state algorithm and computational engine alignment for improved processor power efficiency
Publication/Patent Number: US10884483B2 Publication Date: 2021-01-05 Application Number: 16/130,916 Filing Date: 2018-09-13 Inventor: Haj-yihia, Jawad   Weissmann, Eliezer   Degalahal, Vijay S. R.   Shulman, Nadav   Kuzi, Tal   Franko, Itay   Gur, Amit   Rotem, Efraim   Assignee: Intel Corporation   IPC: G06F1/00 Abstract: Methods and apparatus relating to autonomous C state mechanism and computational engine alignment for improved processor power efficiency. are described. An embodiment determines whether a semiconductor package should enter a package C state based on energy consumption values for entry into and exit from the package C state, an amount of time the semiconductor package stayed in the package C state previously, and one or more breakeven time points between the various package C states. Another embodiment detects a delay by an imaging computational unit of a processor to enter a low power consumption state relative to one or more other computational units of the processor. The logic causes the imaging computational unit to enter the low power consumption state in response to detection of the delay. Other embodiments are also disclosed and claimed.
6
US10963013B2
Display device
Publication/Patent Number: US10963013B2 Publication Date: 2021-03-30 Application Number: 16/311,681 Filing Date: 2018-11-15 Inventor: Song, Yuelong   Assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.   IPC: G06F1/00 Abstract: A display device includes a display panel and a flexible substrate. A first pad and a second pad are arranged on the display panel. The flexible substrate includes a first layer, a first insulating layer, and a second layer on a bending area. A first metal line is arranged in the first layer and connected to the first pad. A second metal line is arranged in the second layer and connected to the second pad. A straightened length of the first metal line is greater than that of the second metal line. The design of a double-layer metal line effectively improves the stress intensity of the metal line in the outer bending area. Therefore, the inner and outer double-line metal line in the bending area is balanced by force, so that the stability of the inner and outer double-line metal line is relatively uniform.
7
US10891249B2
Dynamic system management bus
Publication/Patent Number: US10891249B2 Publication Date: 2021-01-12 Application Number: 16/666,999 Filing Date: 2019-10-29 Inventor: Frushour, Scott E. M.   Assignee: Covidien LP   IPC: G06F1/00 Abstract: A dynamic bus communication apparatus for an electrosurgical system includes a data wire, a clock wire, a first variable resistor coupled to the data wire, a second variable resistor coupled to the clock wire, an analog to digital converter (ADC), and a controller. The data wire is configured to transmit a data signal between a battery and an instrument powered by the battery. The clock wire is configured to transmit a clock signal between a battery and an instrument. The ADC is configured to sample the data signal and the clock signal at a substantially higher frequency than a frequency of the clock signal. The controller is configured to control a resistance of the first variable resistor and a resistance of the second variable resistor based on the digitally sampled data signal and the digitally sampled clock signal.
8
US10896631B2
Indicium illumination
Publication/Patent Number: US10896631B2 Publication Date: 2021-01-19 Application Number: 16/678,534 Filing Date: 2019-11-08 Inventor: Peterson, Cody   Huska, Andrew   Assignee: Rohinni, LLC   IPC: G09F13/00 Abstract: An electronic device comprising a housing having a front and a back; a component embedded within the front or the back of the housing; and an array of light-generating sources (LGSs) deposited on a substrate disposed in the housing, the array of LGSs being disposed adjacent at least a portion of the component of the electronic device.
9
US10909636B1
System, method and non-transitory computer readable medium for parsing receipt information
Publication/Patent Number: US10909636B1 Publication Date: 2021-02-02 Application Number: 15/987,710 Filing Date: 2018-05-23 Inventor: Neveu, Alan   Neveu, Robert   Assignee: Certify, Inc.   IPC: G06F1/00 Abstract: Systems and methods for parsing receipt information are provided. A system includes a receipt parsing component executable by at least one processor. The receipt parsing component is configured to access a plurality of regular expressions associated with a plurality of vendor elements; identify a string of characters in received text that matches a character pattern specified by at least one regular expression of the plurality of regular expressions, wherein the at least one regular expression includes metacharacters; capture a value of a vendor element from the received text, wherein the value of the vendor element comprises the string of characters that match the character pattern; access reference data specifying additional elements associated with the value of the vendor element and information to identify values of the additional elements; and capture the values of the additional elements in the text based on the reference data.
10
US10963034B2
System, apparatus and method for loose lock-step redundancy power management in a processor
Publication/Patent Number: US10963034B2 Publication Date: 2021-03-30 Application Number: 16/546,441 Filing Date: 2019-08-21 Inventor: Rotem, Efraim   Weissmann, Eliezer   Rajwan, Doron   Rosenzweig, Nir   Aizik, Yoni   Assignee: Intel Corporation   IPC: G06F1/00 Abstract: A processor includes a plurality of cores, at least two of which may execute redundantly, a configuration register to store a first synchronization domain indicator to indicate that a first core and a second core are associated with a first synchronization domain, and a power controller having a synchronization circuit to cause a dynamic adjustment to a frequency of at least one of the first and second cores to cause these cores to operate at a common frequency, based at least in part on the first synchronization domain indicator.
11
US10990146B2
Digital synthesizable low dropout regulator with adaptive gain
Publication/Patent Number: US10990146B2 Publication Date: 2021-04-27 Application Number: 16/359,810 Filing Date: 2019-03-20 Inventor: Muthukaruppan, Ramnarayanan   Patra, Pradipta   Goel, Gaurav   Kadali, Uday Bhaskar   Assignee: Intel Corporation   IPC: G06F1/00 Abstract: Described is a voltage regulator with adaptive gain, which comprises: a plurality of power-gate transistors controllable by a digital bus, the plurality of power-gate transistors operable to provide a first power supply to a load, and to receive a second power supply as input; an analog-to-digital converter (ADC) to receive the first power supply and to generate a digital output representative of the first power supply; and a controller to receive the digital output representative of the first power supply and to generate the digital bus for controlling the plurality of power-gate transistors such that a transfer function of the plurality of power-gate transistors is substantially linear over an operating range.
12
CN111698435B
空频谱多维联合调制的成像加速方法和装置
Grant
Publication/Patent Number: CN111698435B Publication Date: 2021-04-27 Application Number: 202010522279.5 Filing Date: 2020-06-10 Inventor: 边丽蘅   宋昊泽   张军   Assignee: 北京理工大学   IPC: H04N5/235 Abstract: 本申请提出一种空频谱多维联合调制的成像加速方法和装置,其中,方法包括:对目标场景进行谱域调制、空域调制和频域调制;使用传感器在单曝光时间内耦合采集谱域调制、空域调制和频域调制下的单张图像;通过解耦算法对单张图像进行反解,得到多帧场景图像。由此,达到加速成像的效果,进而能够有效提升传感器成像速度,提高拍摄视频的帧频,并同时具有鲁棒、精确、高效的优点。
13
EP3451112B1
MULTIFUNCTION APPARATUS
Publication/Patent Number: EP3451112B1 Publication Date: 2021-01-27 Application Number: 18194150.1 Filing Date: 2005-02-16 Inventor: Nishizawa, Minoru   Takahashi, Etsuro   Assignee: Panasonic Corporation   IPC: G06F1/00
14
EP3190474B1
DEVICE FOR MONITORING FLOW RATE AND DISTRIBUTIONAL UNIFORMITY OF LIQUID IN MULTI-CHANNEL HYDRAULIC SYSTEM
Publication/Patent Number: EP3190474B1 Publication Date: 2021-03-31 Application Number: 14901325.2 Filing Date: 2014-09-01 Inventor: Gromyshev, Evgeny Valerievich   Khlyst, Sergey Vasilievich   Khlyst, Ilya Sergeevich   Kuzmichenko, Vladimir Mikhaylovich   Fazatdinov, Renad Ibragimovich   Izotov, Oleg Petrovich   Shestakov, Andrey Nikolaevich   Ivanov, Alexey Gennadievich   Kirichenko, Mikhail Nikolaevich   Pshenichnikov, Pavel Alexandrovich   Assignee: Scientific And Manufacturing Enterprise "Tomsk Electronic Company" Ltd.   IPC: F27D19/00
15
US10963023B1
Orthogonal structure with riser card
Publication/Patent Number: US10963023B1 Publication Date: 2021-03-30 Application Number: 16/827,831 Filing Date: 2020-03-24 Inventor: Zheng, Fengquan   St., Germain Ronald E.   Assignee: JABIL INC.   IPC: G06F1/00 Abstract: A computing system including a housing assembly having a front and a rear, a CPU module positioned towards the front of the housing assembly and including a plurality of I/O connectors, and a plurality of I/O modules positioned towards the rear of the housing assembly, where each I/O module includes a second I/O connector. The computing system also includes a plurality of riser cards each having a PCB with opposing side surfaces, a front edge, a rear edge, a top edge, a bottom edge, a third I/O connector coupled to the bottom edge and a fourth I/O connector coupled to the rear edge. The third I/O connector on each riser card is connected to one of the first I/O connectors and the fourth I/O connector on each riser card is connected to one of the second I/O connectors so that the riser cards are oriented in parallel with each other.
16
US10937378B2
Display panel and display method
Publication/Patent Number: US10937378B2 Publication Date: 2021-03-02 Application Number: 16/759,830 Filing Date: 2019-10-09 Inventor: Li, Zhenzhen   Zhao, Hui   Assignee: BOE TECHNOLOGY GROUP CO., LTD.   IPC: G06F1/00 Abstract: The disclosure provides a display panel and a display method, the display panel includes multiple pixel arrangement units including a first pixel arrangement unit and a second pixel arrangement unit, at least a portion of the sub-pixel regions of the first pixel arrangement unit are vacant sub-pixel regions, each sub-pixel region of the second pixel arrangement unit has one sub-pixel, the display method includes: generating an original image composed of multiple virtual pixels, adjacent virtual sub-pixels in any two adjacent virtual pixels correspond to a single sub-pixel region; controlling color original components of the virtual pixels corresponding to the vacant sub-pixel regions to be 0, acquiring color original components of the virtual sub-pixels in remaining virtual pixels; calculating a display component of each sub-pixel according to the corresponding color original component of a same color in at least one virtual pixel corresponding thereto.
17
US10884473B2
Methods, electronic devices, and storage mediums for waking up an icon
Publication/Patent Number: US10884473B2 Publication Date: 2021-01-05 Application Number: 16/379,134 Filing Date: 2019-04-09 Inventor: Wang, Gang   Tang, Ju   Wang, Di   Assignee: Beijing Xiaomi Mobile Software Co., Ltd.   IPC: G06F1/00 Abstract: A method and a terminal device are provided for waking up an icon. Upon detection of a first wake event while a display screen of said terminal device is in a Screen-Off mode, the terminal device determines whether a second wake event is detected within a preset time threshold. The display screen is equipped with an under-screen fingerprint recognition circuitry in a fingerprint recognition area. Upon detection of said second wake event within said preset time threshold, the terminal device causes said display screen to switch into a Screen-On mode in which a preset icon is displayed in the fingerprint recognition area. When said second wake event is not detected within said preset time threshold, the said terminal device causes said display screen to switch into an Always on Display mode in which said preset icon is displayed in the fingerprint recognition area.
18
US10890962B2
Power management in a configurable bus
Publication/Patent Number: US10890962B2 Publication Date: 2021-01-12 Application Number: 15/909,626 Filing Date: 2018-03-01 Inventor: Sinha, Rajesh Kumar   Assignee: Avago Technologies International Sales Pte. Limited   IPC: G06F1/00 Abstract: A system includes a bus and a component interconnected via the bus. The component may enter a sleep mode during a period of no data transmission involving the component.
19
US10969844B2
Method and apparatus of controlling network node by providing a virtual power distribution unit
Publication/Patent Number: US10969844B2 Publication Date: 2021-04-06 Application Number: 16/443,396 Filing Date: 2019-06-17 Inventor: Xia, Robert Guowu   Wu, Chao   Fu, Bryan Xiaoguang   Shu, Sophia Xiaoxia   Cai, Simon Xingwang   Zhai, Li   Assignee: EMC IP Holding Company, LLC   IPC: G06F1/00 Abstract: Embodiments of the present disclosure provide a method and apparatus of controlling a network node. The method comprises: providing a virtual PDU by using a computing device; and causing the virtual PDU to control power supply of the network node coupled to the virtual PDU according to a type of the network node. By means of the embodiments of the present disclosure, not only physical nodes can be controlled, but also virtual nodes can be controlled.
20
US10996725B2
Power management in a multiple-processor computing device
Publication/Patent Number: US10996725B2 Publication Date: 2021-05-04 Application Number: 16/108,006 Filing Date: 2018-08-21 Inventor: Li, Sau Yan Keith   Dewey, Thomas E.   Chen, Arthur   Lai, Simon   Pabalkar, Amit   Nayak, Santosh   Assignee: NVIDIA Corporation   IPC: G06F1/00 Abstract: A method for managing power in a multiple processor computing device includes detecting a first amount of power being used by a first processor of the computing device; determining an amount of extra power available based on the first amount of power and a power budget for the first processor; and transmits a value to a driver associated with a second processor of the computing device, wherein the value indicates the amount of extra power available, wherein the driver adjusts at least one operating parameter of the second processor based on the amount of extra power available.
Total 500 pages