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No. Publication Number Title Publication/Patent Number Publication/Patent Number Publication Date Publication Date
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1 US10592530B2
System and method for managing transactions for multiple data store nodes without a central log
Publication/Patent Number: US10592530B2 Publication Date: 2020-03-17 Application Number: 15/878,341 Filing Date: 2018-01-23 Inventor: Johnson, Rob   Spillane, Richard P.   Chowksey, Kapil   Gupta, Abhishek   Wang, Wenguang   Assignee: VMware, Inc.   IPC: G06F16/23 Abstract: Data storage system and method for managing transaction requests in the data storage system utilizes prepare requests for a transaction request for multiple data storage operations. The prepare requests are sent to selected destination storage nodes of the data storage system to handle the multiple data storage operations. Each prepare request includes at least one of the multiple data storage operations to be handled by a particular destination data store node and a list of the destination storage nodes involved in the transaction request. Data storage system and method for managing transaction requests in the data storage system utilizes prepare requests for a transaction request for multiple data storage operations. The prepare requests are sent to selected destination storage nodes of the data storage system to ...More Less
2 US10592243B2
Streaming engine with cache-like stream data storage and lifetime tracking
Publication/Patent Number: US10592243B2 Publication Date: 2020-03-17 Application Number: 16/126,680 Filing Date: 2018-09-10 Inventor: Zbiciak, Joseph   Assignee: TEXAS INSTRUMENTS INCORPORATED   IPC: G06F12/0811 Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. The streaming engine fetches stream data ahead of use by the central processing unit core in a stream buffer constructed like a cache. The stream buffer cache includes plural cache lines, each includes tag bits, at least one valid bit and data bits. Cache lines are allocated to store newly fetched stream data. Cache lines are deallocated upon consumption of the data by a central processing unit core functional unit. Instructions preferably include operand fields with a first subset of codings corresponding to registers, a stream read only operand coding and a stream read and advance operand coding. A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements. A steam head register stores data elements next to be supplied to functional units for use as ...More Less
3 US10599120B2
System and method of monitoring of the execution system of a programmable logic controller
Publication/Patent Number: US10599120B2 Publication Date: 2020-03-24 Application Number: 15/715,258 Filing Date: 2017-09-26 Inventor: Dyakin, Pavel V.   Kulagin, Dmitry A.   Assignee: AO Kaspersky Lab   IPC: G06F11/00 Abstract: Disclosed systems and methods for monitoring an execution system of a programming logic controller (PLC), the method comprising: accessing, by a security module, the PLC execution system and dividing the code and data of the PLC execution system into a plurality of program modules; modifying, by the security module, data exchange interfaces of the program modules used for the interaction between the program modules and the resources of the operating system such that said interaction occurs through the security module, while a format of the data being exchanged complies with a format specified by the security module; and monitoring, by the security module, the execution of the PLC execution system, including monitoring the interaction of the program modules of the PLC execution system with each other and with the resources of the operating system. Disclosed systems and methods for monitoring an execution system of a programming logic controller (PLC), the method comprising: accessing, by a security module, the PLC execution system and dividing the code and data of the PLC execution system into a plurality of program ...More Less
4 US10578673B2
Test prioritization and dynamic test case sequencing
Publication/Patent Number: US10578673B2 Publication Date: 2020-03-03 Application Number: 16/209,103 Filing Date: 2018-12-04 Inventor: Ranganathan, Sunder Nochilur   Venkataraman, Mahesh   Girish, Kulkarni   Fernandes, Mallika   Gouthaman, Jothi   Shenoy, Venugopal S.   Durg, Kishore P.   Assignee: Accenture Global Solutions Limited   IPC: G06F9/44 Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for a touchless testing platform employed to, for example, create automated testing scripts, sequence test cases, and implement defect solutions. In one aspect, a method includes receiving a log file and testing results generated from a code base for an application; processing the log file through a pattern-mining algorithm to determine a usage pattern of code modules within the code base; clustering defects from the testing results based on a respective functionality of the application reported within each of the defects; generating testing prioritizations for test cases for the application by assigning weightages to the test cases based on the clusters of defects and the usage pattern of the code modules within the code base; sequencing a set of the test cases based on the test prioritizations; and transmitting the sequence to a test execution engine. Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for a touchless testing platform employed to, for example, create automated testing scripts, sequence test cases, and implement defect solutions. In one aspect, a method includes ...More Less
5 US10579482B2
Method of checkpointing the working environment of a session of a user on a server
Publication/Patent Number: US10579482B2 Publication Date: 2020-03-03 Application Number: 15/213,609 Filing Date: 2016-07-19 Inventor: Cohard, Sylvain   Escovar, Rafael   Assignee: BULL SAS   IPC: G06F11/00 Abstract: The invention relates to a method of checkpointing the working environment of a user (7) session on a server (1) comprising a first step (11) of checkpointing the working environment of a first application of said session, characterized in that it comprises at least one second step (12) of checkpointing the working environment of a second application of said session different from said first application, and in that said first checkpointing step (11) and said second checkpointing step (12) are synchronized with each other such that the checkpointed working environment of the first application and the checkpointed working environment of the second application are coherent with each other. The invention relates to a method of checkpointing the working environment of a user (7) session on a server (1) comprising a first step (11) of checkpointing the working environment of a first application of said session, characterized in that it comprises at least one second ...More Less
6 US10572324B2
Intelligent listening system for agile delivery of cloud services
Publication/Patent Number: US10572324B2 Publication Date: 2020-02-25 Application Number: 15/395,201 Filing Date: 2016-12-30 Inventor: Sharma, Esha   Isaak, Donovan A.   Ramalingam, Vadi   Assignee: Microsoft Technology Licensing, LLC   IPC: G06F11/00 Abstract: A support data generation system detects an indication of a problem within a flighted infrastructure. Based on the detected indication, a feature undergoing implementation within the flighted infrastructure is identified. The identification occurs automatically after the indication is detected. An alert comprises the detected indication and the identified feature is generated and output on a user interface. A support data generation system detects an indication of a problem within a flighted infrastructure. Based on the detected indication, a feature undergoing implementation within the flighted infrastructure is identified. The identification occurs automatically after the ...More Less
7 US10608868B2
System and method for proactive distributed agent based network diagnosis
Publication/Patent Number: US10608868B2 Publication Date: 2020-03-31 Application Number: 15/825,442 Filing Date: 2017-11-29 Inventor: Cheng, Chia-le   Chorley, Jason   Hill, Jevon J. C.   Assignee: International Business Machines Corporation   IPC: G06F11/00 Abstract: A method, system, and apparatus are provided for diagnosing network faults by distributing network test policies to remote devices that issue network tests and report network test results from a first remote device which attempts to access a first network resource over a first specified network path, where a central portal responds to a first network test result by issuing a command to one or more additional remote devices to issue one or more additional network tests for evaluating at least part of the first specified network path and report network verification test results having data which is aggregated with data from the first network test result report for use in proactively diagnosing the network fault in the first specified network path. A method, system, and apparatus are provided for diagnosing network faults by distributing network test policies to remote devices that issue network tests and report network test results from a first remote device which attempts to access a first network resource over a first ...More Less
8 US10608943B2
Dynamic buffer management in multi-client token flow control routers
Publication/Patent Number: US10608943B2 Publication Date: 2020-03-31 Application Number: 15/796,528 Filing Date: 2017-10-27 Inventor: Smith, Alan Dodson   Patel, Chintan S.   Morton, Eric Christopher   Kalyanasundharam, Vydhyanathan   Kamat, Narendra   Assignee: Advanced Micro Devices, Inc.   IPC: G01R31/08 Abstract: Systems, apparatuses, and methods for dynamic buffer management in multi-client token flow control routers are disclosed. A system includes at least one or more processing units, a memory, and a communication fabric with a plurality of routers coupled to the processing unit(s) and the memory. A router servicing multiple active clients allocates a first number of tokens to each active client. The first number of tokens is less than a second number of tokens needed to saturate the bandwidth of each client to the router. The router also allocates a third number of tokens to a free pool, with tokens from the free pool being dynamically allocated to different clients. The third number of tokens is equal to the difference between the second number of tokens and the first number of tokens. An advantage of this approach is reducing the amount of buffer space needed at the router. Systems, apparatuses, and methods for dynamic buffer management in multi-client token flow control routers are disclosed. A system includes at least one or more processing units, a memory, and a communication fabric with a plurality of routers coupled to the processing unit(s) ...More Less
9 US10606674B1
Systems and methods for prognostic network management
Publication/Patent Number: US10606674B1 Publication Date: 2020-03-31 Application Number: 15/447,043 Filing Date: 2017-03-01 Inventor: Tolentino, Elmer   Pritchard, Graham S   Keck, Steven   Champaneri, Jayesh   Hiremagalur, Dharini   Assignee: Juniper Networks, Inc   IPC: G06F11/00 Abstract: A computer-implemented method for prognostic network management may include (1) monitoring a health indicator of a physical component of a device in a network, (2) using the health indicator to estimate a remaining useful life of the physical component, (3) detecting that the remaining useful life of the physical component has reached a predetermined threshold, and (4) reconfiguring the network in response to detecting that the remaining useful life of the physical component has reached the predetermined threshold so that failure of the physical component does not cause the network to become unavailable to any user of the network. Various other methods, systems, and computer-readable media are also disclosed. A computer-implemented method for prognostic network management may include (1) monitoring a health indicator of a physical component of a device in a network, (2) using the health indicator to estimate a remaining useful life of the physical component, (3) detecting that the ...More Less
10 US10606711B2
Recovery strategy for a stream processing system
Publication/Patent Number: US10606711B2 Publication Date: 2020-03-31 Application Number: 15/954,014 Filing Date: 2018-04-16 Inventor: Bishop, Elden Gregory   Chao, Jeffrey   Assignee: salesforce.com, inc.   IPC: G06F11/00 Abstract: The technology disclosed relates to discovering multiple previously unknown and undetected technical problems in fault tolerance and data recovery mechanisms of modern stream processing systems. In addition, it relates to providing technical solutions to these previously unknown and undetected problems. In particular, the technology disclosed relates to discovering the problem of modification of batch size of a given batch during its replay after a processing failure. This problem results in over-count when the input during replay is not a superset of the input fed at the original play. Further, the technology disclosed discovers the problem of inaccurate counter updates in replay schemes of modern stream processing systems when one or more keys disappear between a batch's first play and its replay. This problem is exacerbated when data in batches is merged or mapped with data from an external data store. The technology disclosed relates to discovering multiple previously unknown and undetected technical problems in fault tolerance and data recovery mechanisms of modern stream processing systems. In addition, it relates to providing technical solutions to these previously unknown ...More Less
11 US10606679B2
Debug apparatus and method
Publication/Patent Number: US10606679B2 Publication Date: 2020-03-31 Application Number: 15/830,380 Filing Date: 2017-12-04 Inventor: Kona, Anitha   Williams, Michael John   Horley, John Michael   Grant, Alasdair   Assignee: Arm Limited   IPC: G06F11/00 Abstract: An apparatus includes processor circuitry to perform data processing operations. Interface circuitry forms a connection to a plurality of other apparatuses and receives a foreign exception message indicative of a foreign exception event having been triggered on one of the other apparatuses. In response to receiving the foreign exception message, the interface circuitry forwards the foreign exception message to a set of the plurality of other apparatuses. An apparatus includes processor circuitry to perform data processing operations. Interface circuitry forms a connection to a plurality of other apparatuses and receives a foreign exception message indicative of a foreign exception event having been triggered on one of the other ...More Less
12 US10592326B2
Method and apparatus for data loss assessment
Publication/Patent Number: US10592326B2 Publication Date: 2020-03-17 Application Number: 15/913,955 Filing Date: 2018-03-07 Inventor: Winokur, Alex   Assignee: AXXANA (ISRAEL) LTD.   IPC: G06F11/20 Abstract: A method, including receiving, by a secure processor housed in a disaster-proof casing located at a local site, recurring wireless signals from an application server and from a storage system that are collocated with the processor at the local site, the application server configured to store data to the primary storage system, and to mirror the data to a remote site, each of the wireless signals indicating a status of the application server or the storage system at a given time. A status log including the respective statuses of the application server and the storage system at the received times is stored to a memory in the casing, and subsequent to failures of the application server, the storage system and the mirroring, the status log analyzed to compute a data loss at the local site resulting from the failures of the application server, the storage system, and the mirroring. A method, including receiving, by a secure processor housed in a disaster-proof casing located at a local site, recurring wireless signals from an application server and from a storage system that are collocated with the processor at the local site, the application server ...More Less
13 US10592398B1
Generating a test script execution order
Publication/Patent Number: US10592398B1 Publication Date: 2020-03-17 Application Number: 16/144,817 Filing Date: 2018-09-27 Inventor: N, C Shrikanth   Durg, Kishore P   Podder, Sanjay   Dubash, Neville   Dwarakanath, Anurag   Assignee: Accenture Global Solutions Limited   IPC: G06F9/50 Abstract: A device may determine probabilities for test scripts associated with a test to be executed on a software element, where a respective probability is associated with a respective test script, indicates a likelihood that the respective test script will be unsuccessful in a test cycle, and is determined based on historical test results, associated with the software element, for the respective test script. The device may generate, based on the probabilities, a test script execution order, of the test scripts, for the test cycle, and may execute, based on the test script execution order, the test on the software element in the test cycle. The device may dynamically generate, based on results for the test in the test cycle, an updated test script execution order, and may execute, based on the updated test script execution order, the test on the software element in the test cycle. A device may determine probabilities for test scripts associated with a test to be executed on a software element, where a respective probability is associated with a respective test script, indicates a likelihood that the respective test script will be unsuccessful in a test ...More Less
14 US10592404B2
Performance test of software products with reduced duration
Publication/Patent Number: US10592404B2 Publication Date: 2020-03-17 Application Number: 15/446,114 Filing Date: 2017-03-01 Inventor: Trovato, Ignazio F.   Toro, Pia   Pecoraro, Roberto   Colaiacomo, Giovanni L.   Assignee: International Business Machines Corporation   IPC: G06F11/36 Abstract: A method and system for testing performance of a software product. One or more complete executions of a performance test of corresponding versions of the software product are performed. The complete executions of the performance test identifies a steady state value of each performance parameter monitored during the performance test after each performance parameter has transitioned to a steady state during the performance test. A performance profile of the software product is determined according to the complete executions of the performance test. Partial executions of the performance test of corresponding further versions of the software product are performed, each partial execution having a partial duration preceding the steady state of each performance parameter. Corresponding results of the partial executions of the performance test are estimated according to the performance profile from corresponding partial trends of each performance parameter during the partial executions of the performance test. A method and system for testing performance of a software product. One or more complete executions of a performance test of corresponding versions of the software product are performed. The complete executions of the performance test identifies a steady state value of each ...More Less
15 US10642685B2
Cache memory and processor system
Publication/Patent Number: US10642685B2 Publication Date: 2020-05-05 Application Number: 15/262,218 Filing Date: 2016-09-12 Inventor: Ikegami, Kazutaka   Fujita, Shinobu   Noguchi, Hiroki   Assignee: Kioxia Corporation   IPC: G06F11/00 Abstract: A cache memory has cache memory circuitry comprising a nonvolatile memory cell to store at least a portion of a data which is stored or is to be stored in a lower-level memory than the cache memory circuitry, a first redundancy code storage comprising a nonvolatile memory cell capable of storing a redundancy code of the data stored in the cache memory circuitry, and a second redundancy code storage comprising a volatile memory cell capable of storing the redundancy code. A cache memory has cache memory circuitry comprising a nonvolatile memory cell to store at least a portion of a data which is stored or is to be stored in a lower-level memory than the cache memory circuitry, a first redundancy code storage comprising a nonvolatile memory cell ...More Less
16 US10635441B2
Caller protected stack return address in a hardware managed stack architecture
Publication/Patent Number: US10635441B2 Publication Date: 2020-04-28 Application Number: 15/830,095 Filing Date: 2017-12-04 Inventor: Duvalsaint, Karl J.   Gschwind, Michael K.   Salapura, Valentina   Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION   IPC: G06F11/00 Abstract: Corruption of program stacks is detected by using guard words placed in the program stacks. A called routine executing on a processor checks a guard word in a stack of a calling routine. The checking determines whether the guard word has an expected value. Based on determining the guard word has an unexpected value, an indication of corruption of the stack is provided. Some routines, however, may not support use of guard words. Thus, routines that are interlinked may have differing protection capabilities. A determination is made as to the differing protection capabilities, an indication of the same is provided, and the routines are executed without failing due to the differing protection capabilities. Corruption of program stacks is detected by using guard words placed in the program stacks. A called routine executing on a processor checks a guard word in a stack of a calling routine. The checking determines whether the guard word has an expected value. Based on determining ...More Less
17 US10635910B2
Malfunction diagnosis apparatus
Publication/Patent Number: US10635910B2 Publication Date: 2020-04-28 Application Number: 15/202,527 Filing Date: 2016-07-05 Inventor: Hishinuma, Yoshiaki   Urushizaki, Naoyuki   Sugita, Hirokazu   Kobayashi, Kazuhiko   Assignee: TRANSTRON INC   IPC: G06K9/00 Abstract: This malfunction diagnosis apparatus detects a line on a road surface by distinguishing the line from an asphalt surface other than the line. The malfunction diagnosis apparatus sets a first area corresponding to the line and a second area corresponding to the asphalt surface using a first image captured while the line is detected. The malfunction diagnosis apparatus calculates a first brightness in the first area and a second brightness in the second area using a second image captured while the vehicle is cruising and the line is not detected. Further, the malfunction diagnosis apparatus diagnoses the malfunction based on at least one of the first brightness and the second brightness. This malfunction diagnosis apparatus detects a line on a road surface by distinguishing the line from an asphalt surface other than the line. The malfunction diagnosis apparatus sets a first area corresponding to the line and a second area corresponding to the asphalt surface ...More Less
18 US10635515B2
Recovery of partial memory die
Publication/Patent Number: US10635515B2 Publication Date: 2020-04-28 Application Number: 15/834,050 Filing Date: 2017-12-06 Inventor: Lobana, Sukhminder Singh   Periyannan, Kirubakaran   Assignee: SanDisk Technologies LLC   IPC: G06F11/00 Abstract: A partial memory die is removed from an edge of a wafer such that the partial memory die is missing a portion of the memory structure that was not printed on the wafer. A usable portion of the incomplete memory structure is determined and one or more rectangular zones in the usable portion of the incomplete memory structure are identified. During operation of the memory system, the memory system receives logical addresses for memory operations to be performed on the partial memory die and determines physical addresses that corresponding to the logical addresses. The memory system performs an out of bounds response for a physical address that is on the partial memory die but outside of the one or more rectangular zones. The memory system performs memory operations for physical addresses that are inside the one or more rectangular zones. A partial memory die is removed from an edge of a wafer such that the partial memory die is missing a portion of the memory structure that was not printed on the wafer. A usable portion of the incomplete memory structure is determined and one or more rectangular zones in the ...More Less
19 US10635535B2
Semiconductor memory devices, memory systems, and methods of operating the semiconductor memory devices
Publication/Patent Number: US10635535B2 Publication Date: 2020-04-28 Application Number: 16/185,453 Filing Date: 2018-11-09 Inventor: Cha, Sang-uhn   Kim, Kyung-ryun   Seo, Young-hun   Assignee: SAMSUNG ELECTRONICS CO., LTD.   IPC: G06F11/00 Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, an input/output (I/O) gating circuit, and a control logic circuit. The memory cell array includes a plurality of bank arrays, and each of the bank arrays includes dynamic memory cells. The control logic circuit generates a first control signal to control the I/O gating circuit and a second control signal to control the ECC engine, in response to an access address and a command. The control logic circuit controls the ECC engine to perform s-bit ECC encoding on a write data to be stored in a first page of at least one bank array, in response to a first command, and controls the ECC engine to perform t-bit ECC decoding on a first codeword read from the first page, in response to a second command. A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, an input/output (I/O) gating circuit, and a control logic circuit. The memory cell array includes a plurality of bank arrays, and each of the bank arrays includes dynamic memory ...More Less
20 US10635556B2
Device maintenance apparatus, method for maintaining device, and storage medium
Publication/Patent Number: US10635556B2 Publication Date: 2020-04-28 Application Number: 15/481,697 Filing Date: 2017-04-07 Inventor: Katayama, Hirotaka   Okamoto, Hiromi   Iketsuki, Yuya   Assignee: Yokogawa Electric Corporation   IPC: G06F11/00 Abstract: A device maintenance apparatus includes a setting operator configured to allow for setting a test pattern, the test pattern being set to define a change of output signals output from a device over time, and an execution operator configured to make the device output the output signals based on the set test pattern. A device maintenance apparatus includes a setting operator configured to allow for setting a test pattern, the test pattern being set to define a change of output signals output from a device over time, and an execution operator configured to make the device output the output ...More Less