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No. Publication Number Title Publication/Patent Number Publication/Patent Number Publication Date Publication Date
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1 US10649913B2
Operating method for data storage device
Publication/Patent Number: US10649913B2 Publication Date: 2020-05-12 Application Number: 15/783,973 Filing Date: 2017-10-13 Inventor: Hsu, Hong-jung   Hsu, Chen-hui   Assignee: Silicon Motion, Inc.   IPC: G06F12/1045 Abstract: An operating method for a data storage device is provided. The operating method includes steps of: dividing a mapping table into a plurality of sub-mapping tables; receiving an access command comprising a data address and a command category; determining whether a target sub-mapping table corresponding to the data address has been cached, wherein the target sub-mapping table is one of the sub-mapping tables; and if false, reading and caching the target sub-mapping table from the sub-mapping tables. An operating method for a data storage device is provided. The operating method includes steps of: dividing a mapping table into a plurality of sub-mapping tables; receiving an access command comprising a data address and a command category; determining whether a target ...More ...Less
2 EP2661692B1
MEMORY ADDRESS TRANSLATION
Publication/Patent Number: EP2661692B1 Publication Date: 2020-05-20 Application Number: 12732390.5 Filing Date: 2012-01-05 Inventor: Manning, Troy A.   Culley, Martin L.   Larsen, Troy D.   Assignee: Micron Technology, Inc.   IPC: G06F12/06
3 US10552322B2
Throttling writes with asynchronous flushing
Publication/Patent Number: US10552322B2 Publication Date: 2020-02-04 Application Number: 15/815,313 Filing Date: 2017-11-16 Inventor: Hu, Guoyu   Lv, Shuo   Zhou, Qiaosheng   Gu, Congyue   Assignee: EMC IP Holding Company LLC   IPC: G06F12/0804 Abstract: Embodiments are directed to techniques for allowing a data storage system to be able to flush data to underlying storage when the bandwidth is high without excessively impacting the maximum latency. This may be accomplished by utilizing asynchronous flushing and by throttling incoming writes by preventing too many asynchronous flushes from happening when the amount of available cache space is too small. In addition, an improved system employing Copy on First Write (CoFW) may initiate write throttling only once the amount of available write cache drops below a dynamically-calculated threshold that accounts for an amount of space actually needed to store CoFW buffers. In addition, only a portion of the write caching process is placed under the protection of a mutex or a spinlock, allowing a significant portion of the write caching for any given write operation to be performed without needing the mutex or spinlock, allowing some increased parallelization. Embodiments are directed to techniques for allowing a data storage system to be able to flush data to underlying storage when the bandwidth is high without excessively impacting the maximum latency. This may be accomplished by utilizing asynchronous flushing and by throttling ...More ...Less
4 US10552313B2
Updating cache using two bloom filters
Publication/Patent Number: US10552313B2 Publication Date: 2020-02-04 Application Number: 15/889,521 Filing Date: 2018-02-06 Inventor: Bar-joshua, Michael   Benjamini, Yiftach   Blaner, Bartholomew   Grubman, Michael   Assignee: International Business Machines Corporation   IPC: G06F12/0864 Abstract: Updating cache devices includes a processor to detect a first set of hash functions and a first bit array corresponding to elements of a cache. In some examples, the processor detects a first instruction to add a new element to the cache and modify the first bit array based on the new element. Additionally, the processor processes a first invalidation operation and generates a second bit array and a second set of hash functions, while processing additional instructions. The processor deletes the first bit array and the first set of hash functions in response to detecting that the second bit array and the second set of hash functions have each been generated. Some examples process a second invalidation operation with the second set of hash functions and the second bit array. Updating cache devices includes a processor to detect a first set of hash functions and a first bit array corresponding to elements of a cache. In some examples, the processor detects a first instruction to add a new element to the cache and modify the first bit array based on ...More ...Less
5 US10552288B2
Health-aware garbage collection in a memory system
Publication/Patent Number: US10552288B2 Publication Date: 2020-02-04 Application Number: 15/376,309 Filing Date: 2016-12-12 Inventor: Tomic, Sasa   Pletka, Roman A.   Assignee: International Business Machines Corporation   IPC: G06F12/02 Abstract: A data storage system includes a controller that controls a non-volatile memory array including a plurality of garbage collection units of physical memory. For each of the plurality of garbage collections units storing valid data, the controller determines an invalidation metric and a health-based adjustment of the invalidation metric. The controller selects a garbage collection unit on which to perform garbage collection from among a plurality of garbage collections units predominately based on the invalidation metric for the garbage collection unit and also based on the health-based adjustment for the garbage collection unit. In response to selection of the garbage collection unit, the controller performing garbage collection for the garbage collection unit. A data storage system includes a controller that controls a non-volatile memory array including a plurality of garbage collection units of physical memory. For each of the plurality of garbage collections units storing valid data, the controller determines an invalidation metric ...More ...Less
6 US10546147B1
Uncertain file system
Publication/Patent Number: US10546147B1 Publication Date: 2020-01-28 Application Number: 15/659,589 Filing Date: 2017-07-25 Inventor: Engler, Joseph J.   Meis, Aaron M.   Assignee: Rockwell Collins, Inc.   IPC: G06F12/02 Abstract: A file system stores files in a location base on deterministic nonlinear functions using certain initial conditions of the files creation. The file is chunked and encrypted according to one of a set of encryption algorithms based on the initial conditions. Only the file name and associated initial conditions are stored; the initial location and encryption algorithm are not stored and therefore not retrievable. The file system periodically relocates the files based on one of a set of algorithms based on the initial conditions such that even if the initial location where know, the file would still be irretrievable without knowing the relation between the initial conditions and relocation algorithm. During retrieval, the system uses the stored initial conditions to identify the initial location, relocation algorithm, and encryption algorithm. A file system stores files in a location base on deterministic nonlinear functions using certain initial conditions of the files creation. The file is chunked and encrypted according to one of a set of encryption algorithms based on the initial conditions. Only the file name and ...More ...Less
7 US10545862B2
Memory system and method for controlling nonvolatile memory
Publication/Patent Number: US10545862B2 Publication Date: 2020-01-28 Application Number: 15/913,987 Filing Date: 2018-03-07 Inventor: Kanno, Shinichi   Yoshida, Hideki   Assignee: Toshiba Memory Corporation   IPC: G06F12/02 Abstract: According to one embodiment, a memory system determine both of a first block to which data from a host is to be written and a first location of the first block, when receiving a write request to designate a first logical address from the host. The memory system writes the data from the host to the first location of the first block. The memory system notifies the host of the first logical address, a first block number designating the first block, and a first in-block offset indicating an offset from a leading part of the first block to the first location by a multiple of grain having a size different from a page size. According to one embodiment, a memory system determine both of a first block to which data from a host is to be written and a first location of the first block, when receiving a write request to designate a first logical address from the host. The memory system writes the data ...More ...Less
8 US10545700B2
Memory management method, memory storage device and memory control circuit unit
Publication/Patent Number: US10545700B2 Publication Date: 2020-01-28 Application Number: 16/004,444 Filing Date: 2018-06-11 Inventor: Kuo, Che-yueh   Li, Wen-jin   Assignee: PHISON ELECTRONICS CORP.   IPC: G06F12/00 Abstract: A memory management method for a memory storage device including a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The method includes: performing a data merge operation for at least one physical unit of the rewritable non-volatile memory module according to a write command from a host system; and adjusting times of performing the data merge operation according to a dispersion rate of a plurality of logical units corresponding to first data stored in at least one first-type physical unit of the rewritable non-volatile memory module. A memory management method for a memory storage device including a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The method includes: performing a data merge operation for at least one physical unit of the rewritable ...More ...Less
9 US10540102B2
Physical media aware spacially coupled journaling and replay
Publication/Patent Number: US10540102B2 Publication Date: 2020-01-21 Application Number: 15/282,295 Filing Date: 2016-09-30 Inventor: Peterson, Phillip   Baryudin, Leonid   Sladic, Daniel   Biswas, Sujan   Assignee: AMAZON TECHNOLOGIES, INC.   IPC: G06F11/00 Abstract: An indirection mapping data structure can maintain a mapping between logical block addresses used by a host computer and physical data storage locations on a solid state drive. Changes to the indirection mapping data structure can be stored in journals. When a journal is full, the journal can be stored to a predetermined location on the cluster block determined based on the number of entries stored by the journal, leading to a number of journals scattered throughout the cluster block at predetermined locations. Each physical chunk of media, whether written with data or marked as defective is journaled. Such a journaling scheme, where the journal locations are predetermined and each physical chunk of media is journaled is referred to as physical media-aware spatially coupled journaling. During replay the spatially coupled journals can be retrieved from the predefined locations within cluster blocks and used to rebuild the indirection mapping data structure. An indirection mapping data structure can maintain a mapping between logical block addresses used by a host computer and physical data storage locations on a solid state drive. Changes to the indirection mapping data structure can be stored in journals. When a journal is full ...More ...Less
10 US10528737B2
Randomized heap allocation
Publication/Patent Number: US10528737B2 Publication Date: 2020-01-07 Application Number: 15/834,588 Filing Date: 2017-12-07 Inventor: Zuckerbraun, Simon   Hariri, Abdul Aziz   Gorenc, Brian Thomas   Assignee: Trend Micro Incorporated   IPC: H04L29/06 Abstract: Examples relate to randomized heap allocation. One example enables creating a set of heaps for an application; allocating an array for the application, wherein the application comprises a set of object types, the array comprises a set of elements, and each element of the array is associated with a unique object type of the set of object types; and initializing the array by: iterating over the array to associate each element of the array with a randomly chosen heap of the set of heaps. Examples relate to randomized heap allocation. One example enables creating a set of heaps for an application; allocating an array for the application, wherein the application comprises a set of object types, the array comprises a set of elements, and each element of the array ...More ...Less
11 US10528280B1
Tombstones for no longer relevant deduplication entries
Publication/Patent Number: US10528280B1 Publication Date: 2020-01-07 Application Number: 15/420,726 Filing Date: 2017-01-31 Inventor: Sandvig, Cary A.   Sapuntzakis, Constantine P.   Wang, Feng   Assignee: Pure Storage, Inc.   IPC: G06F12/00 Abstract: An implementation of the disclosure provides a system comprising a storage array comprising a plurality of data blocks and a storage controller coupled to the storage array. The storage controller comprising a processing device to identify a canonical instance of a data block in a vector associated with a deduplication map. The vector represents a plurality of updates to the deduplication map over a determined time period. A deduplication reference representing duplicate data of the data block in the storage array is select from the deduplication map. The deduplication reference is remapped in the deduplication map to point to the canonical instance. Based on the remapping, an entry in the deduplication map for the deduplication reference is updated with a record. Responsive to detecting that the entry is in a location associated with an original entry of the data block in the deduplication map, delete the entry with the record. An implementation of the disclosure provides a system comprising a storage array comprising a plurality of data blocks and a storage controller coupled to the storage array. The storage controller comprising a processing device to identify a canonical instance of a data block in ...More ...Less
12 US10528329B1
Methods, systems, and computer program product for automatic generation of software application code
Publication/Patent Number: US10528329B1 Publication Date: 2020-01-07 Application Number: 15/499,148 Filing Date: 2017-04-27 Inventor: Doyle, Timothy B.   Assignee: INTUIT INC.   IPC: G06F3/06 Abstract: Disclosed are techniques for automatic generation of software application code. These techniques identify or generate a data model in a first programming language. At least one rule is identified or generated from the data model. This at least one rule is tokenized into a plurality of subparts based at least in part upon a second programming language. A rule hierarchy at which the plurality of sub-parts is located is determined based in part or in whole upon a corresponding class hierarchy of a class with which the at least one rule is associated. A transformed data model is generated in the second programming language using at least the plurality of sub-parts and the rule hierarchy. Disclosed are techniques for automatic generation of software application code. These techniques identify or generate a data model in a first programming language. At least one rule is identified or generated from the data model. This at least one rule is tokenized into a ...More ...Less
13 US10564879B2
Memory system and operation method for storing and merging data with different unit sizes
Publication/Patent Number: US10564879B2 Publication Date: 2020-02-18 Application Number: 16/043,714 Filing Date: 2018-07-24 Inventor: Byun, Eu-joon   Assignee: SK hynix Inc.   IPC: G06F3/06 Abstract: A memory system may include: a memory device including a plurality of memory blocks, each including a plurality of pages for storing data; and a controller including a first memory, suitable for storing segments of data corresponding to a plurality of commands received from a host, in the first memory, storing the segments stored in the first memory, in first memory blocks among the memory blocks by a first unit size, in correspondence to data sizes and data types of the segments, and storing the segments stored in the first memory blocks, in second memory blocks among the memory blocks by a second unit size. A memory system may include: a memory device including a plurality of memory blocks, each including a plurality of pages for storing data; and a controller including a first memory, suitable for storing segments of data corresponding to a plurality of commands received from a ...More ...Less
14 US10564860B2
Semiconductor storage device and controller
Publication/Patent Number: US10564860B2 Publication Date: 2020-02-18 Application Number: 16/158,240 Filing Date: 2018-10-11 Inventor: Maejima, Hiroshi   Assignee: Toshiba Memory Corporation   IPC: G06F3/06 Abstract: A semiconductor storage device includes memory cells, select transistors, memory strings, first and second blocks, word lines, and select gate lines. In the memory string, the current paths of plural memory cells are connected in series. When data are written in a first block, after a select gate line connected to the gate of a select transistor of one of the memory strings in the first block is selected, the data are sequentially written in the memory cells in the memory string connected to the selected select gate line. When data are written in the second block, after a word line connected to the control gates of memory cells of different memory strings in the second block is selected, the data are sequentially written in the memory cells of the different memory strings in the second block which have their control gates connected to the selected word line. A semiconductor storage device includes memory cells, select transistors, memory strings, first and second blocks, word lines, and select gate lines. In the memory string, the current paths of plural memory cells are connected in series. When data are written in a first block ...More ...Less