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No. Publication Number Title Publication/Patent Number Publication/Patent Number Publication Date Publication Date
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1 US10586039B2
Information processing apparatus
Publication/Patent Number: US10586039B2 Publication Date: 2020-03-10 Application Number: 16/111,694 Filing Date: 2018-08-24 Inventor: Morizumi, Yoshihisa   Assignee: FUJITSU LIMITED   IPC: G06F21/52 Abstract: An information processing apparatus includes a memory and a processor. The memory stores a first string of error detection codes each corresponding to a used partial area of a stack area allocated to a program. The processor generates, when execution of the program is interrupted, a differential string of error detection codes each corresponding to a used partial area of a difference between used partial areas at the time of generating the first string and used partial areas at the interruption. The processor obtains a second string of error detection codes by reflecting the differential string to the first string. The processor generates, when the execution of the program is resumed, a third string of error detection codes each corresponding to a used partial area of the stack area at the resumption. The processor detects stack destruction based on collation between the second string and the third string. An information processing apparatus includes a memory and a processor. The memory stores a first string of error detection codes each corresponding to a used partial area of a stack area allocated to a program. The processor generates, when execution of the program is ...More ...Less
2 US10645105B2
Network attack detection method and device
Publication/Patent Number: US10645105B2 Publication Date: 2020-05-05 Application Number: 15/745,057 Filing Date: 2016-08-17 Inventor: Shen, Junli   Assignee: NSFOCUS INFORMATION TECHNOLOGY CO., LTD.   NSFOCUS TECHNOLOGIES, INC.   IPC: G06F11/00 Abstract: Provided are a network attack detection method and device. The method comprises: carrying out word segmentation to a character string to be detected and obtain words; determining the tuples corresponding to the to-be-detected character string; determining whether, in an attack model database, there are model tuples corresponding to the tuples, and whether there are model words corresponding to the first one of these words, the model tuples, the occurrence probability of each model tuple; if there are, acquiring the corresponding model tuples and the occurrence probability of the corresponding model words, and determining, according to the occurrence probability of the corresponding model tuples and the occurrence probability of the corresponding model words, the attack probability corresponding to the to-be-detected character string; and if the attack probability is larger than or equal to a preset probability threshold, determining that the to-be-detected character string is a character string having an attack behavior. Provided are a network attack detection method and device. The method comprises: carrying out word segmentation to a character string to be detected and obtain words; determining the tuples corresponding to the to-be-detected character string; determining whether, in an attack ...More ...Less
3 US10659324B2
Application monitoring prioritization
Publication/Patent Number: US10659324B2 Publication Date: 2020-05-19 Application Number: 15/173,477 Filing Date: 2016-06-03 Inventor: Pang, Jackson Ngoc Ki   Yadav, Navindra   Gupta, Anubhav   Gandham, Shashidhar   Rao, Supreeth Hosur Nagesh   Gupta, Sunil Kumar   Assignee: CISCO TECHNOLOGY, INC.   IPC: G08B23/00 Abstract: An approach for establishing a priority ranking for endpoints in a network. This can be useful when triaging endpoints after an endpoint becomes compromised. Ensuring that the most critical and vulnerable endpoints are triaged first can help maintain network stability and mitigate damage to endpoints in the network after an endpoint is compromised. The present technology involves determining a criticality ranking and a secondary value for a first endpoint in a datacenter. The criticality ranking and secondary value can be combined to form priority ranking for the first endpoint which can then be compared to a priority ranking for a second endpoint to determine if the first endpoint or the second endpoint should be triaged first. An approach for establishing a priority ranking for endpoints in a network. This can be useful when triaging endpoints after an endpoint becomes compromised. Ensuring that the most critical and vulnerable endpoints are triaged first can help maintain network stability and ...More ...Less
4 EP3230876B1
STORAGE SYSTEMS
Publication/Patent Number: EP3230876B1 Publication Date: 2020-01-15 Application Number: 15890681.8 Filing Date: 2015-04-30 Inventor: Paul, Reny   Tharakraj, Karthick   Assignee: Hewlett-Packard Development Company, L.P.   IPC: G06F12/16
5 EP3644191A1
MEMORY SYSTEM AND ELECTRONIC DEVICE
Publication/Patent Number: EP3644191A1 Publication Date: 2020-04-29 Application Number: 18820023.2 Filing Date: 2018-02-02 Inventor: Iwasaki, Yukio   Assignee: Kyocera Document Solutions Inc.   IPC: G06F12/16 Abstract: Life of a non-volatile memory is extended without increasing processing time due to turning power ON/OFF. An EEPROM (115) stores counter information and setting information, a first RAM (116) and a second RAM (117) store counter information and setting information, a memory management unit (118) manages a storage area in the first RAM (116) for the counter information and setting information so as to be updatable and manages a storage area in the second RAM (117) for the counter information and setting information so as not to be updatable, and a system control unit (122), when a change in contents of the counter information and the setting information occurs, rewrites the counter information and the setting information in the first RAM (116) in accordance to the changed contents, and when the power is turned OFF, reads and compares the counter information and the setting information in the first RAM (116) with the counter information and the setting information in the second RAM (117), and writes only different data to the EEPROM (115). Life of a non-volatile memory is extended without increasing processing time due to turning power ON/OFF. An EEPROM (115) stores counter information and setting information, a first RAM (116) and a second RAM (117) store counter information and setting information, a memory ...More ...Less
6 US2020019516A1
Primary Data Storage System with Staged Deduplication
Publication/Patent Number: US2020019516A1 Publication Date: 2020-01-16 Application Number: 16/360,010 Filing Date: 2019-03-21 Inventor: Sobolewski, Sebastian Piotr   Long, Kelly E.   Ashmore, Paul A.   Assignee: NexGen Storage, Inc.   IPC: G06F12/16 Abstract: The invention is directed to a primary data storage system for use in a computer network in which a network allows user computers to transfer data to and/or from the primary data storage system. In one embodiment of the invention, the storage processor operates to analyze the data associated with write block commands that relate to different storage locations in a data store system that is associated with the primary data storage system so as to identify the potential writing of the block(s) of the same data to the data store system and prevent the writing of such blocks of data. The invention is directed to a primary data storage system for use in a computer network in which a network allows user computers to transfer data to and/or from the primary data storage system. In one embodiment of the invention, the storage processor operates to analyze the ...More ...Less
7 CN105786400B
一种异构混合内存组件、系统及存储方法
Title (English): A Heterogeneous Mixed Memory Component, System and Storage Method
Publication/Patent Number: CN105786400B Publication Date: 2020-01-31 Application Number: 201410822643.4 Filing Date: 2014-12-25 Inventor: 庞观士   薛英仪   陈志列   王志远   沈航   梁艳妮   徐成泽   Assignee: 研祥智能科技股份有限公司   IPC: G06F3/06 Abstract: 本发明公开了一种异构混合内存组件、系统及存储方法,该异构混合内存组件包括:内存控制器用于接收处理器的写/读请求,根据写/读请求中的地址信息检测处理器访问的页面所对应的单位空间,控制数据从处理器通过缓冲区写入至存储单元阵列,或控制数据从存储单元阵列通过缓冲区读出至处理器;存储单元阵列,用于按照第一存储类型并以多个页面的方式存储写入/读出的数据;缓冲区,用于按照第二存储类型并设置对应于多个页面的多个单位空间存储写入/读出的数据,第二存储方式的读写速率大于第一存储方式的读写速率。该发明的有益效果为:外部存储设备与内存共享同等的数据带宽,而不再通过IO访问,大幅度提升外存的访问效率。 本发明公开了一种异构混合内存组件、系统及存储方法,该异构混合内存组件包括:内存控制器用于接收处理器的写/读请求,根据写/读请求中的地址信息检测处理器访问的页面所对应的单位空间,控制数据从处理器通过缓冲区写入至存储单元阵列,或控制数据从存储单元阵列通过缓冲区读出至处理器;存储单元阵列,用于按照第一存储类型并以多个页面的方式存储写入/读出的数据;缓冲区,用于按照第二存储类型并设置对应于多个页面的多个单位空间存储写入/读出的数据,第二存储方式的读写速率大于第一存储方式的读写速率。该发明的有益效果为:外部存储设备与内存共享同等的数据带宽,而不再通过IO访问,大幅 ...More ...Less
8 US2020042357A1
OS/HYPERVISOR-BASED PERSISTENT MEMORY
Publication/Patent Number: US2020042357A1 Publication Date: 2020-02-06 Application Number: 16/584,880 Filing Date: 2019-09-26 Inventor: Peddamallu, Venkata Subhash Reddy   Tati, Kiran   Venkatasubramanian, Rajesh   Subrahmanyam, Pratap   Assignee: VMware, Inc.   IPC: G06F9/50 Abstract: Techniques for implementing OS/hypervisor-based persistent memory are provided. In one embodiment, an OS or hypervisor running on a computer system can allocate a portion of the volatile memory of the computer system as a persistent memory allocation. The OS/hypervisor can further receive a signal from the computer system's BIOS indicating an AC power loss or cycle event and, in response to the signal, can save data in the persistent memory allocation to a nonvolatile backing store. Then, upon restoration of AC power to the computer system, the OS/hypervisor can restore the saved data from the nonvolatile backing store to the persistent memory allocation. Techniques for implementing OS/hypervisor-based persistent memory are provided. In one embodiment, an OS or hypervisor running on a computer system can allocate a portion of the volatile memory of the computer system as a persistent memory allocation. The OS/hypervisor can ...More ...Less
9 CN110865902A
一种管道导航参考轨道存储上注诊断的批处理方法
Title (English): A Batch Processing Method for Injection Diagnosis on Pipeline Navigation Reference Track Storage
Publication/Patent Number: CN110865902A Publication Date: 2020-03-06 Application Number: 201911025089.6 Filing Date: 2019-10-25 Inventor: 贾艳胜   杨盛庆   王禹   崔佳   王文妍   完备   何煜斌   朱郁斐   王嘉轶   陈桦   Assignee: 上海航天控制技术研究所   IPC: G06F11/10 Abstract: 本发明公开了一种卫星姿轨控分系统管道导航参考轨道存储上注诊断的批处理方法,该方法将参考轨道数据存储至星载计算机的EEPROM三份不同地址中,参考轨道数据按照CCSDS数据格式进行组帧,星载系统首先进行三取二诊断,诊断正常则时按照数据格式进行反解,三取二异常则自动修复异常数据包,之后对数据包进行反解,反解失败则给出异常状态,并停止管道导航。本发明软件复位或星载计算机断电后数据不丢失,且在轨期间更改参考轨道的所有过程均由软件批处理完成。本发明既可以用于地面试验时管道航道的参考轨道上注,也可以用于卫星在轨运行期间在不复位且不影响卫星姿态轨道控制的前提下完成参考轨道的上注。 本发明公开了一种卫星姿轨控分系统管道导航参考轨道存储上注诊断的批处理方法,该方法将参考轨道数据存储至星载计算机的EEPROM三份不同地址中,参考轨道数据按照CCSDS数据格式进行组帧,星载系统首先进行三取二诊断,诊断正常则时按照数据格式进行反解,三取二异常则自动修复异常数据包,之后对数据包进行反解,反解失败则给出异常状态,并停止管道导航。本发明软件复位或星载计算机断电后数据不丢失,且在轨期间更改参考轨道的所有过程均由软件批处理完成。本发明既可以用于地面试验时管道航道的参考轨道上注,也可以用于卫星在轨运行期间在不复位且不影响卫星姿态轨道控制的前提下完成参考 ...More ...Less
10 US10673893B2
Isolating a source of an attack that originates from a shared computing environment
Publication/Patent Number: US10673893B2 Publication Date: 2020-06-02 Application Number: 15/252,453 Filing Date: 2016-08-31 Inventor: Lara, Juan G.   Mcgloin, Mark A.   Pieczul, Olgierd S.   Topete, Ralph L.   Assignee: International Business Machines Corporation   IPC: G08B23/00 Abstract: A method and associated systems for isolating a source of an attack that originates from a shared computing environment. A computer-security system tags outgoing packets originating from within the shared computing environment in a tamper-proof manner in order to identify which tenant of the shared environment is the true source of each packet. If one of those tenants transmits malicious packets to an external recipient, either because the tenant has malicious intent or becomes infected with malware, the transmitted malicious packets' tags allow the recipient to determine which tenant is the source of the unwanted transmissions. The recipient may then block further communications from the problematic tenant without blocking communications from other tenants of the shared environment. A method and associated systems for isolating a source of an attack that originates from a shared computing environment. A computer-security system tags outgoing packets originating from within the shared computing environment in a tamper-proof manner in order to identify which ...More ...Less
11 US10686808B2
Notification for reassembly-free file scanning
Publication/Patent Number: US10686808B2 Publication Date: 2020-06-16 Application Number: 16/031,600 Filing Date: 2018-07-10 Inventor: Dubrovsky, Aleksandr   Korsunsky, Igor   Yanovsky, Roman   Yanovsky, Boris   Assignee: SONICWALL INC.   IPC: G06F11/00 Abstract: Techniques for notification of reassembly-free file scanning are described herein. According to one embodiment, a first request for accessing a document provided by a remote node is received from a client. In response to the first request, it is determined whether a second request previously for accessing the document of the remote node indicates that the requested document from the remote node contains offensive data. If the requested document contains offensive data, a message is returned to the client, without accessing the requested document of the remote node, indicating that the requested document is not delivered to the client. Techniques for notification of reassembly-free file scanning are described herein. According to one embodiment, a first request for accessing a document provided by a remote node is received from a client. In response to the first request, it is determined whether a second ...More ...Less
12 US10540496B2
Dynamic re-composition of patch groups using stream clustering
Publication/Patent Number: US10540496B2 Publication Date: 2020-01-21 Application Number: 15/721,566 Filing Date: 2017-09-29 Inventor: Bulut, Muhammed Fatih   Hwang, Jinho   Sreedhar, Vugranam C.   Zeng, Sai   Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION   IPC: G06F12/16 Abstract: Techniques for dynamic server groups that can be patched together using stream clustering algorithms, and learning components in order to reuse the repeatable patterns using machine learning are provided herein. In one example, in response to a first risk associated with a first server device, a risk assessment component patches a server group to mitigate a vulnerability of the first server device and a second server device, wherein the server group is comprised of the first server device and the second server device. Additionally, a monitoring component monitors data associated with a second risk to the server group to mitigate the second risk to the server group. Techniques for dynamic server groups that can be patched together using stream clustering algorithms, and learning components in order to reuse the repeatable patterns using machine learning are provided herein. In one example, in response to a first risk associated with a first ...More ...Less
13 US10609054B2
Methods, systems, and computer readable media for monitoring, adjusting, and utilizing latency associated with accessing distributed computing resources
Publication/Patent Number: US10609054B2 Publication Date: 2020-03-31 Application Number: 15/482,672 Filing Date: 2017-04-07 Inventor: Jackson, Stephen Samuel   Assignee: KEYSIGHT TECHNOLOGIES SINGAPORE (SALES) PTE. LTD.   IPC: G06F11/00 Abstract: Methods, systems, and computer readable media for monitoring, adjusting, and utilizing latency associated with accessing distributed computing resources are disclosed. One method includes measuring a first latency associated with accessing a first computing resource located at a first site. The method further includes the measuring a second latency associated with accessing a second computing resource located at a second site different from the first site. The method further includes selectively impairing transmission of packets to or processing of packets by at least one of the first and second computing resources in accordance with a performance, network security, or diagnostic goal. Methods, systems, and computer readable media for monitoring, adjusting, and utilizing latency associated with accessing distributed computing resources are disclosed. One method includes measuring a first latency associated with accessing a first computing resource located at a ...More ...Less
14 CN110825203A
适用于电脑机箱的应急电源装置
Title (English): Emergency power supply for computer case
Publication/Patent Number: CN110825203A Publication Date: 2020-02-21 Application Number: 201910928248.7 Filing Date: 2019-09-28 Inventor: 孟琪   Assignee: 徐州市奥仕捷电子机箱有限公司   IPC: G06F1/26 Abstract: 本发明是一种适用于电脑机箱的应急电源装置,包括主设备盒、硬盘数据接口、电源接口、左设备挂载条、右设备挂载条、蜂鸣器和工作状态指示灯,所述的主设备盒一侧表面开两个矩形通孔分别安装硬盘数据接口和电源接口,主设备盒表面开圆形通孔安装蜂鸣器,主设备盒表面开通孔安装工作状态指示灯,主设备盒一侧表面通过螺丝安装左设备挂载条,主设备盒一侧表面通过螺丝安装右设备挂载条,可以在突然断电的情况下紧急对设备进行供电。
15 CN209980143U
一种支持固态硬盘热插拔功能的结构
Title (English): A structure that supports hot-plug function of solid state hard disk
Publication/Patent Number: CN209980143U Publication Date: 2020-01-21 Application Number: 201920615379.5 Filing Date: 2019-04-29 Inventor: 韩向伟   郭桑   陈高鹏   韦拔新   吴乃亮   黄飞帆   Assignee: 深圳市南航电子工业有限公司   IPC: G06F1/18 Abstract: 本实用新型涉及存储领域,公开了一种支持固态硬盘热插拔功能的结构,该结构包括锁止机构、触发机构和主体,锁止机构与触发机构均安装于主体上,锁止机构从开始解锁到解锁完成的时间内,触发机构发出信号。通过在固态硬盘从开始解锁到解锁结束前的时间段内发出一个信号,控制待取出的固态硬盘在弹出之前停止读写和保护文件,实现固态硬盘的热插拔功能,结构简单,适用性强。
16 US10664343B2
Memory controller, non-volatile memory, and method of controlling memory controller
Publication/Patent Number: US10664343B2 Publication Date: 2020-05-26 Application Number: 16/072,831 Filing Date: 2016-12-01 Inventor: Terada, Haruhiko   Assignee: Sony Corporation   IPC: G06F11/10 Abstract: To suppress an increase in a voltage drop in a non-volatile memory including a variable resistive element installed therein. A memory controller includes a voltage drop amount estimating unit and an encoding unit. The voltage drop amount estimating unit estimates a voltage drop amount from a wiring resistance of a wiring up to a memory cell and a leakage current occurring in the memory cell when original data is caused to be held in the memory cell. The encoding unit performs a predetermined encoding process on the original data in a case in which the estimated voltage drop amount exceeds a predetermined threshold value. To suppress an increase in a voltage drop in a non-volatile memory including a variable resistive element installed therein. A memory controller includes a voltage drop amount estimating unit and an encoding unit. The voltage drop amount estimating unit estimates a voltage drop ...More ...Less