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No. Publication Number Title Publication/Patent Number Publication/Patent Number Publication Date Publication Date
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1 US10579290B2
Option code providing circuit and providing method thereof
Publication/Patent Number: US10579290B2 Publication Date: 2020-03-03 Application Number: 15/077,916 Filing Date: 2016-03-23 Inventor: Chan, Johnny   Lin, Chi-shun   Assignee: Winbond Electronics Corp.   IPC: G06F3/06 Abstract: An option code providing circuit includes a plurality of resistive random access memory cells and a controller. The controller determines whether to provide a control signal to operate a heavy forming operation on the resistive random access memory cells or not. Wherein, the controller performs a read operation on the resistive random access memory cells to determine a bit number of the resistive random memory cell which is heavy formed, and the option code is determined by the bit number of resistive random access memory cell which is heavy formed or a bit number of the resistive random access memory cell which is not heavy formed. An option code providing circuit includes a plurality of resistive random access memory cells and a controller. The controller determines whether to provide a control signal to operate a heavy forming operation on the resistive random access memory cells or not. Wherein, the ...More Less
2 US10608048B2
Select device for memory cell applications
Publication/Patent Number: US10608048B2 Publication Date: 2020-03-31 Application Number: 16/123,073 Filing Date: 2018-09-06 Inventor: Wells, David H.   Cardon, Christopher D.   Onal, Caner   Assignee: Micron Technology, Inc.   IPC: G11C11/00 Abstract: The present disclosure includes select devices and methods of using select device for memory cell applications. An example select device includes a first electrode having a particular geometry, a semiconductor material formed on the first electrode and a second electrode having the particular geometry with formed on the semiconductor material, wherein the select device is configured to snap between resistive states in response to signals that are applied to the select device. The present disclosure includes select devices and methods of using select device for memory cell applications. An example select device includes a first electrode having a particular geometry, a semiconductor material formed on the first electrode and a second electrode having ...More Less
3 US10600845B2
Memory device
Publication/Patent Number: US10600845B2 Publication Date: 2020-03-24 Application Number: 16/172,088 Filing Date: 2018-10-26 Inventor: Murooka, Kenichi   Assignee: TOSHIBA MEMORY CORPORATION   IPC: H01L27/24 Abstract: According to one embodiment, a memory device includes first to third interconnects, memory cells, and selectors. The first to third interconnects are provided along first to third directions, respectively. The memory cells includes variable resistance layers formed on two side surfaces, facing each other in the first direction, of the third interconnects. The selectors couple the third interconnects with the first interconnects. One of the selectors includes a semiconductor layer provided between associated one of the third interconnects and associated one of the first interconnects, and gates formed on two side surfaces of the semiconductor layer facing each other in the first direction with gate insulating films interposed therebetween. According to one embodiment, a memory device includes first to third interconnects, memory cells, and selectors. The first to third interconnects are provided along first to third directions, respectively. The memory cells includes variable resistance layers formed on two side ...More Less
4 US10636843B2
Memory device and method of manufacturing the same
Publication/Patent Number: US10636843B2 Publication Date: 2020-04-28 Application Number: 16/281,486 Filing Date: 2019-02-21 Inventor: Jeong, Ji-hyun   Koh, Gwan-hyeob   Kang, Dae-hwan   Assignee: SAMSUNG ELECTRONICS CO., LTD.   IPC: H01L27/24 Abstract: A memory device includes a first electrode line layer including a plurality of first electrode lines extending on a substrate in a first direction and being spaced apart from each other, a second electrode line layer including a plurality of second electrode lines extending on the first electrode line layer in a second direction that is different from the first direction and being spaced apart from each other, and a memory cell layer including a plurality of first memory cells located at a plurality of intersections between the plurality of first electrode lines and the plurality of second electrode lines, each first memory cell including a selection device layer, an intermediate electrode and a variable resistance layer that are sequentially stacked. A side surface of the variable resistance layer is perpendicular to a top surface of the substrate or inclined to be gradually wider toward an upper portion of the variable resistance layer. The first memory cell has a side surface slope so as to have a width gradually decreasing toward its upper portion. A memory device includes a first electrode line layer including a plurality of first electrode lines extending on a substrate in a first direction and being spaced apart from each other, a second electrode line layer including a plurality of second electrode lines extending on ...More Less
5 US10629247B2
Read threshold adjustment using reference data
Publication/Patent Number: US10629247B2 Publication Date: 2020-04-21 Application Number: 15/851,537 Filing Date: 2017-12-21 Inventor: Kale, Salil   Kv, Shreejith   Puthoor, Aneesh   S, Gopu   K, Narayan   Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.   IPC: G11C29/00 Abstract: Apparatuses, systems, and methods are disclosed for read threshold adjustment using reference data for non-volatile memory. An apparatus may include an array of non-volatile memory cells and a controller. A controller may be configured to write a predetermined reference data pattern to a region of an array. A controller may be configured to read reference data from a region. A controller may be configured to set one or more read thresholds based on identifying differences between reference data and a predetermined reference data pattern. Apparatuses, systems, and methods are disclosed for read threshold adjustment using reference data for non-volatile memory. An apparatus may include an array of non-volatile memory cells and a controller. A controller may be configured to write a predetermined reference data ...More Less
6 US10622068B2
Electronic circuit and data storage system
Publication/Patent Number: US10622068B2 Publication Date: 2020-04-14 Application Number: 16/233,351 Filing Date: 2018-12-27 Inventor: Price, Richard   Ramsdale, Catherine   Assignee: PRAGMATIC PRINTING LTD   IPC: G11C13/04 Abstract: A method of manufacturing an electronic circuit comprises: providing an electronic circuit having a first configuration in which the circuit comprises a resistive element having a first resistance, and irradiating at least a part of the resistive element with electromagnetic radiation to change the resistance of the resistive element from the first resistance to a second resistance, the second resistance being lower than the first resistance. A method of storing data comprises: receiving a piece of data to be stored; determining a number according to the data; and irradiating at least part of a resistive element with that number of pulses of electromagnetic radiation to change a resistance of the resistive element from a first resistance to a second resistance, the second resistance being lower than the first resistance. A difference between the first resistance and the second resistance is dependent on the number. Corresponding circuits and data storage systems are disclosed. A method of manufacturing an electronic circuit comprises: providing an electronic circuit having a first configuration in which the circuit comprises a resistive element having a first resistance, and irradiating at least a part of the resistive element with electromagnetic ...More Less
7 US10622555B2
Film scheme to improve peeling in chalcogenide based PCRAM
Publication/Patent Number: US10622555B2 Publication Date: 2020-04-14 Application Number: 16/207,506 Filing Date: 2018-12-03 Inventor: Trinh, Hai-dang   Liang, Chin-wei   Lin, Hsing-lien   Jiang, Fa-shen   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L45/00 Abstract: A phase change memory (PCM) device including a PCM structure with a getter metal layer disposed between a phase change element (PCE) and a dielectric layer is provided. The PCM structure includes a dielectric layer, a bottom electrode, a via, a PCE, and a getter metal layer. The dielectric layer is disposed over a substrate. The bottom electrode overlies the dielectric layer. The via extends through the dielectric layer, from a bottom surface of the dielectric layer to a top surface of the dielectric layer. The phase change element overlies the bottom electrode. The getter metal layer is disposed between the dielectric layer and the PCE. A phase change memory (PCM) device including a PCM structure with a getter metal layer disposed between a phase change element (PCE) and a dielectric layer is provided. The PCM structure includes a dielectric layer, a bottom electrode, a via, a PCE, and a getter metal layer. The ...More Less
8 US10656231B1
Memory Arrays
Publication/Patent Number: US10656231B1 Publication Date: 2020-05-19 Application Number: 16/799,670 Filing Date: 2020-02-24 Inventor: Liu, Zengtao T.   Assignee: Micron Technology, Inc.   IPC: G11C11/00 Abstract: Some embodiments include memory arrays. The memory arrays can have global bitlines extending along a first horizontal direction, vertical local bitlines extending perpendicularly from the global bitlines, and wordlines extending along a second horizontal direction which is perpendicular to the first horizontal direction. The global bitlines may be subdivided into a first series at a first elevational level, and a second series at a second elevational level which is different from the first elevational level. The global bitlines of the first series can alternate with the global bitlines of the second series. There can be memory cell material directly between the wordlines and the vertical local bitlines. The memory cell material may form a plurality of memory cells uniquely addressed by wordline/global bitline combinations. Some embodiments include cross-point memory cell units that have areas of about 2F2. Some embodiments include memory arrays. The memory arrays can have global bitlines extending along a first horizontal direction, vertical local bitlines extending perpendicularly from the global bitlines, and wordlines extending along a second horizontal direction which is ...More Less
9 US10658587B2
CEM switching device
Publication/Patent Number: US10658587B2 Publication Date: 2020-05-19 Application Number: 16/169,372 Filing Date: 2018-10-24 Inventor: Reid, Kimberly Gay   Shifren, Lucian   Paz, De Araujo Carlos Alberto   Celinska, Jolanta Bozena   Assignee: Arm Limited   IPC: H01L45/00 Abstract: Subject matter herein disclosed relates to a method for the manufacture of a CEM switching device providing that the CEM layer comprises a doped metal compound substantially free from metal wherein ions of the same metal element are present in different oxidation states. The method may provide a CEM layer which is born on and capable of switching with operating voltages below 2.0V. Subject matter herein disclosed relates to a method for the manufacture of a CEM switching device providing that the CEM layer comprises a doped metal compound substantially free from metal wherein ions of the same metal element are present in different oxidation states. The ...More Less
10 US10614883B2
Resistance memory cell
Publication/Patent Number: US10614883B2 Publication Date: 2020-04-07 Application Number: 16/516,782 Filing Date: 2019-07-19 Inventor: Kellam, Mark D.   Bronner, Gary Bela   Assignee: Hefei Reliance Memory Limited   IPC: G11C13/00 Abstract: A resistance memory includes a resistance memory cell having a resistance memory element and a two-terminal access device in series. The two-terminal access device affects the current-voltage characteristic of the resistance memory cell. The resistance memory additionally includes a circuit to apply across the resistance memory cell a set pulse having a set polarity to set the resistance memory cell to a low-resistance state that is retained after application of the set pulse, a reset pulse having a reset polarity, opposite to the set polarity, to reset the resistance memory cell to a high-resistance state that is retained after application of the reset pulse, and a read pulse of the reset polarity and smaller in magnitude than the reset pulse to determine the resistance state of the resistance memory cell without changing the resistance state of the resistance memory cell. A resistance memory includes a resistance memory cell having a resistance memory element and a two-terminal access device in series. The two-terminal access device affects the current-voltage characteristic of the resistance memory cell. The resistance memory additionally ...More Less
11 US10535818B2
Resistance change memory device
Publication/Patent Number: US10535818B2 Publication Date: 2020-01-14 Application Number: 15/942,236 Filing Date: 2018-03-30 Inventor: Ha, Tae Jung   Assignee: SK HYNIX INC.   IPC: G11C11/16 Abstract: A resistance change memory device is provided. The resistance change memory device includes a lower electrode, a tunneling barrier layer disposed on the lower electrode, a resistance switching layer disposed on the tunneling barrier layer, an oxygen vacancy reservoir layer disposed on the resistance switching layer, and an upper electrode disposed on the oxygen vacancy reservoir layer. The oxygen vacancy reservoir layer is electrically conductive. A resistance change memory device is provided. The resistance change memory device includes a lower electrode, a tunneling barrier layer disposed on the lower electrode, a resistance switching layer disposed on the tunneling barrier layer, an oxygen vacancy reservoir layer ...More Less
12 US10529422B2
Method for programming 1-R resistive change element arrays
Publication/Patent Number: US10529422B2 Publication Date: 2020-01-07 Application Number: 16/260,080 Filing Date: 2019-01-28 Inventor: Bertin, Claude L.   Cleveland, Lee   Assignee: Nantero, Inc.   IPC: G11C11/00 Abstract: Methods for reading and programming one or more resistive change elements within a 1-R resistive change element array are disclosed. These methods include using measurement and storage elements to measure the electrical response of one or more selected cells within an array and then comparing that stored electrical response to the electrical response of a reference element within the array to determine the resistive state of the one or more selected cells. These methods also include programming methods wherein selectable current limiting elements are used to permit or inhibit programming currents from flowing through selected and unselected cells, respectively. These methods further include programing methods that use specific biasing of array lines to provide sufficient programing currents through only selected cells. Methods for reading and programming one or more resistive change elements within a 1-R resistive change element array are disclosed. These methods include using measurement and storage elements to measure the electrical response of one or more selected cells within an array and ...More Less
13 US10553793B2
Systems and methods for gated-insulator reconfigurable non-volatile memory devices
Publication/Patent Number: US10553793B2 Publication Date: 2020-02-04 Application Number: 16/367,637 Filing Date: 2019-03-28 Inventor: Jha, Rashmi   Rush, Andrew   Herrmann, Eric   Assignee: University of Cincinnati   IPC: G11C5/14 Abstract: Systems and methods of use and fabrication are described for a non-volatile resistive random access memory (RRAM) multi-terminal device including a first electrode, a second electrode, a metal oxide disposed between the first electrode and the second electrode, and an at least first gate configured to apply a voltage bias to change a resistive state in the metal oxide. Systems and methods of use and fabrication are described for a non-volatile resistive random access memory (RRAM) multi-terminal device including a first electrode, a second electrode, a metal oxide disposed between the first electrode and the second electrode, and an at least ...More Less
14 US10538618B2
Polymer based memristors
Publication/Patent Number: US10538618B2 Publication Date: 2020-01-21 Application Number: 15/869,607 Filing Date: 2018-01-12 Inventor: Gilroy, Joe B.   Fanchini, Giovanni   Paquette, Joseph A.   Ezugwu, Sabastine C.   Assignee: THE UNIVERSITY OF WESTERN ONTARIO   IPC: C08G61/02 Abstract: Disclosed herein are redox-active 6-oxoverdazyl polymers having structures (S1) and (S2) synthesized via ring-opening metathesis polymerization (ROMP) and their solution, bulk, and thin-film properties investigated. Detailed studies of the ROMP method employed confirmed that stable radical polymers with controlled molecular weights and narrow molecular weight distributions (Ð<1.2) were produced. Thermal gravimetric analysis of a representative example of the title polymers demonstrated stability up to 190° C., while differential scanning calorimetry studies revealed a glass transition temperature of 152° C. An ultrathin memristor device was produced using these polymers, namely a 10 nm homogeneous thin film of poly-[1,5-diisopropyl-3-(cis-5-norbornene-exo-2,3-dicarboxiimide)-6-oxoverdazyl] (P6OV), a poly-radical with three tunable charge states per each radical monomer: positive, neutral and negative. Disclosed herein are redox-active 6-oxoverdazyl polymers having structures (S1) and (S2) synthesized via ring-opening metathesis polymerization (ROMP) and their solution, bulk, and thin-film properties investigated. Detailed studies of the ROMP method employed confirmed that ...More Less
15 US10553644B2
Test circuit block, variable resistance memory device including the same, and method of forming the variable resistance memory device
Publication/Patent Number: US10553644B2 Publication Date: 2020-02-04 Application Number: 16/016,148 Filing Date: 2018-06-22 Inventor: Kang, Seok Joon   Em, Ho Seok   Assignee: Sk hynix Inc.   IPC: H01L27/24 Abstract: A test circuit block may include a first signal line, a second signal line, a high resistive path unit, and a low resistive path unit. The high resistive path unit may be connected between the first signal line and the second signal line. The low resistive path unit may have a resistance lower than that of the high resistive path unit. The low resistive path unit may be selectively connected in parallel with the high resistive path unit between the first signal line and the second signal line. A test circuit block may include a first signal line, a second signal line, a high resistive path unit, and a low resistive path unit. The high resistive path unit may be connected between the first signal line and the second signal line. The low resistive path unit may have a ...More Less
16 US10546636B2
Apparatuses and methods for accessing variable resistance memory device
Publication/Patent Number: US10546636B2 Publication Date: 2020-01-28 Application Number: 15/971,723 Filing Date: 2018-05-04 Inventor: Fantini, Paolo   Ielmini, Daniele   Ciocchini, Nicola   Assignee: Micron Technology, Inc.   IPC: G11C13/00 Abstract: The disclosed technology generally relates to memory apparatuses and methods of operating the same, and more particularly to a memory device having a controller configured to cause a write operation to be performed on a variable resistance memory cell, which includes application of two successive access pulses having opposite polarities, and methods of using the same. The disclosed technology generally relates to memory apparatuses and methods of operating the same, and more particularly to a memory device having a controller configured to cause a write operation to be performed on a variable resistance memory cell, which includes application ...More Less
17 US10559356B2
Memory circuit having concurrent writes and method therefor
Publication/Patent Number: US10559356B2 Publication Date: 2020-02-11 Application Number: 15/622,738 Filing Date: 2017-06-14 Inventor: Pelley, Perry H.   Roy, Anirban   Bhagavatheeswaran, Gayathri   Assignee: NXP USA, INC.   IPC: G11C11/00 Abstract: A memory circuit includes a plurality of memory tiles. Each memory tile in the plurality of memory tiles includes a plurality of bit cells and a control circuit coupled to the plurality of bit cells. The control circuit is configured to provide latched data to the plurality of bit cells during write operations. A first write control line is coupled to the control circuit in a first memory tile, and the first write control line is configured to initiate a first write operation in the first memory tile. And a second write control line is coupled to the control circuit in a second memory tile, and the second write control line configured to initiate a second write operation in the second memory tile. The second write operation may be initiated before the first write operation is completed. A memory circuit includes a plurality of memory tiles. Each memory tile in the plurality of memory tiles includes a plurality of bit cells and a control circuit coupled to the plurality of bit cells. The control circuit is configured to provide latched data to the plurality of ...More Less
18 US10559345B1
Address decoding circuit performing a multi-bit shift operation in a single clock cycle
Publication/Patent Number: US10559345B1 Publication Date: 2020-02-11 Application Number: 16/191,356 Filing Date: 2018-11-14 Inventor: Diamant, Ron   Cohen, Jonathan   Valfer, Elad   Assignee: Amazon Technologies, Inc.   IPC: G11C8/00 Abstract: A decoder is disclosed that is used to select an area of address space in an Integrated Circuit. The decoder uses a hardware shifting module that performs shift operations on constants. Such a structure reduces an overall area consumption of the shifting module. Additionally, the decoder can perform a multi-bit shift operation in a single clock cycle. A decoder is disclosed that is used to select an area of address space in an Integrated Circuit. The decoder uses a hardware shifting module that performs shift operations on constants. Such a structure reduces an overall area consumption of the shifting module. Additionally ...More Less
19 US10573375B1
Methods and circuitry for programming non-volatile resistive switches using varistors
Publication/Patent Number: US10573375B1 Publication Date: 2020-02-25 Application Number: 16/114,892 Filing Date: 2018-08-28 Inventor: He, Yue-song   Kurniawan, Rusli   Smolen, Richard G.   Pass, Christopher J.   Lee, Andy L.   Watt, Jeffrey T.   Liu, Anwen   Roy, Alok Nandini   Assignee: Intel Corporation   IPC: G11C11/413 Abstract: Integrated circuits with an array of programmable resistive switch elements are provided. A programmable resistive switch element may include two non-volatile resistive memory elements connected in series and two varistors. A first of the two varistors is used to program a top resistive memory element in the resistive switch element, whereas a second of the two varistors is used to program a bottom resistive memory element in the resistive switch element. Row and column drivers implemented using only thin gate oxide transistors are used to program a selected resistive switch in the array without violating a maximum voltage level that satisfies predetermined defects per million (DPM) reliability criteria. Integrated circuits with an array of programmable resistive switch elements are provided. A programmable resistive switch element may include two non-volatile resistive memory elements connected in series and two varistors. A first of the two varistors is used to program a top ...More Less
20 US10586591B2
High speed thin film two terminal resistive memory
Publication/Patent Number: US10586591B2 Publication Date: 2020-03-10 Application Number: 15/864,179 Filing Date: 2018-01-08 Inventor: Li, Ning   Sadana, Devendra   Assignee: International Business Machines Corporation   IPC: G11C13/00 Abstract: A high speed thin film two terminal resistive memory article of manufacture comprises a chargeable and dischargeable variable resistance thin film battery having a plurality of layers operatively associated with one another, the plurality of layers comprising in sequence, a cathode-side conductive layer, a cathode layer comprised of a material that can take up cations and discharge cations in a charging and discharging process, an electrolyte layer comprising the cations, a barrier layer, an anode layer, and an optional anode-side conductive layer, the barrier layer comprised of a material that substantially prevents the cations from combining with the anode layer. A high speed thin film two terminal resistive memory article of manufacture comprises a chargeable and dischargeable variable resistance thin film battery having a plurality of layers operatively associated with one another, the plurality of layers comprising in sequence, a ...More Less