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No. Publication Number Title Publication/Patent Number Publication/Patent Number Publication Date Publication Date
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1 US10545824B2
Selective error coding
Publication/Patent Number: US10545824B2 Publication Date: 2020-01-28 Application Number: 15/809,046 Filing Date: 2017-11-10 Inventor: Chinnakkonda, Vidyapoornachary Diyanesh Babu   Dell, Timothy J.   Gollub, Marc A.   Lingambudi, Anil B.   Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION   IPC: G06F11/10 Abstract: A system and method of performing selective error coding in memory management of a memory device are described. The method includes performing a process of detecting and correcting memory errors in the memory of the memory device either prior to or after a chip mark associated with the memory device is in place. The method also includes localizing hard errors of the memory device based on a second process of detecting the memory errors in the memory of the memory device, the hard errors being persistent memory errors that persist from the process of detecting and correcting the memory errors to the second process, determining an extent of the hard errors based on the localizing, and preventing placement of the chip mark or removing the chip mark after de-allocating one or more ranges of addresses based on a result of the determining the extent of the hard errors. A system and method of performing selective error coding in memory management of a memory device are described. The method includes performing a process of detecting and correcting memory errors in the memory of the memory device either prior to or after a chip mark associated ...More ...Less
2 US10528288B2
Three-dimensional stacked memory access optimization
Publication/Patent Number: US10528288B2 Publication Date: 2020-01-07 Application Number: 15/847,957 Filing Date: 2017-12-20 Inventor: Chinnakkonda, Vidyapoornachary Diyanesh B.   Deforge, John B.   Maule, Warren E.   Peterson, Kirk D.   Rangarajan, Sridhar H.   Sethuraman, Saravanan   Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION   IPC: G06F3/06 Abstract: An aspect includes receiving a request to access one or more memory devices in a stack of memory devices in a memory. Each of the memory devices are communicatively coupled to at least one other of the memory devices in the stack via a through silicon via (TSV). A current operating mode of the memory is determined in response to receiving the request. Based at least in part on the current operating mode of the memory being a first mode, a chip select switch is activated to provide access to exactly one of the memory devices in the stack of memory devices. Based at least in part on the current operating mode of the memory being a second mode, the chip select switch is activated to access all of the memory devices in the stack in parallel. The request is serviced using the activated chip select switch. An aspect includes receiving a request to access one or more memory devices in a stack of memory devices in a memory. Each of the memory devices are communicatively coupled to at least one other of the memory devices in the stack via a through silicon via (TSV). A current ...More ...Less
3 US10564900B2
Temperature variation compensation
Publication/Patent Number: US10564900B2 Publication Date: 2020-02-18 Application Number: 16/004,806 Filing Date: 2018-06-11 Inventor: Achtenberg, Stella   Sharon, Eran   Rozman, David   Eyal, Alon   Alrod, Idan   Lee, Dana   Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.   IPC: G11C7/00 Abstract: A data storage device includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller is operable to measure a first threshold voltage (Vt) of a memory cell under a first parameter at a read temperature and measure a second Vt of the memory cell under a second parameter at the read temperature in which the first parameter is different from the second parameter. A Vt correction term for the memory cell is determined based upon the first Vt measurement and the second Vt measurement. A read Vt of the memory cell is adjusted by using the Vt correction term. A data storage device includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller is operable to measure a first threshold voltage (Vt) of a memory cell under a first parameter at a read temperature and measure a second Vt of the memory ...More ...Less
4 US10579472B2
Semiconductor devices
Publication/Patent Number: US10579472B2 Publication Date: 2020-03-03 Application Number: 15/604,138 Filing Date: 2017-05-24 Inventor: Kim, Chang Hyun   Assignee: SK hynix Inc.   IPC: G06F11/10 Abstract: A semiconductor device may include an error correction circuit and a fuse signal generation circuit. The error correction circuit may be configured to generate a syndrome signal from data using an error correction code. The fuse signal generation circuit may be configured to receive the syndrome signal to generate a fuse signal for repairing a cell array storing the data. A semiconductor device may include an error correction circuit and a fuse signal generation circuit. The error correction circuit may be configured to generate a syndrome signal from data using an error correction code. The fuse signal generation circuit may be configured to ...More ...Less
5 US10580514B2
Periodically updating a log likelihood ratio (LLR) table in a flash memory controller
Publication/Patent Number: US10580514B2 Publication Date: 2020-03-03 Application Number: 15/884,133 Filing Date: 2018-01-30 Inventor: Wu, Yunxiang   Cai, Yu   Chen, Zhengang   Haratsch, Erich   Assignee: Seagate Technology LLC   IPC: G11C29/52 Abstract: Log likelihood ratio (LLR) values that are computed in a flash memory controller during read retries change over time as the number of program-and-erase cycles (PECs) that the flash memory die has been subjected to increases. Therefore, in cases where an LLR table is used to provide pre-defined, fixed LLR values to the error-correcting code (ECC) decoding logic of the controller, decoding success and the resulting BER will degrade over time as the number of PECs to which the die has been subjected increases. In accordance with embodiments, a storage system, a flash memory controller for use in the storage system and method are provided that periodically measure the LLR values and update the LLR table with new LLR values. Periodically measuring the LLR values and updating the LLR table with new LLR values ensures high decoding success and a low BER over the life of the flash memory die. Log likelihood ratio (LLR) values that are computed in a flash memory controller during read retries change over time as the number of program-and-erase cycles (PECs) that the flash memory die has been subjected to increases. Therefore, in cases where an LLR table is used to ...More ...Less
6 US10572343B2
Targeted aliasing single error correction (SEC) code
Publication/Patent Number: US10572343B2 Publication Date: 2020-02-25 Application Number: 15/873,357 Filing Date: 2018-01-17 Inventor: Halbert, John B.   Criss, Kjersten E.   Assignee: Intel Corporation   IPC: G11C29/00 Abstract: A memory device is configured to provide internal or on-die ECC (error checking and correction or error correction coding). In such a system, the code matrix can be managed as four quadrants of (N/4) bits, with two adjacent quadrants in an (N/2)-bit segment or portion. The N codes of the matrix correspond to the N bits of a data word to be protected by the ECC. The code matrix includes M codes corresponding to the M ECC check bits. The memory device includes internal ECC circuitry to perform ECC in the DRAM device with the ECC bits and code matrix in response to a request to access the data word. The codes in a quadrant steer an aliased bit to a quadrant other than an adjacent quadrant. A memory device is configured to provide internal or on-die ECC (error checking and correction or error correction coding). In such a system, the code matrix can be managed as four quadrants of (N/4) bits, with two adjacent quadrants in an (N/2)-bit segment or portion. The N ...More ...Less
7 US10572651B2
Key generating method and apparatus using characteristic of memory
Publication/Patent Number: US10572651B2 Publication Date: 2020-02-25 Application Number: 15/428,677 Filing Date: 2017-02-09 Inventor: Kim, Seung-chan   Shin, Jungsoon   Jung, Taesung   Park, Du-sik   Park, Joonah   Lim, Soochul   Assignee: Samsung Electronics Co., Ltd.   IPC: G06F21/44 Abstract: A key generating method includes obtaining a first error correcting code (ECC) for original data, obtaining read data from a cell array of a memory comprising the original data, generating a second ECC for the read data, obtaining a location of a cell in which an error occurs from the cell array of the memory in response to the second ECC being different from the first ECC, and generating a key for the memory based on the location of the cell in which the error occurs. A key generating method includes obtaining a first error correcting code (ECC) for original data, obtaining read data from a cell array of a memory comprising the original data, generating a second ECC for the read data, obtaining a location of a cell in which an error occurs ...More ...Less
8 US10606481B2
Memory system
Publication/Patent Number: US10606481B2 Publication Date: 2020-03-31 Application Number: 16/100,608 Filing Date: 2018-08-10 Inventor: Okamoto, Shinken   Assignee: TOSHIBA MEMORY CORPORATION   IPC: G11C16/14 Abstract: According to the embodiments, a memory system includes a nonvolatile semiconductor memory and a writing-loop-count monitoring unit that monitors a loop count of an applied voltage to the nonvolatile semiconductor memory required for data writing of the nonvolatile semiconductor memory as a writing loop count. Moreover, the memory system includes a management table for managing the writing loop count in block unit that is a unit of data erasing and a life managing unit that determines a degraded state of the nonvolatile semiconductor memory based on the management table. According to the embodiments, a memory system includes a nonvolatile semiconductor memory and a writing-loop-count monitoring unit that monitors a loop count of an applied voltage to the nonvolatile semiconductor memory required for data writing of the nonvolatile semiconductor ...More ...Less
9 US10565048B2
Logic buffer for hitless single event upset handling
Publication/Patent Number: US10565048B2 Publication Date: 2020-02-18 Application Number: 15/829,542 Filing Date: 2017-12-01 Inventor: Cananzi, David Anthony   Van, Hartingsveldt Elliott B.   Romain, Michael   Assignee: Arista Networks, Inc.   IPC: G06F11/07 Abstract: Methods and systems for handling a single event upset. The methods include, and/or the systems include functionality for, receiving, from a monitored device, data at a first input of an initial state change device; detecting, based on receiving the data, a state change; asserting, based on detecting the state change, an initial state change device enable signal; transferring the first data from the first input to a first output of the initial state change device (which may be operatively connected to a second input of a state hold device); triggering, based on detecting the state change, a delay counter; making a determination that the delay period counted by the delay counter expired without receipt of an error detection signal; and based on the determination, asserting a state hold device enable signal to allow the data to pass from the second input to a second output of the state hold device. Methods and systems for handling a single event upset. The methods include, and/or the systems include functionality for, receiving, from a monitored device, data at a first input of an initial state change device; detecting, based on receiving the data, a state change; ...More ...Less
10 US10613932B2
Method for controlling operations of memory device, associated memory device and controller thereof, and associated electronic device
Publication/Patent Number: US10613932B2 Publication Date: 2020-04-07 Application Number: 16/162,377 Filing Date: 2018-10-16 Inventor: Hsu, Mei-yu   Assignee: Silicon Motion, Inc.   IPC: G06F12/02 Abstract: A method for controlling operations of a memory device, the memory device and controller thereof, and an associated electronic device are provided. The method may include: transmitting a read command to a non-volatile (NV) memory to make the NV memory output a data stream; and utilizing a plurality of sub-circuits of a control logic circuit of the controller to perform parallel processing upon the data stream, respectively. Utilizing the sub-circuits to perform parallel processing upon the data stream may include: utilizing a randomizing/de-randomizing and error correction code (ECC) circuit to perform de-randomizing and ECC decoding according to the data stream, wherein this operation is related to initialization of the memory device; and utilizing an empty-page detection circuit to perform empty-page detection according to the data stream, wherein this operation is related to speeding up of the initialization of the memory device. A method for controlling operations of a memory device, the memory device and controller thereof, and an associated electronic device are provided. The method may include: transmitting a read command to a non-volatile (NV) memory to make the NV memory output a data stream; and ...More ...Less
11 US10629275B2
Data storage device and operating method thereof
Publication/Patent Number: US10629275B2 Publication Date: 2020-04-21 Application Number: 15/952,949 Filing Date: 2018-04-13 Inventor: Gim, Yeong Dong   Assignee: SK hynix Inc.   IPC: G11C11/00 Abstract: A data storage device includes a nonvolatile memory device including a plurality of memory cells; and a controller suitable for determining whether the memory cells are erased or not, wherein, when it is determined, based on first data read as a read voltage set including a first read voltage is applied to the memory cells, that the memory cells are not erased, the controller determines whether the memory cells are erased or not based on second data read as the read voltage set in which the first read voltage is replaced with a second read voltage is applied to the memory cells, and wherein the first and second read voltages are read voltages of lowest levels among read voltages included in the read voltage set. A data storage device includes a nonvolatile memory device including a plurality of memory cells; and a controller suitable for determining whether the memory cells are erased or not, wherein, when it is determined, based on first data read as a read voltage set including a ...More ...Less
12 US10629260B2
Dynamic management of programming states to improve endurance
Publication/Patent Number: US10629260B2 Publication Date: 2020-04-21 Application Number: 16/146,351 Filing Date: 2018-09-28 Inventor: Yang, Nian Niles   Manohar, Abhijeet   Assignee: SanDisk Technologies LLC   IPC: G11C11/56 Abstract: A storage device with a memory may include improved endurance and programming speed by modifying the programming states of the memory blocks. For example, the blocks may be three bit memory blocks, but a dynamic reassignment of verify levels and read margins can result in the block acting like a two bit memory block. Memory blocks may be designed for a certain number of bits per cell (i.e. number of states) and the programming is based on that number. However, single level cell (SLC) programming is still possible in addition to programming according to the number of bits per cell that the memory is designed for. Multiple SLC programming steps can be used to modify the number of states for certain memory cells by the memory controller. A storage device with a memory may include improved endurance and programming speed by modifying the programming states of the memory blocks. For example, the blocks may be three bit memory blocks, but a dynamic reassignment of verify levels and read margins can result in the ...More ...Less
13 US10621023B2
Memory controller with error detection and retry modes of operation
Publication/Patent Number: US10621023B2 Publication Date: 2020-04-14 Application Number: 16/120,819 Filing Date: 2018-09-04 Inventor: Tsern, Ely K.   Horowitz, Mark A.   Ware, Frederick A.   Assignee: Rambus Inc.   IPC: G06F11/07 Abstract: A memory system includes a link having at least one signal line and a controller. The controller includes at least one transmitter coupled to the link to transmit first data, and a first error protection generator coupled to the transmitter. The first error protection generator dynamically adds an error detection code to at least a portion of the first data. At least one receiver is coupled to the link to receive second data. A first error detection logic determines if the second data received by the controller contains at least one error and, if an error is detected, asserts a first error condition. The system includes a memory device having at least one memory device transmitter coupled to the link to transmit the second data. A second error protection generator coupled to the memory device transmitter dynamically adds an error detection code to at least a portion of the second data. A memory system includes a link having at least one signal line and a controller. The controller includes at least one transmitter coupled to the link to transmit first data, and a first error protection generator coupled to the transmitter. The first error protection generator ...More ...Less
14 US10658058B1
Bit error rate estimation for NAND flash memory
Publication/Patent Number: US10658058B1 Publication Date: 2020-05-19 Application Number: 16/525,409 Filing Date: 2019-07-29 Inventor: Kurosawa, Yasuhiko   Steiner, Avi   Weingarten, Hanan   Assignee: Toshiba Memory Corporation   IPC: G11C16/06 Abstract: The present embodiments relate to methods for estimating bit error rates (BERs) associated with a flash memory. According to certain aspects, embodiments provide estimating the BER of multi-bit flash memories during the programming of the flash memory, and providing the estimated BER in a readable status register of the flash memory, thereby improving the speed of programming of the flash memory. The present embodiments relate to methods for estimating bit error rates (BERs) associated with a flash memory. According to certain aspects, embodiments provide estimating the BER of multi-bit flash memories during the programming of the flash memory, and providing the ...More ...Less