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1 | CN112349312A |
存储系统
Substantial Examination
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Publication/Patent Number: CN112349312A | Publication Date: 2021-02-09 | Application Number: 202010396011.1 | Filing Date: 2020-05-12 | Inventor： 崔准佑 黄正太 | Assignee: 爱思开海力士有限公司 | IPC: G11C5/02 | Abstract: 一种存储系统，包括共享从存储器控制器接收到的公共地址的第一存储器和第二存储器，其中，第一存储器包括适用于对公共地址进行加扰以生成指定第一存储器中要被激活的字线的第一加扰地址的第一加扰电路；第二存储器包括适用于对公共地址进行加扰以生成指定第二存储器中要被激活的字线的第二加扰地址的第二加扰电路；以及第一加扰电路和第二加扰电路以如下的方式执行加扰操作：通过第二公共地址而非第一公共地址来在第一存储器和第二存储器之中的最多一个存储器中选择与由第一公共地址选择的字线相邻的相邻字线。 | |||
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2 | US2021027816A1 |
METHODS FOR CLOCK SIGNAL ALIGNMENT IN A MEMORY DEVICE AND MEMORY DEVICES AND SYSTEMS EMPLOYING THE SAME
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Publication/Patent Number: US2021027816A1 | Publication Date: 2021-01-28 | Application Number: 16/518,767 | Filing Date: 2019-07-22 | Inventor： Richards, Randon K. Khatri, Dirgha | Assignee: Micron Technology, Inc. | IPC: G11C7/22 | Abstract: Methods, systems, and apparatuses for managing clock signals at a memory device are described. A memory device or other component of a memory module or electronic system may offset a received clock signal. For example, the memory device may receive a clock signal that has a nominal speed or frequency of operation for a system, and the memory device may adjust or offset the clock signal based on other operating factors, such as the speed or frequency of other signals, physical constraints, indications received from a host device, or the like. A clock offset value may be based on propagation of, for example, command/address signaling. In some examples, a memory module may include a registering clock driver (RCD), hub, or local controller that may manage or coordinate clock offsets among or between various memory devices on the module. Clock offset values may be programmed to a mode register or registers. | |||
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3 | US2021035618A1 |
MEMORY CONTROLLER, METHOD FOR READ CONTROL OF MEMORY, AND ASSOCIATED STORAGE SYSTEM
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Publication/Patent Number: US2021035618A1 | Publication Date: 2021-02-04 | Application Number: 16/937,539 | Filing Date: 2020-07-23 | Inventor： Liu, Hsian-feng | Assignee: Xiamen Sigmastar Technology Ltd. | IPC: G11C7/22 | Abstract: A memory controller, a method for read control of a memory, and an associated storage system are provided. The memory controller includes a data latch circuit, a mask generating circuit, a clock control logic electrically coupled to the mask generating circuit, and a demultiplexer electrically coupled to the data latch circuit and the clock control logic. The data latch circuit latches a series of data within a data signal from the memory according to a data strobe signal from the memory. The mask generating circuit generates a mask signal according to the data strobe signal. The clock control logic generates a receiving clock signal according to the mask signal. The demultiplexer determines valid data within the series of data with aid of the receiving clock signal. | |||
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4 | US10902899B2 |
Apparatuses and method for reducing row address to column address delay
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Publication/Patent Number: US10902899B2 | Publication Date: 2021-01-26 | Application Number: 16/729,185 | Filing Date: 2019-12-27 | Inventor： Kawamura, Christopher | Assignee: Micron Technology, inc. | IPC: G11C8/18 | Abstract: Apparatuses and methods for reducing row address (RAS) to column address (CAS) delay are disclosed. An example apparatus includes a memory including a memory cell coupled to a first digit line in response to a wordline being set to an active state and a sense amplifier coupled to the first digit line and to a second digit line. The sense amplifier is configured to perform a threshold voltage compensation operation to bias the first digit line and the second digit line based on a threshold voltage difference between at least two circuit components of the sense amplifier. The apparatus further comprising a decoder circuit coupled to the wordline and to the sense amplifier. In response to an activate command, the decoder circuit is configured to initiate the threshold voltage compensation operation and, during the threshold voltage compensation operation, to the set the wordline to the active state. | |||
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5 | US2021026789A1 |
Method of Memory Time Division Control and Related Device
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Publication/Patent Number: US2021026789A1 | Publication Date: 2021-01-28 | Application Number: 16/744,202 | Filing Date: 2020-01-16 | Inventor： Cheng, Ching-sheng Lin, Wen-wei Huang, Kuan-chia | Assignee: Realtek Semiconductor Corp. | IPC: G06F13/16 | Abstract: A method of memory time division control for a memory system comprising a plurality of memory controllers and memory devices is disclosed. The method comprises assigning a first operation timing to a first memory controller of the plurality of memory controllers and assigning a second operation timing to a second memory controller of the plurality of memory controllers, wherein the first operation timing is interleaved with the time of the second operation timing, transmitting a first chip select signal generated according to the first command signal, to a first memory device of the plurality of memory devices, and transmitting a second chip select signal generated according to the second command signal, to a second memory device of the plurality of memory devices. | |||
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6 | US2021043240A1 |
NON-VOLATILE MEMORY DEVICE, CONTROLLER AND MEMORY SYSTEM
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Publication/Patent Number: US2021043240A1 | Publication Date: 2021-02-11 | Application Number: 16/916,345 | Filing Date: 2020-06-30 | Inventor： Mun, Kuiyon Shin, Beomkyu Jeong, Jaeyong | Assignee: SAMSUNG ELECTRONICS CO., LTD. | IPC: G11C8/18 | Abstract: A non-volatile memory device is provided. The non-volatile memory device includes a clock pin, a clock signal being received from a controller through the clock pin; a first input/output pin; a second input/output pin, data being received from the controller in synchronization with the clock signal through the second input/output pin; a command/address buffer configured to operate at a first operating speed and buffer a command and an address received through the first input/output pin in synchronization with the clock signal; a memory cell array including a plurality of memory cells; and a control logic configured to control operations with respect to the plurality of memory cells, based on the command and the address buffered in the command/address buffer. | |||
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7 | US2021027821A1 |
APPARATUSES AND METHOD FOR REDUCING ROW ADDRESS TO COLUMN ADDRESS DELAY
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Publication/Patent Number: US2021027821A1 | Publication Date: 2021-01-28 | Application Number: 17/035,462 | Filing Date: 2020-09-28 | Inventor： Kawamura, Christopher | Assignee: Micron Technology, Inc. | IPC: G11C8/18 | Abstract: Apparatuses and methods for reducing row address (RAS) to column address (CAS) delay (tRCD) are disclosed. In some examples, tRCD may be reduced by providing a non-zero offset voltage to a target wordline at an earlier time, such as during a threshold voltage compensation phase of a sense operation. Setting the wordline to a non-zero offset voltage at an earlier time may reduce a time for the wordline to reach an activation voltage, which may reduce tRCD. In other examples, protection against row hammer attacks during precharge phases may be improved by setting the wordline to the non-zero offset voltage. | |||
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8 | US2021043237A1 |
SEMICONDUCTOR DEVICES
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Publication/Patent Number: US2021043237A1 | Publication Date: 2021-02-11 | Application Number: 17/081,744 | Filing Date: 2020-10-27 | Inventor： Yoon, Young Jun Kim, Hyun Seung | Assignee: SK hynix Inc. | IPC: G11C7/10 | Abstract: A semiconductor device includes an input/output (I/O) line drive control circuit and a data I/O circuit. The I/O line drive control circuit is configured to generate drive control pulses having a generation sequence, wherein the generation sequence of the drive control pulses are controlled based on a command pulse and address latch signals, and wherein the address latch signals are set based on when the command pulse is generated to perform a read operation or a write operation. The command pulse is generated to perform a read operation or a write operation. The data I/O circuit controls data I/O operations of a plurality of bank groups based on the drive control pulses. | |||
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9 | US2021055772A1 |
POWER MANAGEMENT
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Publication/Patent Number: US2021055772A1 | Publication Date: 2021-02-25 | Application Number: 16/548,910 | Filing Date: 2019-08-23 | Inventor： Guo, Xiaojiang | Assignee: MICRON TECHNOLOGY, INC. | IPC: G06F1/324 | Abstract: Methods of operating a die might include determining an expected peak current magnitude of the die for a period of time, and outputting the expected peak current magnitude from the die prior to completion of the period of time. Apparatus might be configured to perform similar methods. | |||
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10 | US10885949B2 |
Memory bandwidth aggregation using simultaneous access of stacked semiconductor memory die
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Publication/Patent Number: US10885949B2 | Publication Date: 2021-01-05 | Application Number: 16/653,252 | Filing Date: 2019-10-15 | Inventor： Frans, Yohan | Assignee: Rambus Inc. | IPC: G11C8/18 | Abstract: A packaged semiconductor device includes a data pin, a first memory die, and a second memory die stacked with the first memory die. The first memory die includes a first data interface coupled to the data pin and a first memory core having a plurality of banks. The second memory die includes a second memory core having a plurality of banks. A respective bank of the first memory core and a respective bank of the second memory core perform parallel row access operations in response to a first command signal and parallel column access operations in response to a second command signal. The first data interface of the first die provides aggregated data from the parallel column access operations in the first and second die to the data pin. | |||
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11 | CN107112042B |
数据信号的边沿感知同步的设备、系统和介质
Grant
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Publication/Patent Number: CN107112042B | Publication Date: 2021-02-05 | Application Number: 201580061633.6 | Filing Date: 2015-11-11 | Inventor： G.k.陈 M.a.安德斯 H.考尔 | Assignee: 英特尔公司 | IPC: G11C7/10 | Abstract: 接收包括第一沿和第二沿的信号。信号的第一沿与第一时钟同步，并且信号的同步的第一沿被传递到输出。同步导致信号的第一沿的延迟。信号的第二沿被传递到输出。信号的传递的第二沿具有比信号的第一沿的延迟小第一时钟的至少一个时钟周期的延迟。 | |||
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12 | US2021057016A1 |
SEMICONDUCTOR MEMORY DEVICE HAVING CLOCK GENERATION SCHEME BASED ON COMMAND
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Publication/Patent Number: US2021057016A1 | Publication Date: 2021-02-25 | Application Number: 17/093,786 | Filing Date: 2020-11-10 | Inventor： Shin, Seungjun Doo, Su Yeon Oh, Taeyoung | Assignee: SAMSUNG ELECTRONICS CO., LTD. | IPC: G11C11/4076 | Abstract: A semiconductor memory device includes a command decoder configured to generate an auto-sync signal in response to a command for writing data at a memory cell or reading data from a memory cell, and an internal data clock generating circuit configured to phase synchronize a second clock, having a clock frequency higher than a clock frequency of a first clock, with the first clock in response to the auto-sync signal. | |||
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13 | US2021005234A1 |
SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY (SDRAM) DUAL IN-LINE MEMORY MODULE (DIMM) HAVING INCREASED PER DATA PIN BANDWIDTH
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Publication/Patent Number: US2021005234A1 | Publication Date: 2021-01-07 | Application Number: 17/030,107 | Filing Date: 2020-09-23 | Inventor： Galbi, Duane E. Nale, Bill | Assignee: Intel Corporation | IPC: G11C7/22 | Abstract: An apparatus is described. The apparatus includes logic circuitry to multiplex on a data bus a first data burst, a second data burst, a third data burst and a fourth data burst having different respective base target addresses that respectively target a first memory rank, a second memory rank, a third memory rank and a fourth memory rank. A first data transfer for the first data burst occurs on a first edge of a first pulse of a data strobe signal for the data bus and a second data transfer for the second data burst occurs on a second edge of the first pulse of the data strobe signal. A third data transfer for the third data burst occurs on a first edge of a second pulse of the data strobe signal for the data bus and a fourth data transfer for the fourth data burst occurs on a second edge of the second pulse. The second pulse immediately follows the first pulse on the data strobe signal. The first memory rank, the second memory rank, the third memory rank and the fourth memory rank are on a same memory module. | |||
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14 | US10924097B2 |
Shifter circuits having registers arranged in a folded topology
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Publication/Patent Number: US10924097B2 | Publication Date: 2021-02-16 | Application Number: 16/834,892 | Filing Date: 2020-03-30 | Inventor： Miyano, Kazutaka | Assignee: Micron Technology, Inc. | IPC: G11C8/00 | Abstract: Examples described herein include command latency shifters which may include a plurality of registers arranged in a folded topology. | |||
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15 | US10923167B2 |
Semiconductor devices
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Publication/Patent Number: US10923167B2 | Publication Date: 2021-02-16 | Application Number: 16/400,454 | Filing Date: 2019-05-01 | Inventor： Kim, Woongrae | Assignee: SK hynix Inc. | IPC: G11C7/00 | Abstract: A semiconductor device includes an address latch circuit and a column address generation circuit. The address latch circuit latches an address based on an input control signal generated according to a column control pulse and outputs the latched address as a pre-column address based on an output control signal generated according to an internal column control pulse. The column address generation circuit generates a column address from the pre-column address based on a delayed column control pulse and a delayed internal column control pulse. | |||
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16 | US10915487B2 |
Switching reduction bus using data bit inversion
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Publication/Patent Number: US10915487B2 | Publication Date: 2021-02-09 | Application Number: 16/553,552 | Filing Date: 2019-08-28 | Inventor： Funahashi, Akinori Kondo, Chikara | Assignee: Micron Technology, Inc. | IPC: G06F13/42 | Abstract: Apparatus and methods structured with respect to a data bus having a number of data lines and a number of shield lines can be implemented in a variety of applications. Such apparatus and methods can include driver and receiver circuits that operate to generate and/or decode a data bit inversion signal associated with data propagated on data lines of the data bus. The driver and receiver circuits may be arranged to operate on a two bit basis to interface with the data bus having data lines grouped with respect to the two bits with shield lines for the respective two bit data lines. | |||
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17 | US10897244B1 |
Apparatuses and methods for voltage dependent delay
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Publication/Patent Number: US10897244B1 | Publication Date: 2021-01-19 | Application Number: 16/545,384 | Filing Date: 2019-08-20 | Inventor： Huang, Zhi Qi Chu, Wei Lu Pan, Dong | Assignee: Micron Technology, Inc. | IPC: G11C7/00 | Abstract: Apparatus and methods are described for voltage dependent delay. An example apparatus includes an oscillator including a delay circuit that is configured to provide an oscillating output signal has a delay based on a delay of the delay circuit. The delay of the delay circuit is based on a voltage it receives. For example, the delay of the delay circuit increases for an increasing received voltage and decreases for a decreasing received voltage. As a result, the oscillating output signal provided by the oscillator is based on the received voltage. For example, a frequency of the oscillating output signal decreases for increasing received voltage and increases for decreasing received voltage. Described in another way, the frequency of the oscillating output signal is relatively low for relatively high received voltage and relatively high for relatively low received voltage. | |||
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18 | US2021005227A1 |
CENTRALIZED PLACEMENT OF COMMAND AND ADDRESS IN MEMORY DEVICES
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Publication/Patent Number: US2021005227A1 | Publication Date: 2021-01-07 | Application Number: 17/028,558 | Filing Date: 2020-09-22 | Inventor： Yoshida, Kazuhiro Ishii, Kumiko | Assignee: Micron Technology, Inc. | IPC: G11C5/02 | Abstract: Memory devices, memory systems, and systems, include memory devices with a bonding pad region including two or more bonding pads for operably coupling to external signals and a number of command-and-address (CA) input signals. The memory device also includes centralized CA interface region including two or more CA input circuits operably coupled to the number of input signals. One of the tow or more CA input circuits for each CA input signal may border at least two other CA input circuits coupled to different CA input signals. | |||
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19 | US10885959B1 |
Apparatuses and methods for semiconductor devices including clock signal lines
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Publication/Patent Number: US10885959B1 | Publication Date: 2021-01-05 | Application Number: 16/591,461 | Filing Date: 2019-10-02 | Inventor： Yatsushiro, Ryosuke Narui, Seiji | Assignee: Micron Technology, Inc. | IPC: G11C5/06 | Abstract: Apparatuses for providing a clock signal for a semiconductor device are described. An example apparatus includes a chip including a first clock tree and a second clock tree. The first clock tree includes a first wiring segment extending in a first direction and a second wiring segment extending in a second direction perpendicular to the first direction and coupled the first wiring segment. The second clock tree includes a third wiring segment extending in the second direction, a fourth wiring segment extending in the first direction and coupled to the third wiring segment, and a fifth wiring segment extending in the second direction and coupled to the fourth wiring segment. | |||
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20 | US2021043236A1 |
SEMICONDUCTOR DEVICES
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Publication/Patent Number: US2021043236A1 | Publication Date: 2021-02-11 | Application Number: 17/081,677 | Filing Date: 2020-10-27 | Inventor： Yoon, Young Jun Kim, Hyun Seung | Assignee: SK hynix Inc. | IPC: G11C7/10 | Abstract: A semiconductor device includes an input/output (I/O) line drive control circuit and a data I/O circuit. The I/O line drive control circuit is configured to generate drive control pulses having a generation sequence, wherein the generation sequence of the drive control pulses are controlled based on a command pulse and address latch signals, and wherein the address latch signals are set based on when the command pulse is generated to perform a read operation or a write operation. The command pulse is generated to perform a read operation or a write operation. The data I/O circuit controls data I/O operations of a plurality of bank groups based on the drive control pulses. |
3.Current Quota