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No. Publication Number Title Publication/Patent Number Publication/Patent Number Publication Date Publication Date
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1
EP3762958A1
ELECTRICALLY CONDUCTIVE MATERIAL
Publication/Patent Number: EP3762958A1 Publication Date: 2021-01-13 Application Number: 19711675.9 Filing Date: 2019-03-07 Inventor: Craicun, Monica   Russo, Saverio   Soares, Das Neves Ana Isabel   Torres, Alonso Elias   Dong-wook, Shin   Assignee: University of Exeter   IPC: H01L21/20
2
CN109119331B
一种半导体器件及其制造方法、电子装置
Grant
Publication/Patent Number: CN109119331B Publication Date: 2021-02-02 Application Number: 201710485112.4 Filing Date: 2017-06-23 Inventor: 三重野文健   Assignee: 上海新昇半导体科技有限公司   IPC: H01L21/20 Abstract: 本发明提供一种半导体器件及其制造方法、电子装置,所述方法包括:提供基底,在所述基底的至少部分表面上形成有氧化物;对所述基底的表面进行预处理,其中,所述预处理包括以下步骤:通入包括含Ge的化合物与第一载气的混合气体对所述基底的表面进行处理,以去除所述氧化物;在所述基底表面外延生长外延层。该方法在低温下即可实现对基底表面氧化物的去除,并且还可以和后续的外延生长工艺在同一腔室中执行,使外延生长工艺更加简单易操作,从而保证后续生长的外延层具有良好的质量,进一步提高器件的性能和可靠性。
3
CN112204709A
具有AlScN和AlGaN材料的光子器件
Substantial Examination
Publication/Patent Number: CN112204709A Publication Date: 2021-01-08 Application Number: 201980030226.7 Filing Date: 2019-04-30 Inventor: M·索尔塔尼   E·m·詹贝斯   Assignee: 雷神BBN技术公司   雷声公司   IPC: H01L21/20 Abstract: 一种光子器件具有AlScN和AlGaN材料,其中,Al是铝,Sc是钪,Ga是镓,并且N是氮,并且其中,0小于x并且x小于或等于0.45,并且0小于或等于y并且y小于或等于1。
4
CN112236844A
硅上氮化镓器件中的寄生电容降低
Public
Publication/Patent Number: CN112236844A Publication Date: 2021-01-15 Application Number: 201980028012.6 Filing Date: 2019-06-05 Inventor: 加百利·r·奎瓦   蒂莫西·e·博莱斯   韦恩·麦克·斯特鲁布尔   Assignee: 镁可微波技术有限公司   IPC: H01L21/20 Abstract: 用于制造半导体结构的方法包括:在硅衬底上限定一个或更多个器件区域和一个或更多个互连区域;在硅衬底的互连区域中形成沟槽;使沟槽中的硅衬底氧化以形成二氧化硅区;在硅衬底的表面上形成第III族氮化物材料层;在氮化镓层的器件区域中形成器件;以及在互连区域中形成互连。二氧化硅区降低了互连与接地之间的寄生电容。
5
CN106663604B
旋转批量外延系统
Grant
Publication/Patent Number: CN106663604B Publication Date: 2021-01-26 Application Number: 201580035653.6 Filing Date: 2015-06-09 Inventor: 雅各布·纽曼   Assignee: 应用材料公司   IPC: H01L21/20 Abstract: 本发明实施方式涉及用于在外延薄膜形成期间批量处理的方法与装置。在一个实施例中,处理腔室包括腔室盖件与基板支撑件。腔室盖件包括中心设置的气体入口与第一气体偏转器,第一气体偏转器与腔室盖件耦接并经调适而将第一工艺气体侧向导向横跨多个基板的表面。该盖件也包括一或多个气体出口及多个灯,气体出口自中心设置的气体入口径向向外设置,多个灯设置于中心设置的气体入口与一或多个气体出口之间。基板支撑件是可旋转的且包括气体通道与第二气体偏转器,气体通道于基板支撑件中形成以用于将第二工艺气体引至处理腔室的内部容积,第二气体偏转器经调适而将第二工艺气体侧向地导向横跨多个基板的表面。
6
CN112219262A
用于制备可转移的薄层的方法
Substantial Examination
Publication/Patent Number: CN112219262A Publication Date: 2021-01-12 Application Number: 201880085526.0 Filing Date: 2018-11-15 Inventor: P·罗卡伊卡巴罗卡斯   陈王华   罗曼·卡里乌   Assignee: 国家科学研究中心   法国光伏研究所   综合工科学校   道达尔公司   法国电力公司   IPC: H01L21/20 Abstract: 本发明涉及一种用于制备包括至少一个全单晶半导体层的半导体材料的方法,该方法包括以下步骤:(i)预处理第一衬底的表面以容纳单晶硅层;(ii)在步骤(i)中获得的单晶硅层上,使用等离子体增强化学气相沉积(PECVD),通过具有生长速率梯度的外延生长来沉积单晶硅层;以及(iii)在步骤(ii)中获得的单晶硅层上外延生长半导体材料的单晶层,由此获得包括至少一个全单晶半导体层的材料。本发明还涉及一种多层材料,该多层材料包括半导体材料的单晶层。
7
US10923479B2
Method for fabricating a memory device
Publication/Patent Number: US10923479B2 Publication Date: 2021-02-16 Application Number: 16/889,065 Filing Date: 2020-06-01 Inventor: Chen, Huang-nan   Ikeda, Noriaki   Assignee: Winbond Electronics Corp.   IPC: H01L21/20 Abstract: A method for fabricating a memory device includes: forming a first dielectric layer disposed on a substrate, and a first opening in the first dielectric layer; filling a lower portion of the first opening with a first conductive material layer; conformally forming a lining layer over sidewalls of an upper portion of the first opening and a top surface of the first conductive material layer; filling the upper portion of the first opening with a second conductive material layer; etching back the second conductive material layer and the lining layer to form a recess; conformally forming a protection layer on sidewalls and a bottom portion of the recess and a top surface of the first dielectric layer; forming a second opening that penetrates through the protection layer, the second conductive material layer, the lining layer and the first conductive material layer; forming a pair of contacts in the first opening.
8
CN112382560A
一种多层外延减压生长方法
Public
Publication/Patent Number: CN112382560A Publication Date: 2021-02-19 Application Number: 202011264301.7 Filing Date: 2020-11-12 Inventor: 侯龙   Assignee: 重庆万国半导体科技有限公司   IPC: H01L21/20 Abstract: 本发明公开了多层外延减压生长方法,涉及超级结型功率器件外延生长技术领域,包括如下步骤:A、减压外延生长设备的反应腔前处理;B、外延减压生长步骤;C、每重复步骤A、B 3~5次后进行一次图形刻蚀步骤;D、图形刻蚀的后处理。减压外延工艺比普通外延工艺时间减少10%以上,设备产能提升可达30%以上,本申请所指减压外延工艺对图形的保形更好,可以减少超级结型功率器件两道光刻工艺,本申请所指减压外延低温工艺使wafer的翘曲改善,更利于后续工艺。
9
EP3776632A1
METHOD FOR MANUFACTURING A SUBSTRATE FOR A RADIOFREQUENCY DEVICE
Publication/Patent Number: EP3776632A1 Publication Date: 2021-02-17 Application Number: 19719549.8 Filing Date: 2019-03-26 Inventor: Belhachemi, Djamel   Barge, Thierry   Assignee: SOITEC   IPC: H01L21/20
10
US2021035805A1
Method And Apparatus For Determining Expansion Compensation In Photoetching Process, And Method For Manufacturing Device
Publication/Patent Number: US2021035805A1 Publication Date: 2021-02-04 Application Number: 16/582,549 Filing Date: 2019-09-25 Inventor: Zhao, Changlin   Hu, Sheng   Zhou, Yunpeng   Assignee: Wuhan Xinxin Semiconductor Manufacturing Co., Ltd.   IPC: H01L21/20 Abstract: A method and an apparatus for determining expansion compensation in a photoetching process, and a method for manufacturing a semiconductor device are provided. A relative vector misalignment value of a first wafer and a second wafer after being bonded is obtained based on a relative position relationship between a first alignment pattern of the first wafer and a second alignment pattern of the second wafer in a boding structure. A relative expansion value of the first wafer and the second wafer is obtained based on the relative vector misalignment value. A developing expansion compensation value in the photoetching process is obtained. The expansion compensation value is used to the photoetching process of a first conductor layer including the first alignment pattern of the first wafer and/or a second conductor layer including the second alignment pattern of the second wafer.
11
CN112204708A
公共层上的光子器件和电子器件
Substantial Examination
Publication/Patent Number: CN112204708A Publication Date: 2021-01-08 Application Number: 201980030204.0 Filing Date: 2019-04-30 Inventor: M·索尔塔尼   E·m·詹贝斯   Assignee: 雷神BBN技术公司   雷声公司   IPC: H01L21/20 Abstract: 一种光子器件具有AlScN和AlGaN材料,其中,Al是铝,Sc是钪,Ga是镓,并且N是氮,并且其中,0小于x并且x小于或等于0.45,并且0小于或等于y并且y小于或等于1。
12
EP3552226B1
METHOD FOR TRANSFERRING THIN FILMS
Publication/Patent Number: EP3552226B1 Publication Date: 2021-01-06 Application Number: 17809324.1 Filing Date: 2017-12-08 Inventor: Montmeat, Pierre   Fournel, Frank   Assignee: Commissariat à l'Énergie Atomique et aux Énergies Alternatives   IPC: H01L21/78
13
US10896894B2
Wafer-level methods of fabricating semiconductor device packages and related packages
Publication/Patent Number: US10896894B2 Publication Date: 2021-01-19 Application Number: 16/150,061 Filing Date: 2018-10-02 Inventor: Zhou, Wei   Assignee: Micron Technology, Inc.   IPC: H01L23/00 Abstract: Methods of fabricating semiconductor device packages may involve forming trenches in a first wafer. A dielectric material may be placed over a first active surface. Electrically conductive elements may be operatively connected to bond pads of a second wafer with the dielectric material interposed between the first wafer and the second wafer. Force may be applied to the first wafer and the second wafer while exposing the first wafer and the second wafer to an elevated temperature. Portions of the dielectric material may flow into the trenches. The elevated temperature may be reduced to at least partially solidify the dielectric material. A thickness of the first wafer may be reduced to reveal the portions of the dielectric material in the trenches. The first wager may be singulated and the second wafer may be singulated to form semiconductor dice.
14
CN112236843A
激光退火方法、激光退火装置及有源矩阵基板的制造方法
Substantial Examination
Publication/Patent Number: CN112236843A Publication Date: 2021-01-15 Application Number: 201880094154.8 Filing Date: 2018-06-06 Inventor: 石田茂   Assignee: 堺显示器制品株式会社   IPC: H01L21/20 Abstract: 本发明实施方式的激光退火方法包括:在载物台(70)上配置表面形成有非晶硅膜的基板(1S)的工序;向非晶硅膜的被选择区域的表面供给‑100℃以下的第一氮气的工序;通过向供给第一氮气的被选择区域发射多个激光束(LB),在非晶硅膜内形成多个结晶硅岛的工序。
15
US10886123B2
Methods for forming low temperature semiconductor layers and related semiconductor device structures
Publication/Patent Number: US10886123B2 Publication Date: 2021-01-05 Application Number: 15/974,988 Filing Date: 2018-05-09 Inventor: Raisanen, Petri   Mousa, Moataz Bellah   Hsu, Peng-fu   Assignee: ASM IP Holding B.V.   IPC: H01L21/20 Abstract: A method for forming a metal nitride film with good film closure at low temperatures is disclosed. The method may comprise utilizing plasma to form NH and NH2 radicals to allow for the formation of the metal nitride at low temperatures. The method may also comprise flowing an etch gas to result in an amorphous film with uniform thickness. The method may also comprise flowing an alkyl hydrazine to inhibit three-dimensional island growth of the metal nitride film.
16
US10886129B2
Method for manufacturing semiconductor device and method for evaluating semiconductor device
Publication/Patent Number: US10886129B2 Publication Date: 2021-01-05 Application Number: 16/318,223 Filing Date: 2017-07-03 Inventor: Ohtsuki, Tsuyoshi   Nakasugi, Tadashi   Takeno, Hiroshi   Suzuki, Katsuyoshi   Assignee: SHIN-ETSU HANDOTAI CO., LTD.   IPC: H01L21/02 Abstract: A method for manufacturing a semiconductor device, including forming a Fin structure on a semiconductor silicon substrate, performing ion implantation into the Fin structure, and subsequently performing recovery heat treatment on the semiconductor silicon substrate to recrystallize silicon of the Fin structure, wherein the Fin structure is processed so as not to have an end face of a {111} plane of the semiconductor silicon onto a sidewall of the Fin structure to be formed. It also includes a method for manufacturing a semiconductor device that is capable of preventing a defect from being introduced into a Fin structure when the Fin structure is subjected to ion implantation and recovery heat treatment.
17
US10903162B2
Fuse element resistance enhancement by laser anneal and ion implantation
Publication/Patent Number: US10903162B2 Publication Date: 2021-01-26 Application Number: 16/293,237 Filing Date: 2019-03-05 Inventor: Jiang, Liying   Li, Juntao   Yang, Chih-chao   Rizzolo, Michael   Song, Yi   Assignee: International Business Machines Corporation   IPC: H01L21/20 Abstract: A method for fabricating an electronic fuse includes forming a recess within a film material to define opposed contact segments and a central fuse segment interconnecting the contact segments and altering the material of the central fuse segment of the film material to increase electrical resistance characteristics of the central fuse segment. The central fuse segment may include defects such as voids created by directing a laser at the central fuse segment as a component of a laser annealing process. Alternatively, and or additionally, the central fuse segment may include dopants implementing via an ion implantation process to increase resistance characteristics of the central fuse segment.
18
CN108138361B
基底基板、基底基板的制造方法和第13族氮化物结晶的制造方法
Grant
Publication/Patent Number: CN108138361B Publication Date: 2021-02-12 Application Number: 201680052907.X Filing Date: 2016-09-30 Inventor: 平尾崇行   岩井真   今井克宏   吉野隆史   Assignee: 日本碍子株式会社   IPC: H01L21/20 Abstract: 作为本发明的一个实施方式的基底基板(14)在蓝宝石基板(15)上具备第13族氮化物的晶种层(16)。在晶种层(16)的主面以条纹状重复出现凸部(16a)和凹部(16b),凸部(16a)的阶差(ha)为0.3~40μm,凸部(16a)的宽度(wa)为5~100μm,凹部(16b)的厚度(tb)为2μm以上,凹部(16b)的宽度(wb)为50~500μm。
19
US2021005475A1
WAFER TO WAFER BONDING METHODS AND WAFER TO WAFER BONDING APPARATUSES
Publication/Patent Number: US2021005475A1 Publication Date: 2021-01-07 Application Number: 16/747,783 Filing Date: 2020-01-21 Inventor: Lim, Kyeongbin   Yun, Hyeonjun   Jo, Gwanghee   Lee, Jewon   Han, Minsoo   Kim, Junhyung   Seok, Seungdae   Assignee: Samsung Electronics Co., Ltd.   IPC: H01L21/67 Abstract: In a wafer to wafer bonding method, a first wafer is vacuum suctions on a first surface of a lower stage and a second wafer is vacuum suctioned on a second surface of an upper stage. Pressure is applied to a middle portion of the first wafer by a lower push rod and pressure is applied to a middle portion of the second wafer by an upper push rod. Bonding of the first and second wafers propagates radially outwards. A bonding propagation position of the first and second wafers is detected. A ratio of protruding lengths of the lower push rod and the upper push rod is changed according to the bonding propagation position.
20
EP2932540B1
METHODS FOR PROCESSING OLED DEVICES
Publication/Patent Number: EP2932540B1 Publication Date: 2021-01-27 Application Number: 13863421.7 Filing Date: 2013-12-09 Inventor: Bellman, Robert Alan   Bookbinder, Dana Craig   Manley, Robert George   Mazumder, Prantik   Assignee: Corning Incorporated   IPC: H01L51/52
Total 500 pages