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1
CN107293482B
一种氮化镓高电子迁移率晶体管栅电极的制作方法
Grant
Publication/Patent Number: CN107293482B Publication Date: 2021-03-23 Application Number: 201710448653.X Filing Date: 2017-06-14 Inventor: 孔欣   Assignee: 成都海威华芯科技有限公司   IPC: H01L21/285 Abstract: 本发明公布了一种氮化镓高电子迁移率晶体管栅电极的制作方法:采用步进式曝光机定义栅线条,再采用缩胶工艺将栅线条特征尺寸缩小,随后,在ICP腔体中采用氟基气体刻蚀栅线条开口下的氮化硅介质,刻蚀完成后去除光刻胶,随后匀涂光刻胶曝光得到栅帽线条,经过前处理后进入溅射台溅射金属W,随后取出置入电子束蒸发台淀积Ni/Pt/Au,最后经剥离工艺形成栅电极。本发明所述之方法与传统的采用电子束蒸发金属制作栅电极的方法相比,其优点在于可有效改善栅金属的侧壁填充性,减小器件漏电,提高器件可靠性。
2
CN108597997B
GaN基器件欧姆接触电极的制备方法
Grant
Publication/Patent Number: CN108597997B Publication Date: 2021-03-23 Application Number: 201810166841.8 Filing Date: 2018-02-28 Inventor: 谭永亮   吕鑫   赵红刚   胡泽先   崔玉兴   付兴昌   Assignee: 中国电子科技集团公司第十三研究所   IPC: H01L21/285 Abstract: 本发明适用于半导体技术领域,提供了一种GaN基器件欧姆接触电极的制备方法,该方法包括以下步骤:在器件的上表面生长第一介质层;在所述第一介质层与欧姆接触电极区对应的区域和所述器件的所述欧姆接触电极区注入硅离子和/或铟离子;在所述第一介质层的上表面生长第二介质层;通过高温退火工艺激活所述硅离子和/或所述铟离子,形成N型重掺杂;分别去除所述第一介质层和所述第二介质层与所述欧姆接触电极区对应的部分;在所述器件的所述欧姆接触电极区的上表面生长金属层,形成欧姆接触电极。本发明制备的欧姆接触电极能够保证金属层表面平整、边缘光滑整齐,器件击穿电压稳定、可靠性和寿命长。
3
CN109273357B
改善低掺杂浓度材料表面欧姆接触的方法及材料
Grant
Publication/Patent Number: CN109273357B Publication Date: 2021-03-23 Application Number: 201811137925.5 Filing Date: 2018-09-28 Inventor: 张杨   李弋洋   Assignee: 中科芯电半导体科技(北京)有限公司   IPC: H01L21/285 Abstract: 本发明公开了改善低掺杂浓度材料表面欧姆接触的方法及表面生长Ga金属的低掺杂浓度材料,改善低掺杂浓度材料表面欧姆接触的方法,包括以下步骤:(1)在低掺杂浓度材料表面上外延生长镓金属,镓金属覆盖在低掺杂浓度材料表面上呈圆形薄膜层;(2)将表面生长镓金属的低掺杂浓度材料在氮气气氛下进行退火,使镓金属与低掺杂浓度材料形成欧姆接触。表面生长Ga金属的低掺杂浓度材料,所述低掺杂浓度材料的表面上覆盖呈直径为0.6‑1.5mm的圆形Ga金属薄膜层,所述低掺杂浓度材料上有6‑15μm厚的Ga金属。所述低掺杂浓度材料为III‑V族化合物半导体材料。
4
CN107591319B
半导体装置的制造方法
Grant
Publication/Patent Number: CN107591319B Publication Date: 2021-02-05 Application Number: 201710540888.1 Filing Date: 2017-07-05 Inventor: 青山敬幸   Assignee: 株式会社斯库林集团   IPC: H01L21/28 Abstract: 本发明提供一种能够在不给器件结构带来损伤的情况下导入氟的半导体装置的制造方法。作为处理对象的半导体晶片具有在硅基材的上方隔着二氧化硅的界面层膜形成高介电常数栅极绝缘膜,而且在高介电常数栅极绝缘膜的上方形成含有氟的金属栅极电极的堆叠结构。热处理装置(1)在含有氢的环境气体中从闪光灯向半导体晶片照射闪光来进行100毫秒以下的极短时间加热处理。由此,能够抑制金属栅极电极中含有的氮的扩散,仅使氟从高介电常数栅极绝缘膜扩散至界面层膜和硅基材之间的界面来减少界面态,并提高栅极堆叠结构的可靠性。
5
CN112563128A
一种提高芯片Al电极打线成功率的工艺方法
Substantial Examination
Publication/Patent Number: CN112563128A Publication Date: 2021-03-26 Application Number: 202011432721.1 Filing Date: 2020-12-10 Inventor: 陈旭   吴庆才   Assignee: 苏州工业园区纳米产业技术研究院有限公司   IPC: H01L21/28 Abstract: 本发明涉及一种提高芯片Al电极打线成功率的工艺方法,其包括:启动磁控溅射设备沉积TiN,用以沉积Ti和TiN的第二腔体内留存用以形成TiN的氮气且Ti靶材表面会残留一层TiN薄膜;芯片上依次沉积Al层、Ti层和TiN层,而后退火、沉积钝化层、刻蚀后得到具有麻点Al电极的芯片,在Al层和Ti层之间形成一层TiN,避免退火时,Al和Ti接触而形成合金而阻碍Al的应力释放及再结晶,使得得到的Al电极具有麻点,因麻点为凹凸不平结构,使得打线不易脱落,有利于后续打线的成功率,此外,制备Al层和Ti层之间的TiN层时,没有增加额外工艺步骤和物料,只是利用上次在制备TiN时在第二腔体内留存的氮气和TiN,制备工艺简单,可批量化生产产品,产品良率高且节约成本。
6
US10950448B2
Film quality control in a linear scan physical vapor deposition process
Publication/Patent Number: US10950448B2 Publication Date: 2021-03-16 Application Number: 16/375,941 Filing Date: 2019-04-05 Inventor: Mebarki, Bencherki   Lee, Joung Joo   Tang, Xianmin   Assignee: APPLIED MATERIALS, INC.   IPC: H01L21/285 Abstract: Methods and apparatus for control of the quality of films deposited via physical vapor deposition are provided herein. In some embodiments, a method of depositing a film using linear scan physical vapor deposition includes: determining a deposition rate of a material to be deposited on a substrate in a linear scan physical vapor deposition process; calculating a scan rate of the substrate to achieve deposition of the material to a desired thickness in a single pass when deposited at the deposition rate; and performing the linear scan physical vapor deposition process while moving the substrate at the calculated scan rate.
7
CN110349839B
一种p/n型碳化硅欧姆接触的制备方法
Grant
Publication/Patent Number: CN110349839B Publication Date: 2021-03-12 Application Number: 201910540297.3 Filing Date: 2019-06-21 Inventor: 夏经华   张文婷   田丽欣   吴沛飞   安运来   田亮   查祎英   吴军民   潘艳   杨霏   Assignee: 全球能源互联网研究院有限公司   国家电网有限公司   国网江苏省电力有限公司电力科学研究院   IPC: H01L21/02 Abstract: 本发明属于碳化硅制备技术领域,具体涉及一种p/n型碳化硅欧姆接触的制备方法。该方法包括对碳化硅外延片进行前清洗和预处理,然后采用原子层沉积工艺在碳化硅外延片上依次形成3TiC/SiC层、3TiC/xSiC层和TiC层,经合金化热处理后依次形成TiSiC层、过渡层和TiC层,得到具有欧姆接触特性的p/n型碳化硅;本发明采用ALD,通过控制摩尔比在碳化硅外延片上形成3TiC/SiC层,经合金化热处理后形成TiSiC层,可以降低界面处势垒的高度,与碳化硅外延片形成欧姆接触,该方法避免了沉积过程与碳化硅外延片中的SiC晶圆发生合金化反应,减少了碳富集和空隙等问题的出现。
8
CN112563129A
具有高台阶结构的硅片的金属剥离工艺
Substantial Examination
Publication/Patent Number: CN112563129A Publication Date: 2021-03-26 Application Number: 202011444807.6 Filing Date: 2020-12-11 Inventor: 耿增华   宋厚伟   Assignee: 苏州工业园区纳米产业技术研究院有限公司   IPC: H01L21/28 Abstract: 本发明涉及一种具有高台阶结构的硅片的金属剥离工艺,包括以下步骤:S1、提供硅片,所述硅片具有台阶结构,在所述硅片上定义金属电极区域和非金属电极区域;S2、在所述非金属电极区域上设置感光性干膜;S3、在所述硅片上蒸发金属,通过金属剥离工艺将所述感光性干膜和其上的金属进行剥离,保留所述金属电极区域内的金属。该具有高台阶结构的硅片的金属剥离工艺可以使具有高台阶结构的硅片上的金属剥离干净,避免造成产品异常。
9
US2021020444A1
METHOD FOR MITIGATING LATERIAL FILM GROWTH IN AREA SELECTIVE DEPOSITION
Publication/Patent Number: US2021020444A1 Publication Date: 2021-01-21 Application Number: 16/930,842 Filing Date: 2020-07-16 Inventor: Tapily, Kandabara N.   Assignee: Tokyo Electron Limited   IPC: H01L21/285 Abstract: A substrate processing method for area selective deposition includes providing a substrate containing a first film, a second film, and a third film, forming a first blocking layer on the first film, forming a second blocking layer on the second film, where the second blocking layer is different from the first blocking layer, and selectively forming a material film on the third film. In one example, the first film contains a metal film, second film contains a metal-containing liner that surrounds the metal film, and the third film includes a dielectric film that surrounds the metal-containing liner.
10
EP3447793B1
METHOD FOR PRODUCING SEED LAYERS FOR COPPER INTERCONNECTS
Publication/Patent Number: EP3447793B1 Publication Date: 2021-01-06 Application Number: 18189568.1 Filing Date: 2018-08-17 Inventor: Wu, Zhiyuan   Tseng, Meng Chu   Naik, Mehul B.   Sheu, Ben-li   Assignee: Applied Materials, Inc.   IPC: H01L21/285
11
CN212461601U
一种金刚石基欧姆接触结构
Grant
Publication/Patent Number: CN212461601U Publication Date: 2021-02-02 Application Number: 202021193069.8 Filing Date: 2020-06-24 Inventor: 张鹏飞   陈伟东   张少鹏   王宏兴   Assignee: 内蒙古工业大学   IPC: H01L21/285 Abstract: 本实用新型涉及一种金刚石基欧姆接触结构,属于半导体材料与器件技术领域。该金刚石基欧姆接触结构,包括金刚石衬底,金刚石衬底的表面设有欧姆接触电极,欧姆接触电极包括两层金属电极层,接触金刚石衬底的第一电极层为Ni金属层,第一电极层的上层为第二电极层,第二电极层为化学惰性金属层。金刚石衬底表面上还可预先设有单晶金刚石外延薄膜。在金刚石材料衬底上沉积第一电极层,在第一电极层上沉积第二电极层,之后进行快速退火形成耐高温金刚石基欧姆接触结构。本实用新型的金刚石基欧姆接触结构在高温下有良好的热稳定性和电学特性,同时显著提高了金属电极与金刚石材料之间的黏附性。
12
US10886170B2
Method of forming tungsten film
Publication/Patent Number: US10886170B2 Publication Date: 2021-01-05 Application Number: 15/960,726 Filing Date: 2018-04-24 Inventor: Maekawa, Koji   Sameshima, Takashi   Aoyama, Shintaro   Suzuki, Mikio   Arima, Susumu   Matsumoto, Atsushi   Shibata, Naoki   Assignee: TOKYO ELECTRON LIMITED   IPC: H01L21/768 Abstract: A method of forming a tungsten film having low resistance is provided. The method includes forming a discontinuous film containing a metal on a substrate; and forming the tungsten film on the substrate on which the discontinuous film is formed. In the forming of the discontinuous film, a first source gas and a nitriding gas are supplied onto the substrate alternately along with, for example, a carrier gas. In the forming of the tungsten film, a second source gas and a reducing gas are supplied onto the substrate alternately along with, for example, a carrier gas.
13
US2021028021A1
METHOD OF FORMING AN ELECTRODE ON A SUBSTRATE AND A SEMICONDUCTOR DEVICE STRUCTURE INCLUDING AN ELECTRODE
Publication/Patent Number: US2021028021A1 Publication Date: 2021-01-28 Application Number: 17/038,514 Filing Date: 2020-09-30 Inventor: Mousa, Moataz Bellah   Hsu, Peng-fu   Johnson, Ward   Raisanen, Petri   Assignee: ASM IP Holding B.V.   IPC: H01L21/28 Abstract: A method of forming an electrode on a substrate is disclosed. The method may include: contacting the substrate with a first vapor phase reactant comprising a titanium tetraiodide (TiI4) precursor; contacting the substrate with a second vapor phase reactant comprising a nitrogen precursor; and depositing a titanium nitride layer over a surface of the substrate thereby forming the electrode; wherein the titanium nitride layer has an electrical resistivity of less than 400 μΩ-cm. Related semiconductor device structures including a titanium nitride electrode deposited by the methods of the disclosure are also provided.
14
CN107210340B
发光元件及用于制造该发光元件的电子束沉积装置
Grant
Publication/Patent Number: CN107210340B Publication Date: 2021-01-29 Application Number: 201580074190.4 Filing Date: 2015-12-30 Inventor: 孙秀亨   李建和   崔炳均   崔光基   Assignee: LG伊诺特有限公司   IPC: H01L33/38 Abstract: 一种实施例的发光元件可以包括:发光结构,包括第一导电型半导体层、有源层和第二导电型半导体层;以及第一电极和第二电极,被分别置于第一导电型半导体层和第二导电型半导体层上,其中,发光结构包括第一台面区域,第一导电型半导体层包括第二台面区域,以及第一电极包括:第一区域,其是第二台面区域上表面的部分区域;第二区域,其是第二台面区域的侧表面;以及第三区域,布置成从第二台面区域侧表面的边缘开始延伸,其中,第一、第二和第三区域被形成为使得第一区域的厚度(d1)、第二区域的厚度(d2)和第三区域的厚度(d3)的比例为d1:d2:d3=1:0.9至1.1:1。
15
US2021013041A1
METHOD FOR DEPOSITING A METAL LAYER ON A WAFER
Publication/Patent Number: US2021013041A1 Publication Date: 2021-01-14 Application Number: 16/543,628 Filing Date: 2019-08-19 Inventor: Guo, Xijun   Chen, Jianhua   Zhu, Haipeng   Zhang, Xianlei   Chen, Min-hsien   Yang, Ching-ning   Tan, Wen Yi   Assignee: United Semiconductor (Xiamen) Co., Ltd.   IPC: H01L21/285 Abstract: A method for depositing a metal layer on a wafer is disclosed. A PVD chamber is provide having therein a wafer chuck for holding a wafer to be processed, a target situated above the wafer chuck, a magnet positioned on a backside of the target, and a DC power supply for supplying a DC voltage to the target. The target is a metal or a metal alloy having ferromagnetism property. A paste process is performed to the PVD chamber. The paste process includes sequential steps of: admitting a working gas into the PVD chamber; and igniting the working gas in cascade stages. The wafer is then loaded into the PVD chamber and positioned onto the wafer chuck. A deposition process is then performed to deposit a metal layer sputtered from the target onto the wafer.
16
CN109637933B
薄膜晶体管及其制作方法
Grant
Publication/Patent Number: CN109637933B Publication Date: 2021-03-19 Application Number: 201811589145.4 Filing Date: 2018-12-25 Inventor: 黄北洲   Assignee: 惠科股份有限公司   IPC: H01L21/336 Abstract: 本发明涉及一种薄膜晶体管及其制作方法。该制作方法包括如下步骤:在基板上沉积栅极金属薄膜,通过第一构图工艺,得到栅极的图形;在形成栅极图形的基板上依次沉积栅极绝缘膜、半导体薄膜、掺杂半导体薄膜和源漏极金属薄膜,通过第二构图工艺得到沟道区域和源极、漏极的图形;其中,在掺杂半导体薄膜上沉积源漏极金属薄膜的步骤包括:在掺杂半导体薄膜上依次沉积第一金属钼薄膜、金属铝薄膜和第二金属钼薄膜。解决了在第二次构图工艺中由于源漏极金属薄膜过刻蚀导致掺杂半导体层相对于源漏极金属层具有突出部,降低薄膜晶体管性能的问题。
17
US2021098269A1
SUBSTRATE PROCESSING APPARATUS AND STAGE CLEANING METHOD
Publication/Patent Number: US2021098269A1 Publication Date: 2021-04-01 Application Number: 17/028,702 Filing Date: 2020-09-22 Inventor: Hiroki, Tsutomu   Assignee: TOKYO ELECTRON LIMITED   IPC: H01L21/67 Abstract: A substrate processing apparatus includes a stage on which a substrate to be processed is placed, a liquid supply unit for supplying liquid for controlling a temperature of the substrate to the stage, a flow path formed in the stage and through which the supplied liquid flows, a liquid receiving unit for receiving the liquid discharged from the flow path, a heater for heating the stage to a temperature higher than a usable temperature range of the liquid to remove deposits adhered to the stage, a gas supply unit for supplying a gas to the flow path, and a controller. The controller is configured to switch fluid in the flow path from the liquid supplied from the liquid supply unit to the gas supplied from the gas supply unit, and to control the heater to heat the stage after replacement of the fluid in the flow path with the gas.
18
US10964608B2
Platform and method of operating for integrated end-to-end gate contact process
Publication/Patent Number: US10964608B2 Publication Date: 2021-03-30 Application Number: 16/356,451 Filing Date: 2019-03-18 Inventor: Clark, Robert   Assignee: Tokyo Electron Limited   IPC: H01L21/66 Abstract: A method is provided for gate contact formation on a semiconductor workpiece using an integrated sequence of processing steps executed on a common manufacturing platform (CMP) hosting one or more film-forming modules, one or more etching modules, and one or more transfer modules. A workpiece having a contact feature formed therein, and inspected throughout, the contact feature having a semiconductor contact surface exposed, is received into the CMP. A plurality of metal layers is deposited at a bottom of the contact feature after the workpiece is treated to remove contamination. The integrated sequence of processing steps is executed within the CMP without leaving the controlled environment, the transfer modules used to transfer the workpiece between the modules while maintaining the workpiece within the controlled environment.
19
US2021005460A1
SELECTIVE DEPOSITION USING HYDROLYSIS
Publication/Patent Number: US2021005460A1 Publication Date: 2021-01-07 Application Number: 16/977,438 Filing Date: 2019-03-01 Inventor: Hausmann, Dennis M.   Lemaire, Paul C.   Assignee: Lam Research Corporation   IPC: H01L21/288 Abstract: Methods and apparatuses for selective deposition of metal oxides on metal surfaces relative to dielectric surfaces are provided. Selective deposition is achieved by exposing metal and dielectric surfaces to a blocking reagent capable of forming a hydrolyzable bond with metal while forming a non hydrolyzable bond with the dielectric, and dipping the surfaces in water to cleave the hydrolyzable bond and leave a blocked surface on the dielectric surface, followed by depositing metal oxide selectively on the metal surface relative to the dielectric surface. Blocking reagents are deposited by wet or dry techniques and may include an alkylaminosilane or alkylchlorosilane as examples.
20
CN112166489A
半导体器件的制造方法、衬底处理装置及程序
Substantial Examination
Publication/Patent Number: CN112166489A Publication Date: 2021-01-01 Application Number: 201880093867.2 Filing Date: 2018-05-28 Inventor: 出贝求   芦原洋司   Assignee: 株式会社国际电气   IPC: H01L21/31 Abstract: 提供能够在衬底上选择性地形成膜的技术。具有:向具有第1表面和与所述第1表面不同的第2表面的衬底供给含有无机配体的改性气体,对所述第1表面进行改性的工序;和向所述衬底供给沉积气体,使膜选择生长于所述第2表面的工序。
Total 500 pages