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1 | CN112185818A |
一种ZnO薄膜的干法刻蚀方法
Substantial Examination
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Publication/Patent Number: CN112185818A | Publication Date: 2021-01-05 | Application Number: 202011070446.3 | Filing Date: 2020-10-09 | Inventor： 高钰麒 咸冯林 徐林华 匡文剑 郑改革 曹兆楼 李金花 杨明珠 裴世鑫 | Assignee: 南京信息工程大学 | IPC: H01L21/4763 | Abstract: 一种ZnO薄膜的干法刻蚀方法，包括如下步骤：对ZnO薄膜进行清洗，吹干后待用；在ZnO薄膜表面旋涂一层光刻胶；通过掩模紫外曝光和丙酮清洗获得所需图案；对ICP刻蚀的刻蚀腔进行抽真空；向刻蚀腔内通入甲烷、氢气和氩气，气体流量分别为3 sccm、8 sccm和5sccm，调节真空腔压强为0.13Pa；对刻蚀腔进行预刻蚀；在刻蚀腔内载入ZnO薄膜，调节刻蚀温度为20摄氏度，射频功率设置为200 W，ICP功率设置为500W或1000W，进行刻蚀，完成后取出样品，使用丙酮超声清洗去除光刻胶，获得最终样品。本发明方法能够形成表面光滑，刻蚀界面清晰的ZnO刻蚀界面。 | |||
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2 | US10978342B2 |
Interconnect with self-forming wrap-all-around barrier layer
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Publication/Patent Number: US10978342B2 | Publication Date: 2021-04-13 | Application Number: 16/262,560 | Filing Date: 2019-01-30 | Inventor： Huang, Huai Nogami, Takeshi Grill, Alfred Briggs, Benjamin D. Lanzillo, Nicholas A. Lavoie, Christian Sil, Devika Bhosale, Prasad Kelly, James | Assignee: International Business Machines Corporation | IPC: H01L21/4763 | Abstract: The present invention provides interconnects with self-forming wrap-all-around graphene barrier layer. In one aspect, a method of forming an interconnect structure is provided. The method includes: patterning at least one trench in a dielectric; forming an interconnect in the at least one trench embedded in the dielectric; and forming a wrap-all-around graphene barrier surrounding the interconnect. An interconnect structure having a wrap-all-around graphene barrier is also provided. | |||
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3 | US2021005738A1 |
METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
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Publication/Patent Number: US2021005738A1 | Publication Date: 2021-01-07 | Application Number: 16/971,061 | Filing Date: 2019-02-22 | Inventor： Okazaki, Kenichi Shima, Yukinori | Assignee: Semiconductor Energy Laboratory Co., Ltd. | IPC: H01L29/66 | Abstract: A semiconductor device having favorable electrical characteristics is provided. The semiconductor device is manufactured by a first step of forming a semiconductor layer containing a metal oxide, a second step of forming a first insulating layer, a third step of forming a first conductive film over the first insulating layer, a fourth step of etching part of the first conductive film to form a first conductive layer, thereby forming a first region over the semiconductor layer that overlaps with the first conductive layer and a second region over the semiconductor layer that does not overlap with the first conductive layer, and a fifth step of performing first treatment on the conductive layer. The first treatment is plasma treatment in an atmosphere including a mixed gas of a first gas containing an oxygen element but not containing a hydrogen element, and a second gas containing a hydrogen element but not containing an oxygen element. | |||
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4 | US2021095207A1 |
ETCHANT
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Publication/Patent Number: US2021095207A1 | Publication Date: 2021-04-01 | Application Number: 16/971,926 | Filing Date: 2018-03-26 | Inventor： Yamada, Youzou Goto, Toshiyuki | Assignee: MITSUBISHI GAS CHEMICAL COMPANY, INC. | IPC: C09K13/08 | Abstract: The present invention provides an etchant less causing damage to IGZOs. The etchant of the present invention comprises hydroxyethanediphosphonic acid (A), one or more phosphonic acids (B), hydrogen peroxide (C), nitric acid (D), a fluorine compound (E), an azole (F), and an alkali (G), and is characterized in that the phosphoric acids (B) comprise one or more phosphonic acids selected from the group consisting of diethylenetriaminepentamethylenephosphonic acid, N,N,N′,N′-ethylenediaminetetrakismethylenephosphonic acid, and aminotrimethylenephosphonic acid and that the proportion of the hydroxyethanediphosphonic acid (A) is in the range of 0.01-0.1 mass % and the proportion of the phosphonic acids (B) is in the range of 0.003-0.04 mass %. | |||
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5 | US2021043746A1 |
THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF
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Publication/Patent Number: US2021043746A1 | Publication Date: 2021-02-11 | Application Number: 16/616,509 | Filing Date: 2019-09-09 | Inventor： Liu, Jing | Assignee: TCL CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD | IPC: H01L29/49 | Abstract: The present invention discloses a thin film transistor and manufacturing method thereof, comprising in sequence a substrate, a gate, a gate insulation layer, an active layer, a contact layer and a source/drain, wherein, the gate comprises a metal barrier layer and a conductive layer, the metal barrier layer is a molybdenum alloy layer, the molybdenum alloy layer comprises a Mo and two other metal elements. | |||
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6 | US10950587B2 |
Printed circuit board and package structure
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Publication/Patent Number: US10950587B2 | Publication Date: 2021-03-16 | Application Number: 16/662,080 | Filing Date: 2019-10-24 | Inventor： Jeon, Kee-su Seong, Min-jae | Assignee: Samsung Electro-Mechanics Co., Ltd. | IPC: H01L29/40 | Abstract: A printed circuit board includes an insulating material with a bump pad buried in one surface, an adhesive layer stacked on the one surface of the insulating material, an insulating layer stacked on the adhesive layer, and a cavity passing through both of the adhesive layer and the insulating layer to expose the bump pad, wherein the cavity has a cross-sectional area decreasing in a direction toward the insulating material. | |||
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7 | US2021050453A1 |
Semiconductor Device and Method for Manufacturing the Same
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Publication/Patent Number: US2021050453A1 | Publication Date: 2021-02-18 | Application Number: 17/002,971 | Filing Date: 2020-08-26 | Inventor： Miyairi, Hidekazu Osada, Takeshi Yamazaki, Shunpei | Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD. | IPC: H01L29/786 | Abstract: As a display device has a higher definition, the number of pixels, gate lines, and signal lines are increased. When the number of the gate lines and the signal lines are increased, a problem of higher manufacturing cost, because it is difficult to mount an IC chip including a driver circuit for driving of the gate and signal lines by bonding or the like. A pixel portion and a driver circuit for driving the pixel portion are provided over the same substrate, and at least part of the driver circuit includes a thin film transistor using an oxide semiconductor interposed between gate electrodes provided above and below the oxide semiconductor. Therefore, when the pixel portion and the driver portion are provided over the same substrate, manufacturing cost can be reduced. | |||
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8 | US10957645B1 |
Package structure having conductive patterns with crystal grains copper columnar shape and method manufacturing the same
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Publication/Patent Number: US10957645B1 | Publication Date: 2021-03-23 | Application Number: 16/572,609 | Filing Date: 2019-09-17 | Inventor： Lee, Yu-ming Lee, Chiang-hao Kuo, Hung-jui Ho, Ming-che | Assignee: Taiwan Semiconductor Manufacturing Company, Ltd. | IPC: H01L23/48 | Abstract: A package structure includes a semiconductor die and a redistribution circuit structure. The redistribution circuit structure is disposed on and electrically connected to the semiconductor die and includes a metallization layer and a dielectric layer disposed on the metallization layer. The metallization layer has conductive patterns, where each of the conductive patterns includes crystal grains, the crystal grains each are in a column shape and include a plurality of first banded structures having copper atoms oriented on a (220) lattice plane. | |||
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9 | US10886172B2 |
Methods for wordline separation in 3D-NAND devices
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Publication/Patent Number: US10886172B2 | Publication Date: 2021-01-05 | Application Number: 16/848,754 | Filing Date: 2020-04-14 | Inventor： Chen, Yihong Duan, Ziqing Mallick, Abhijit Basu Chan, Kelvin | Assignee: Applied Materials, Inc. | IPC: H01L21/4763 | Abstract: Methods of wordline separation in semiconductor devices (e.g., 3D-NAND) are described. A metal film is deposited in the wordlines and on the surface of a stack of spaced oxide layers. The metal film is removed by high temperature oxidation and etching of the oxide or low temperature atomic layer etching by oxidizing the surface and etching the oxide in a monolayer fashion. After removal of the metal overburden, the wordlines are filled with the metal film. | |||
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10 | US10950550B2 |
Semiconductor package with through bridge die connections
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Publication/Patent Number: US10950550B2 | Publication Date: 2021-03-16 | Application Number: 15/774,306 | Filing Date: 2015-12-22 | Inventor： Qian, Zhiguo Xie, Jianyong Aygun, Kemal | Assignee: Intel Corporation | IPC: H01L23/12 | Abstract: Semiconductor packages with through bridge die connections and a method of manufacture therefor is disclosed. The semiconductor packages may house one or more electronic components as a system in a package (SiP) implementation. A bridge die, such as an embedded multi-die interconnect bridge (EMIB), may be embedded within one or more build-up layers of the semiconductor package. The bridge die may have an electrically conductive bulk that may be electrically connected on a backside to a power plane and used to deliver power to one or more dies attached to the semiconductor package via interconnects formed on a topside of the bridge die that are electrically connected to the bulk of the bridge die. A more direct path for power delivery through the bridge die may be achieved compared to routing power around the bridge die. | |||
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11 | US2021020717A1 |
DISPLAY DEVICE AND METHOD FOR FABRICATING THE SAME
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Publication/Patent Number: US2021020717A1 | Publication Date: 2021-01-21 | Application Number: 16/843,764 | Filing Date: 2020-04-08 | Inventor： Kim, Hyung Jun Kim, Myoung Hwa Kim, Tae Sang Moon, Yeon Keon Park, Joon Seok Sohn, Sang Woo Shin, Sang Won Lim, Jun Hyung Choi, Hye Lim | Assignee: Samsung Display Co., Ltd. | IPC: H01L27/32 | Abstract: A display device and a method for fabricating the same are provided. The display device comprises pixels connected to scan lines, and to data lines crossing the scan lines, each of the pixels including a light emitting element, and a first transistor configured to control a driving current supplied to the light emitting element according to a data voltage applied from the data line, the first transistor including a first active layer having an oxide semiconductor, and a first oxide layer on the first active layer and having a crystalline oxide containing tin (Sn). | |||
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12 | US10943863B2 |
Techniques to improve reliability in Cu interconnects using Cu intermetallics
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Publication/Patent Number: US10943863B2 | Publication Date: 2021-03-09 | Application Number: 16/570,037 | Filing Date: 2019-09-13 | Inventor： Hu, Chao-kun Lavoie, Christian Rossnagel, Stephen M. Shaw, Thomas M. | Assignee: International Business Machines Corporation | IPC: H01L23/48 | Abstract: Techniques for improving reliability in Cu interconnects using Cu intermetallics are provided. In one aspect, a method of forming a Cu interconnect in a dielectric over a Cu line includes the steps of: forming at least one via in the dielectric over the Cu line; depositing a metal layer onto the dielectric and lining the via such that the metal layer is in contact with the Cu line at the bottom of the via, wherein the metal layer comprises at least one metal that can react with Cu to form a Cu intermetallic; annealing the metal layer and the Cu line under conditions sufficient to form a Cu intermetallic barrier at the bottom of the via; and plating Cu into the via to form the Cu interconnect, wherein the Cu interconnect is separated from the Cu line by the Cu intermetallic barrier. A device structure is also provided. | |||
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13 | US10968364B2 |
Plasma polymerized thin film having low dielectric constant, device, and method of preparing thin film
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Publication/Patent Number: US10968364B2 | Publication Date: 2021-04-06 | Application Number: 16/549,150 | Filing Date: 2019-08-23 | Inventor： Jung, Donggeun Ban, Wonjin Kwon, Sungyool Park, Yoonsoo Lim, Hyuna Kim, Younghyun | Assignee: Research & Business Foundation Sungkyunkwan University | IPC: H01L21/4763 | Abstract: A plasma polymerized thin film having low dielectric constant prepared by depositing a first precursor material represented by the following Chemical Formula 1: wherein in the above Chemical Formula 1, R1 to R14 are each independently H or a substituted or non-substituted C1-C5 alkyl group, and when the R1 to R14 are substituted, their substituents comprise an amino group, a hydroxyl group, a cyano group, a halogen group, a nitro group, or a methoxy group. | |||
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14 | US10902804B2 |
Display device
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Publication/Patent Number: US10902804B2 | Publication Date: 2021-01-26 | Application Number: 16/720,697 | Filing Date: 2019-12-19 | Inventor： Yamazaki, Shunpei Kimura, Hajime | Assignee: Semiconductor Energy Laboratory Co., Ltd. | IPC: G09G3/36 | Abstract: A display device that is suitable for increasing in size is achieved. Three or more source lines are provided for each pixel column. Video signals having the same polarity are input to adjacent source lines during one frame period. Dot inversion driving is used to reduce a flicker, crosstalk, or the like. | |||
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15 | US10950478B2 |
Info structure with copper pillar having reversed profile
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Publication/Patent Number: US10950478B2 | Publication Date: 2021-03-16 | Application Number: 16/410,183 | Filing Date: 2019-05-13 | Inventor： Cheng, Hsi-kuei Chang, Ching Fu Han, Chih-kang Huang, Hsin-chieh | Assignee: Taiwan Semiconductor Manufacturing Company, Ltd. | IPC: H01L21/4763 | Abstract: A method includes forming a first polymer layer to cover a metal pad of a wafer, and patterning the first polymer layer to form a first opening. A first sidewall of the first polymer layer exposed to the first opening has a first tilt angle where the first sidewall is in contact with the metal pad. The method further includes forming a metal pillar in the first opening, sawing the wafer to generate a device die, encapsulating the device die in an encapsulating material, performing a planarization to reveal the metal pillar, forming a second polymer layer over the encapsulating material and the device die, and patterning the second polymer layer to form a second opening. The metal pillar is exposed through the second opening. A second sidewall of the second polymer layer exposed to the second opening has a second tilt angle greater than the first tilt angle. | |||
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16 | US10903136B2 |
Package structure having a plurality of insulating layers
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Publication/Patent Number: US10903136B2 | Publication Date: 2021-01-26 | Application Number: 16/183,128 | Filing Date: 2018-11-07 | Inventor： Wu, Ming-hung Wu, Chi-fu Tseng, An-ping Wu, Hao-yu | Assignee: TDK Taiwan Corp. | IPC: H01L23/12 | Abstract: A package structure is provided, including a first insulating layer, a second insulating layer, a third insulating layer, and a chip. The second insulating layer is disposed on the first insulating layer, the chip is disposed in the second insulating layer, and the third insulating layer is disposed on the second insulating layer. The heat conductivity of the second insulating layer is lower than the heat conductivity of the first insulating layer, and the hardness of the second insulating layer is lower than the hardness of the first insulating layer. | |||
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17 | CN107146761B |
一种巨磁光效应的钇铁石榴石/铋异质薄膜的制备方法
Grant
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Publication/Patent Number: CN107146761B | Publication Date: 2020-07-28 | Application Number: 201710312918.3 | Filing Date: 2017-05-05 | Inventor： 金立川 洪彩云 张怀武 杨青慧 钟智勇 饶毅恒 李颉 廖宇龙 | Assignee: 电子科技大学 | IPC: H01L21/4763 | Abstract: 本发明公开了一种巨磁光效应的钇铁石榴石/铋异质薄膜及其制备方法，该方法，包括采用液相外延在[111]晶向的钆镓石榴石(GGG)上生长的高质量单晶钇铁石榴石(YIG)作为基片，以及所述的YIG基片上利用分子束外延(MBE)技术生长很薄的一层铋得到钇铁石榴石/铋异质薄膜。该方法简单可行的，所制得的钇铁石榴石/铋异质薄膜相对于无铋薄膜的钇铁石榴石(YIG)的磁光克尔转角显著增大；本发明相比在YIG中铋的置换掺杂，制备工艺简单，为异质结型磁光材料的制备与研究提供了一种新的方法，在光通信、磁光存储等众多领域有广泛的应用。 | |||
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18 | US10763159B2 |
Method for forming a multi-level interconnect structure
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Publication/Patent Number: US10763159B2 | Publication Date: 2020-09-01 | Application Number: 16/518,361 | Filing Date: 2019-07-22 | Inventor： Briggs, Basoene Wilson, Christopher Boemmels, Juergen | Assignee: IMEC vzw | IPC: H01L21/4763 | Abstract: A method is provided for forming a multi-level interconnect structure on a semiconductor substrate, e.g., for use in an integrated circuit, comprising forming on the substrate a first interconnection level comprising a first dielectric layer and a first set of conductive structures arranged in the first dielectric layer, forming on the first interconnection level a second interconnection level comprising a second dielectric layer and a second set of conductive structures arranged in the second dielectric layer, and forming on the second interconnection level a third interconnection level. | |||
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19 | US10685868B2 |
Method of fabricating contact hole
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Publication/Patent Number: US10685868B2 | Publication Date: 2020-06-16 | Application Number: 16/553,202 | Filing Date: 2019-08-28 | Inventor： Chang, Feng-yi Tzou, Shih-fang Lee, Fu-che Chiang, Hsin-yu Chen, Yu-ching | Assignee: UNITED MICROELECTRONICS CORP. Fujian Jinhua Integrated Circuit Co., Ltd. | IPC: H01L21/4763 | Abstract: A method of fabricating a contact hole includes the steps of providing a conductive line, a mask layer covering and contacting the conductive line, a high-k dielectric layer covering and contacting the mask layer, and a first silicon oxide layer covering and contacting the high-k dielectric layer, wherein the high-k dielectric layer includes a first metal oxide layer, a second metal oxide layer and a third metal oxide layer stacked from bottom to top. A dry etching process is performed to etch the first silicon oxide layer, the high-k dielectric layer, and the mask layer to expose the conductive line and form a contact hole. Finally, a wet etching process is performed to etch the first silicon oxide layer, the third metal oxide layer and the second metal oxide layer to widen the contact hole, and the first metal oxide layer remains after the wet etching process. | |||
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20 | US10529663B1 |
Copper interconnect with filled void
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Publication/Patent Number: US10529663B1 | Publication Date: 2020-01-07 | Application Number: 16/159,671 | Filing Date: 2018-10-14 | Inventor： Nogami, Takeshi Yang, Chih-chao | Assignee: International Business Machines Corporation | IPC: H01L21/4763 | Abstract: Voids within metal deposited on interconnect structures are filled with cobalt or a cobalt compound to enhance electromigration performance. A reflow process to enlarge interconnect metal grain size is performed prior to filling the voids. An interconnect metal microstructure beneath the filled voids includes grain boundaries extending to the bottom portions of the voids. A coating of manganese atoms provides resistance to electromigration. Copper interconnects having fine dimensions and improved reliability are obtained. |
3.Current Quota