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1 | US2021005571A1 |
Bonding Device
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Publication/Patent Number: US2021005571A1 | Publication Date: 2021-01-07 | Application Number: 16/919,570 | Filing Date: 2020-07-02 | Inventor： Seidl, Siegfried Enthammer, Johann | Assignee: F&S Bondtec Semiconductor GmbH | IPC: H01L23/00 | Abstract: Bonding device for producing bonding connections, in particular wire bonding connections, tape bonding connections and ball bonding connections, on carriers fixed outside the bonding device and having contact surfaces for the bonding connections, in different spatial directions with respect to the respective carrier, the bonding device comprising a base body, a bonding tool which is movable relative to the base body for applying a bonding force to a bonding means placed on the contact surface of the carrier to produce a material bond between the bonding means and the contact surface as a bonding connection, and bonding force generating means for generating a bonding force directed towards the contact surface when the bonding tool is placed on the carrier, wherein the bonding force generating means comprise a bonding force setting device for realizing a predetermined effective bonding force independently of its spatial direction of action. | |||
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2 | US2021013171A1 |
CLIPS FOR SEMICONDUCTOR PACKAGES
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Publication/Patent Number: US2021013171A1 | Publication Date: 2021-01-14 | Application Number: 16/507,003 | Filing Date: 2019-07-09 | Inventor： Bajuri, Mohd Kahar Mohamed, Abdul Rahman Chua, Siang Kuan Tean, Ke Yan | Assignee: Infineon Technologies AG | IPC: H01L23/00 | Abstract: A clip for a semiconductor package and a semiconductor having a clip is disclosed. In one example, the clip includes a first planar portion, a plurality of first pillars, and a plurality of first solder balls. Each first pillar of the plurality of first pillars is coupled to the first planar portion. Each first solder ball of the plurality of first solder balls is coupled to a corresponding first pillar of the plurality of first pillars. | |||
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3 | US2021013174A1 |
METHOD OF LIQUID ASSISTED BONDING
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Publication/Patent Number: US2021013174A1 | Publication Date: 2021-01-14 | Application Number: 16/505,716 | Filing Date: 2019-07-09 | Inventor： Chen, Li-yi | Assignee: MIKRO MESA TECHNOLOGY CO., LTD. | IPC: H01L23/00 | Abstract: A method of liquid assisted bonding includes: forming a structure with a liquid layer between an electrode of a device and a contact pad of a substrate, and two opposite surfaces of the liquid layer being respectively in contact with the electrode and the contact pad in which hydrogen bonds are formed between the liquid layer and at least one of the electrode and the contact pad; and evaporating the liquid layer to break said hydrogen bonds such that at least one of a surface of the electrode facing the contact pad and a surface of the contact pad facing the electrode is activated so as to assist a formation of a diffusion bonding between the electrode of the device and the contact pad in which a contact area between the electrode and the contact pad is smaller than or equal to about 1 square millimeter. | |||
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4 | US2021035934A1 |
Method for Producing a Connection Between Component Parts
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Publication/Patent Number: US2021035934A1 | Publication Date: 2021-02-04 | Application Number: 17/046,209 | Filing Date: 2019-05-08 | Inventor： Katz, Simeon Huppmann, Sophia Hoenle, Michael Wagner, Thorsten Hingerl, Kurt | Assignee: OSRAM Opto Semiconductors GmbH | IPC: H01L23/00 | Abstract: In an embodiment a method includes providing the first component part with a partially exposed first insulating layer, a plurality of first through-vias and an exposed first contact layer structured in places and planarized in places, wherein the first through-vias are each laterally enclosed by the first insulating layer, and wherein the first contact layer partially covers the first insulating layer and completely covers the first through-vias; providing the second component part with a partially exposed second insulating layer, a plurality of second through-vias and an exposed second contact layer structured in places and planarized in places, wherein the second through-vias are each laterally enclosed by the second insulating layer, and wherein the second contact layer partially covers the second insulating layer and completely covers the second through-vias and joining the component parts such that the contact layers overlap each other thereby mechanically and electrically connecting the component parts to each other by a direct bonding process at the contact layers. | |||
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5 | US10916511B1 |
Method for reducing warpage occurred to substrate strip after molding process
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Publication/Patent Number: US10916511B1 | Publication Date: 2021-02-09 | Application Number: 16/784,299 | Filing Date: 2020-02-07 | Inventor： Liu, Fu-chou Lee, Chien-chen Chang, Ya-han | Assignee: KINGPAK TECHNOLOGY INC. | IPC: H01L23/00 | Abstract: A method for reducing warpage occurred to a substrate strip after a molding process is provided. First, several dies are mounted on a top surface of a substrate strip. Then, a base having a top surface with a surface curvature is provided, and the top surface of the base is contacted against a bottom surface of the substrate strip to bend the substrate strip. Next, under the status that the top surface of the base is contacted against the bottom surface of the substrate strip, a molding compound is wrapped around each die. Finally, the molding compound is cooled to a room temperature. Accordingly, the molding process is performed on the substrate strip reversely bent in a direction opposite to a warpage direction. Therefore, the warpage originally caused by the molding process is offset by the reverse bending. | |||
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6 | US10923454B2 |
Method and apparatus for creating a bond between objects based on formation of inter-diffusion layers
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Publication/Patent Number: US10923454B2 | Publication Date: 2021-02-16 | Application Number: 15/176,567 | Filing Date: 2016-06-08 | Inventor： Paknejad, Seyed Amir | Assignee: Paknejad, Seyed Amir | IPC: H01L23/00 | Abstract: The present disclosure provides a method of creating a bond between a first object and a second object. For example, creating a joint or die attach between a semiconductor chip and an electronic substrate, especially for harsh and high temperature environments. The method may include a step of filling a space between the first object and the second object with a filler material. Further, the method may include a step of heating the filler material to facilitate formation of a plurality of inter-diffusion layers. Accordingly, a first inter-diffusion layer may be formed between the filler material and the first object. Further, a second inter-diffusion layer may be formed between the filler material and the second object. Furthermore, in some embodiments, the first inter-diffusion layer may be contiguous with the second inter-diffusion layer. The contiguity may be facilitated by placement of at least one insert between the first object and the second object, in which the inter-diffusion of the filler material and the at least one insert may produce the third inter-diffusion layer, wherein the third inter-diffusion layer is contiguous with each of the first inter-diffusion layer and the second inter-diffusion layer. | |||
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7 | US2021035935A1 |
SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
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Publication/Patent Number: US2021035935A1 | Publication Date: 2021-02-04 | Application Number: 17/071,895 | Filing Date: 2020-10-15 | Inventor： Chen, Ming-fa Chen, Hsien-wei | Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. | IPC: H01L23/00 | Abstract: A semiconductor structure includes a first substrate, a first dielectric layer disposed over the first substrate, a plurality of first bonding pads disposed in the first dielectric layer, a plurality of second bonding pads disposed in the first dielectric layer, a second substrate, and a second dielectric layer disposed over the second substrate. The first bonding pads have a first width. The second bonding pads have a second width greater than the first width. The second bonding pads are arranged to form a frame pattern surrounding the first bonding pads. A portion of the second dielectric layer is in physical contact with the second bonding pads. The first bonding pads and the second bonding pads are arranged to form a plurality of columns and a plurality of rows. Two of the second bonding pads are disposed at two opposite ends of each column and two opposite ends of each row. | |||
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8 | US10896887B2 |
Stress relieving structure for semiconductor device
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Publication/Patent Number: US10896887B2 | Publication Date: 2021-01-19 | Application Number: 16/295,856 | Filing Date: 2019-03-07 | Inventor： Bodea, Marius Aurel Heidmann, Terry Richard Mataln, Marianne Sgiarovello, Claudia | Assignee: Infineon Technologies AG | IPC: H01L23/00 | Abstract: A semiconductor device includes a semiconductor body, a stress relieving layer or layer stack disposed over at least part of the semiconductor body, the stress relieving layer or layer stack comprising a plurality of openings which yield a patterned surface topography for the stress relieving layer or layer stack, and a metal layer or layer stack formed on the stress relieving layer or layer stack and occupying the plurality of openings in the stress relieving layer or layer stack. The patterned surface topography of the stress relieving layer or layer stack is transferred to a surface of the metal layer or layer stack facing away from the semiconductor body. The stress relieving layer or layer stack has a different elastic modulus than the metal layer or layer stack over a temperature range. | |||
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9 | US2021013166A1 |
BOND PAD RELIABILITY OF SEMICONDUCTOR DEVICES
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Publication/Patent Number: US2021013166A1 | Publication Date: 2021-01-14 | Application Number: 16/508,288 | Filing Date: 2019-07-10 | Inventor： Chockalingam, Ramasamy Tan, Juan Boon Melville, Ian | Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd. | IPC: H01L23/00 | Abstract: The disclosed subject matter relates to a structure and method to improve bond pad reliability of semiconductor devices. According to an aspect of the present disclosure, a bond pad structure is provided that includes a dielectric layer and at least one bond pad in the dielectric layer, wherein the bond pad has a top surface. A passivation layer has an opening over the bond pad, wherein the opening has sidewalls. A low-k barrier layer is covering the sidewalls of the opening and the top surface of the bond pad. Protective structures are formed over the sidewalls of the opening. | |||
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10 | US2021050321A1 |
NOBLE METAL-COATED SILVER WIRE FOR BALL BONDING AND METHOD FOR PRODUCING THE SAME, AND SEMICONDUCTOR DEVICE USING NOBLE METAL-COATED SILVER WIRE FOR BALL BONDING AND METHOD FOR PRODUCING THE SAME
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Publication/Patent Number: US2021050321A1 | Publication Date: 2021-02-18 | Application Number: 16/969,357 | Filing Date: 2018-04-19 | Inventor： Chiba, Jun Antoku, Yuki Kawano, Shota | Assignee: TANAKA DENSHI KOGYO K.K. | IPC: H01L23/00 | Abstract: A noble metal-coated silver bonding wire suppresses corrosion at the bonding interface under severe conditions of high temperature and high humidity, and the noble metal-coated silver bonding wire can be ball-bonded in the air. The noble metal-coated silver wire for ball bonding is a noble metal-coated silver wire including a noble metal coating layer on a core material made of pure silver or a silver alloy, wherein the wire contains at least one sulfur group element, the noble metal coating layer includes a palladium intermediate layer and a gold skin layer, the palladium content relative to the entire wire is 0.01 mass % or more and 5.0 mass % or less, the gold content relative to the entire wire is 1.0 mass % or more and 6.0 mass % or less, and the sulfur group element content relative to the entire wire is 0.1 mass ppm or more and 100 mass ppm or less. | |||
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11 | CN108022883B |
包括电子芯片堆叠的设备
Grant
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Publication/Patent Number: CN108022883B | Publication Date: 2021-01-29 | Application Number: 201710282275.2 | Filing Date: 2017-04-26 | Inventor： C·查姆佩克斯 N·博瑞尔 | Assignee: 意法半导体(鲁塞)公司 | IPC: H01L23/00 | Abstract: 一种设备，包括：第一芯片，该第一芯片具有前侧和后侧；第二芯片，该第二芯片与该第一芯片堆叠，并且位于该第一芯片的该后侧上；以及第一环，该第一环包括：第一通孔和第二通孔，这些通孔位于该第一芯片中并且每个通孔具有在该第一芯片的该前侧上的第一端以及在该第一芯片的该后侧上的第二端；第一轨道，该第一轨道连接这些第一端，并且位于该第一芯片中在其前侧上；以及第二轨道，该第二轨道连接这些第二端，并且位于该第二芯片中，该第一芯片包括用于检测该第一环的电气特性的第一电路。 | |||
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12 | US10903179B2 |
Semiconductor contact structure having stress buffer layer formed between under bump metal layer and copper pillar
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Publication/Patent Number: US10903179B2 | Publication Date: 2021-01-26 | Application Number: 16/294,906 | Filing Date: 2019-03-06 | Inventor： Lin, Yu-jie | Assignee: UNITED MICROELECTRONICS CORPORATION | IPC: H01L23/00 | Abstract: Semiconductor apparatus and method for manufacturing semiconductor apparatus are provided. Semiconductor apparatus includes a semiconductor substrate having metal pads, a first passivation layer, a second passivation layer, an under bump metal layer, a stress buffer layer, a copper pillar and a solder structure. First passivation layer is formed on the semiconductor substrate and covers a portion of each metal pad, the first passivation layer has first passivation layer openings to expose a first portion of each metal pad. Second passivation layer is formed on the first passivation layer, the second passivation layer has second passivation layer openings to expose a second portion of each metal pad. Under bump metal layer is formed on the second portion of each metal pad exposed by the second passivation layer opening. Stress buffer layer is formed on the under bump metal layer, and the copper pillar is disposed on the stress buffer layer. | |||
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13 | US10910330B2 |
Pad structure and integrated circuit die using the same
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Publication/Patent Number: US10910330B2 | Publication Date: 2021-02-02 | Application Number: 15/892,460 | Filing Date: 2018-02-09 | Inventor： Chen, Chun-liang | Assignee: MediaTek Inc. | IPC: H01L23/00 | Abstract: A pad structure is formed on an IC die and includes a first conductive layer, a dielectric layer, a second conductive layer and a passivation layer. The first conductive layer is formed on an upper surface of the IC die and having a hollow portion. The dielectric layer covers the first conductive layer. The second conductive layer is formed on the dielectric layer and electrically connected to the first conductive layer. The passivation layer covers the second conductive layer and has an opening exposing the second conductive layer for receiving a bonding wire. | |||
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14 | US2021020585A1 |
SEMICONDUCTOR DEVICES HAVING CRACK-INHIBITING STRUCTURES
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Publication/Patent Number: US2021020585A1 | Publication Date: 2021-01-21 | Application Number: 17/062,922 | Filing Date: 2020-10-05 | Inventor： Arifeen, Shams U. Chun, Hyunsuk Yang, Sheng Wei Kawakita, Keizo | Assignee: Micron Technology, Inc. | IPC: H01L23/00 | Abstract: Semiconductor devices having metallization structures including crack-inhibiting structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a metallization structure formed over a semiconductor substrate. The metallization structure can include a bond pad electrically coupled to the semiconductor substrate via one or more layers of conductive material, and an insulating material—such as a low-κ dielectric material—at least partially around the conductive material. The metallization structure can further include a crack-inhibiting structure positioned beneath the bond pad between the bond pad and the semiconductor substrate. The crack-inhibiting structure can include (a) a metal lattice extending laterally between the bond pad and the semiconductor substrate and (b) barrier members extending vertically between the metal lattice and the bond pad. | |||
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15 | CN112259506A |
一种基于铝热自蔓延薄膜的芯片销毁封装结构
Substantial Examination
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Publication/Patent Number: CN112259506A | Publication Date: 2021-01-22 | Application Number: 202011253036.2 | Filing Date: 2020-11-11 | Inventor： 周立彦 朱思雄 朱家昌 | Assignee: 中国电子科技集团公司第五十八研究所 | IPC: H01L23/00 | Abstract: 本发明公开一种基于铝热自蔓延薄膜的芯片销毁封装结构，属于集成电路封装领域。所述基于铝热自蔓延薄膜的芯片销毁封装结构中包括管壳基板、芯片、铝热自蔓延薄膜；芯片贴装在所述管壳基板中；铝热自蔓延薄膜贴装在所述芯片上，并通过键合引线引出到封装结构外。由于铝热自蔓延薄膜的贴装特性，在封装工艺中避免了传统火工装置的药剂填装腔体，因而体积更小，毁伤区域更集中；封装过程中工艺温度控制在触发温度以下，则基本没有安全隐患；贴装薄膜的工艺与常规芯片封装工艺兼容，基板/管壳设计仅需增加少许触发用引出端，因此适合批量生产。 | |||
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16 | US2021035945A1 |
SOLDERING A CONDUCTOR TO AN ALUMINUM LAYER
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Publication/Patent Number: US2021035945A1 | Publication Date: 2021-02-04 | Application Number: 16/943,084 | Filing Date: 2020-07-30 | Inventor： Heinrich, Alexander Otremba, Ralf Schwab, Stefan | Assignee: Infineon Technologies AG | IPC: H01L23/00 | Abstract: An arrangement is disclosed. In one example, the arrangement of a conductor and an aluminum layer soldered together comprises a substrate and the aluminum layer disposed over the substrate. The aluminum forms a first bond metal. An intermetallic compound layer is disposed over the aluminum layer. A solder layer is disposed over the intermetallic compound layer, wherein the solder comprises a low melting majority component. The conductor is disposed over the solder layer, wherein the conductor has a soldering surface which comprises a second bond metal. The intermetallic compound comprises aluminum and the second bond metal and is predominantly free of the low melting majority component. | |||
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17 | CN112400226A |
焊接线材与焊线机上的焊接位置之间的焊接的检测方法
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Publication/Patent Number: CN112400226A | Publication Date: 2021-02-23 | Application Number: 201980043484.9 | Filing Date: 2019-06-26 | Inventor： G·s·吉洛蒂 | Assignee: 库利克和索夫工业公司 | IPC: H01L23/00 | Abstract: 提供一种确定线材与半导体器件的至少一个焊接位置之间的焊接状况的方法。方法包括以下步骤：(a)利用焊线机的焊接工具，将线材的一部分焊接到半导体器件的至少一个焊接位置；以及(b)检测与焊接工具接合并与所述线材的一部分分离的线材的另一部分在预定高度范围中有无接触所述线材的一部分，由此确定所述线材的一部分是否被焊接到所述至少一个焊接位置。 | |||
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18 | CN112331618A |
半导体组件及其制造方法
Public
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Publication/Patent Number: CN112331618A | Publication Date: 2021-02-05 | Application Number: 201910716001.9 | Filing Date: 2019-08-05 | Inventor： 蔡耀庭 陈江宏 庄哲辅 洪文 | Assignee: 华邦电子股份有限公司 | IPC: H01L23/00 | Abstract: 本发明提供一种半导体组件及其制造方法，所述制造方法包括以下步骤。在衬底上形成彼此分离的第一密封环与第二密封环。在所述衬底上形成保护层，覆盖所述第一密封环与所述第二密封环，其中所述第一密封环与所述第二密封环之间的所述保护层具有凹面。移除位于所述凹面处的所述保护层以及所述第一密封环上的部分所述保护层，于所述第一密封环的侧壁形成间隙壁，并在所述保护层中形成开口，所述开口的宽度大于所述第一密封环的宽度，且所述开口裸露出所述第一密封环的顶面以及所述间隙壁。 | |||
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19 | US2021035947A1 |
METHOD AND DEVICE FOR COMPRESSION BONDING CHIP TO SUBSTRATE
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Publication/Patent Number: US2021035947A1 | Publication Date: 2021-02-04 | Application Number: 17/072,175 | Filing Date: 2020-10-16 | Inventor： Hsieh, Chin-tang Tu, Chia-jung | Assignee: CHIPBOND TECHNOLOGY CORPORATION | IPC: H01L23/00 | Abstract: Method and device for compression bonding are disclosed. During compression bonding a chip to a substrate, an anti-adhesion layer on a stage is provided to contact with a solder resist layer on the substrate. The solder resist layer will not stick to the anti-adhesion layer such that the reduction of bonding precision due to the solder resist layer remains residues on the compression bonding device is preventable. | |||
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20 | US2021043597A1 |
Selective Soldering with Photonic Soldering Technology
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Publication/Patent Number: US2021043597A1 | Publication Date: 2021-02-11 | Application Number: 16/834,471 | Filing Date: 2020-03-30 | Inventor： Zhang, Leilei Marsh, Jason P. Hoang, Lan Abdollahian, Yashar | Assignee: Apple Inc. | IPC: H01L23/00 | Abstract: Electronic assembly methods and structures are described. In an embodiment, an electronic assembly method includes bringing together an electronic component and a routing substrate, and directing a large area photonic soldering light pulse toward the electronic component to bond the electronic component to the routing substrate. |
3.Current Quota