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No. Publication Number Title Publication/Patent Number Publication/Patent Number Publication Date Publication Date
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1
US2021005571A1
Bonding Device
Publication/Patent Number: US2021005571A1 Publication Date: 2021-01-07 Application Number: 16/919,570 Filing Date: 2020-07-02 Inventor: Seidl, Siegfried   Enthammer, Johann   Assignee: F&S Bondtec Semiconductor GmbH   IPC: H01L23/00 Abstract: Bonding device for producing bonding connections, in particular wire bonding connections, tape bonding connections and ball bonding connections, on carriers fixed outside the bonding device and having contact surfaces for the bonding connections, in different spatial directions with respect to the respective carrier, the bonding device comprising a base body, a bonding tool which is movable relative to the base body for applying a bonding force to a bonding means placed on the contact surface of the carrier to produce a material bond between the bonding means and the contact surface as a bonding connection, and bonding force generating means for generating a bonding force directed towards the contact surface when the bonding tool is placed on the carrier, wherein the bonding force generating means comprise a bonding force setting device for realizing a predetermined effective bonding force independently of its spatial direction of action.
2
US2021091021A1
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
Publication/Patent Number: US2021091021A1 Publication Date: 2021-03-25 Application Number: 16/815,324 Filing Date: 2020-03-11 Inventor: Takahashi, Hiroaki   Assignee: Kabushiki Kaisha Toshiba   Toshiba Electronic Devices & Storage Corporation   IPC: H01L23/00 Abstract: A semiconductor device of an embodiment includes: a semiconductor substrate; a first insulating layer provided on or above the semiconductor substrate; an aluminum layer provided on the first insulating layer; a second insulating layer provided on the first insulating layer, the second insulating layer covering a first region of a surface of the aluminum layer; and an aluminum oxide film provided on a second region other than the first region of the surface of the aluminum layer, the aluminum oxide film including α-alumina as a main component, and a film thickness of the aluminum oxide film being equal to or larger than 0.5 nm and equal to or smaller than 3 nm.
3
US2021091026A1
WAFER-LEVEL PACKAGE INCLUDING UNDER BUMP METAL LAYER
Publication/Patent Number: US2021091026A1 Publication Date: 2021-03-25 Application Number: 17/115,093 Filing Date: 2020-12-08 Inventor: Jang, Hyung Sun   Yoon, Yeo Hoon   Assignee: Samsung Electronics Co., Ltd.   IPC: H01L23/00 Abstract: A semiconductor package includes a semiconductor chip comprising a first surface and a second surface, a redistribution layer on the first surface of the semiconductor chip, an under bump metal (UBM) layer on the redistribution layer, and a solder bump on the UBM layer, and the solder bump covers both outer side surfaces of the UBM layer.
4
US2021074669A1
SEMICONDUCTOR DEVICE PACKAGES AND METHODS OF MANUFACTURING THE SAME
Publication/Patent Number: US2021074669A1 Publication Date: 2021-03-11 Application Number: 16/563,701 Filing Date: 2019-09-06 Inventor: Tu, Shun-tsat   Lo, Pei-jen   Sie, Fong Ren   Weng, Cheng-en   Huang, Min Lung   Assignee: Advanced Semiconductor Engineering, Inc.   IPC: H01L23/00 Abstract: A semiconductor device package includes a connection structure having a first portion and a second portion extending from the first portion, the second portion having a width less than the first portion; and a dielectric layer surrounding the connection structure, wherein the dielectric layer and the second portion of the connection structure defines a space.
5
US2021074675A1
SEMICONDUCTOR DEVICE
Publication/Patent Number: US2021074675A1 Publication Date: 2021-03-11 Application Number: 16/807,910 Filing Date: 2020-03-03 Inventor: Shini, Masato   Assignee: KIOXIA CORPORATION   IPC: H01L23/00 Abstract: According to one embodiment, a semiconductor device includes a first wafer, a first wiring layer, a first insulating layer, a first electrode, a second wafer, a second wiring layer, a second insulating layer, a second electrode, and a first layer. The first electrode includes a first surface, a second surface, a third surface, and a fourth surface. The second electrode includes a fifth surface, a sixth surface, a seventh surface, a second side surface, and an eighth surface. The first layer is provided between the fourth surface and a portion of the first insulating layer that surrounds the fourth surface, and is provided away from the third surface in the first direction.
6
US10978416B2
Dual bond pad structure for photonics
Publication/Patent Number: US10978416B2 Publication Date: 2021-04-13 Application Number: 16/573,179 Filing Date: 2019-09-17 Inventor: Gambino, Jeffrey P.   Graf, Richard S.   Leidy, Robert K.   Maling, Jeffrey C.   Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION   IPC: H01L23/00 Abstract: A dual bond pad structure for a wafer with laser die attachment and methods of manufacture are disclosed. The method includes forming a bonding layer on a surface of a substrate. The method further includes forming solder bumps on the bonding layer. The method further includes patterning the bonding layer to form bonding pads some of which comprise the solder bumps thereon. The method further includes attaching a laser diode to selected bonding pads using solder connections formed on the laser diode. The method further includes attaching an interposer substrate to the solder bumps formed on the bonding pads.
7
US2021111146A1
CUPD WIRE BOND CAPILLARY DESIGN
Publication/Patent Number: US2021111146A1 Publication Date: 2021-04-15 Application Number: 17/066,153 Filing Date: 2020-10-08 Inventor: Camargo, Soto Miguel   Assignee: SKYWORKS SOLUTIONS, INC.   IPC: H01L23/00 Abstract: A capillary for performing ball bonding includes a body defining a lumen, a first blade defined in a lower tip of the body, and a second blade defined in the lower tip of the body for increasing reliability of a ball bonding procedure performed using the capillary.
8
US2021111148A1
METHOD OF USING OPTOELECTRONIC SEMICONDUCTOR STAMP TO MANUFACTURE OPTOELECTRONIC SEMICONDUCTOR DEVICE
Publication/Patent Number: US2021111148A1 Publication Date: 2021-04-15 Application Number: 17/131,092 Filing Date: 2020-12-22 Inventor: Chen, Hsien-te   Assignee: Ultra Display Technology Corp.   IPC: H01L23/00 Abstract: A method of using an optoelectronic semiconductor stamp to manufacture an optoelectronic semiconductor device comprises the following steps: a preparation step: preparing at least one optoelectronic semiconductor stamp group and a target substrate, wherein each optoelectronic semiconductor stamp group comprises at least one optoelectronic semiconductor stamp, each optoelectronic semiconductor stamp comprises a plurality of optoelectronic semiconductor components disposed on a heat conductive substrate, each optoelectronic semiconductor component has at least one electrode, and the target substrate has a plurality of conductive portions; an align-press step: aligning and attaching at least one optoelectronic semiconductor stamp to the target substrate, so that the electrodes are pressed on the corresponding conductive portions; and a bonding step: electrically connecting the electrodes to the corresponding conductive portions.
9
US2021111149A1
METHOD FOR PRODUCING A STABLE SANDWICH ARRANGEMENT OF TWO COMPONENTS WITH SOLDER SITUATED THEREBETWEEN
Publication/Patent Number: US2021111149A1 Publication Date: 2021-04-15 Application Number: 16/629,770 Filing Date: 2018-10-29 Inventor: Schäfer, Michael   Schmitt, Wolfgang   Assignee: Heraeus Deutschland GmbH & Co. KG   IPC: H01L23/00 Abstract: A method for producing a stable sandwich arrangement of two components with solder situated therebetween, comprising the steps: (1) providing two components, each having at least one contact surface, and a free solder preform, (2) producing a sandwich arrangement of the components and a solder preform arranged between them and thus not yet connected to them by bringing into contact (i) each one of the contact surfaces, (ii) each of the single contact surface of the components or (iii) one of the contact surfaces of one component and a single contact surface of the other component, with the contact surfaces of the free solder preform, and (3) hot-pressing the sandwich arrangement produced in step (2) so as to form the stable sandwich arrangement at a temperature being at 10 to 40% below the melting temperature of the solder metal of the solder preform, expressed in ° C.
10
US10964661B2
Wire bonding apparatus, circuit for wire bonding apparatus, and method for manufacturing semiconductor device
Publication/Patent Number: US10964661B2 Publication Date: 2021-03-30 Application Number: 16/088,081 Filing Date: 2017-03-24 Inventor: Abe, Junichi   Ueda, Hisashi   Kondo, Yutaka   Assignee: SHINKAWA LTD.   IPC: H01L23/00 Abstract: The present invention comprises: a spool (10); a clamper (22); a torch electrode (31); a high-voltage power source circuit (30); a non-bonding detection circuit (40); a first changeover switch (50) switching a connection between the spool (10) and the high-voltage power source circuit (30) or the non-bonding detection circuit (40); and a relay (53) turning on/off a connection between the clamper (22) and a spool side of the first changeover switch (50), and comprises a control part (60) that sets the first changeover switch (50) to the high-voltage power source circuit side and turns off the relay (53) to generate electric discharge, and that sets the first changeover switch (50) to the non-bonding detection circuit side and turns on the relay (53) to perform non-bonding detection. Due to this configuration, electric corrosion of a wire clamper can be suppressed and non-bonding detection can be carried out with a simple configuration.
11
US2021035934A1
Method for Producing a Connection Between Component Parts
Publication/Patent Number: US2021035934A1 Publication Date: 2021-02-04 Application Number: 17/046,209 Filing Date: 2019-05-08 Inventor: Katz, Simeon   Huppmann, Sophia   Hoenle, Michael   Wagner, Thorsten   Hingerl, Kurt   Assignee: OSRAM Opto Semiconductors GmbH   IPC: H01L23/00 Abstract: In an embodiment a method includes providing the first component part with a partially exposed first insulating layer, a plurality of first through-vias and an exposed first contact layer structured in places and planarized in places, wherein the first through-vias are each laterally enclosed by the first insulating layer, and wherein the first contact layer partially covers the first insulating layer and completely covers the first through-vias; providing the second component part with a partially exposed second insulating layer, a plurality of second through-vias and an exposed second contact layer structured in places and planarized in places, wherein the second through-vias are each laterally enclosed by the second insulating layer, and wherein the second contact layer partially covers the second insulating layer and completely covers the second through-vias and joining the component parts such that the contact layers overlap each other thereby mechanically and electrically connecting the component parts to each other by a direct bonding process at the contact layers.
12
US10916511B1
Method for reducing warpage occurred to substrate strip after molding process
Publication/Patent Number: US10916511B1 Publication Date: 2021-02-09 Application Number: 16/784,299 Filing Date: 2020-02-07 Inventor: Liu, Fu-chou   Lee, Chien-chen   Chang, Ya-han   Assignee: KINGPAK TECHNOLOGY INC.   IPC: H01L23/00 Abstract: A method for reducing warpage occurred to a substrate strip after a molding process is provided. First, several dies are mounted on a top surface of a substrate strip. Then, a base having a top surface with a surface curvature is provided, and the top surface of the base is contacted against a bottom surface of the substrate strip to bend the substrate strip. Next, under the status that the top surface of the base is contacted against the bottom surface of the substrate strip, a molding compound is wrapped around each die. Finally, the molding compound is cooled to a room temperature. Accordingly, the molding process is performed on the substrate strip reversely bent in a direction opposite to a warpage direction. Therefore, the warpage originally caused by the molding process is offset by the reverse bending.
13
CN107887337B
受保护的电子芯片
Grant
Publication/Patent Number: CN107887337B Publication Date: 2021-02-26 Application Number: 201710179661.9 Filing Date: 2017-03-23 Inventor: C·查姆佩克斯   N·博瑞尔   A·萨拉菲亚诺斯   Assignee: 意法半导体(鲁塞)公司   IPC: H01L23/00 Abstract: 公开了受保护的电子芯片。一种电子芯片,包括:第一导电类型的掺杂半导体衬底、覆盖该衬底的第二导电类型的掺杂掩埋层以及覆盖该掩埋层的该第一导电类型的第一掺杂阱。电路部件可以形成在该第一掺杂阱的顶表面处并与该掩埋层分隔开。电流检测器耦合到该掩埋层并且被配置成用于检测流入或流出该掩埋层的偏置电流。
14
US2021013171A1
CLIPS FOR SEMICONDUCTOR PACKAGES
Publication/Patent Number: US2021013171A1 Publication Date: 2021-01-14 Application Number: 16/507,003 Filing Date: 2019-07-09 Inventor: Bajuri, Mohd Kahar   Mohamed, Abdul Rahman   Chua, Siang Kuan   Tean, Ke Yan   Assignee: Infineon Technologies AG   IPC: H01L23/00 Abstract: A clip for a semiconductor package and a semiconductor having a clip is disclosed. In one example, the clip includes a first planar portion, a plurality of first pillars, and a plurality of first solder balls. Each first pillar of the plurality of first pillars is coupled to the first planar portion. Each first solder ball of the plurality of first solder balls is coupled to a corresponding first pillar of the plurality of first pillars.
15
US2021013174A1
METHOD OF LIQUID ASSISTED BONDING
Publication/Patent Number: US2021013174A1 Publication Date: 2021-01-14 Application Number: 16/505,716 Filing Date: 2019-07-09 Inventor: Chen, Li-yi   Assignee: MIKRO MESA TECHNOLOGY CO., LTD.   IPC: H01L23/00 Abstract: A method of liquid assisted bonding includes: forming a structure with a liquid layer between an electrode of a device and a contact pad of a substrate, and two opposite surfaces of the liquid layer being respectively in contact with the electrode and the contact pad in which hydrogen bonds are formed between the liquid layer and at least one of the electrode and the contact pad; and evaporating the liquid layer to break said hydrogen bonds such that at least one of a surface of the electrode facing the contact pad and a surface of the contact pad facing the electrode is activated so as to assist a formation of a diffusion bonding between the electrode of the device and the contact pad in which a contact area between the electrode and the contact pad is smaller than or equal to about 1 square millimeter.
16
US2021125951A1
INTEGRATED DEVICE COMPRISING INTERCONNECT STRUCTURES HAVING AN INNER INTERCONNECT, A DIELECTRIC LAYER AND A CONDUCTIVE LAYER
Publication/Patent Number: US2021125951A1 Publication Date: 2021-04-29 Application Number: 16/665,883 Filing Date: 2019-10-28 Inventor: Weng, Li-sheng   Li, Yue   Sun, Yangyang   Assignee: QUALCOMM Incorporated   IPC: H01L23/00 Abstract: An integrated device that includes a substrate, an interconnect portion and an interconnect structure. The interconnect portion is located over the substrate. The interconnect portion includes a plurality of interconnects and at least one dielectric layer. The interconnect structure is located over the interconnect portion. The interconnect structure includes an inner interconnect, a dielectric layer coupled to the inner interconnect, and an outer conductive layer coupled to the dielectric layer. The outer conductive layer is configured to operate as a shield for the inner interconnect.
17
CN213071099U
一种电子元件分离装置
Grant
Publication/Patent Number: CN213071099U Publication Date: 2021-04-27 Application Number: 202021806211.1 Filing Date: 2020-08-25 Inventor: 王冠群   Assignee: 镇江太迪电子有限公司   IPC: H01L23/00 Abstract: 本实用新型公开了一种电子元件分离装置,包括底座和移动板,所述底座的两端皆安装有固定板,且固定板的顶部安装有顶板,所述固定板靠近底座一端的顶部皆设置有滑槽,且滑槽通过滑块安装有移动板,所述底座顶部的两端皆安装有安装板,且安装板靠近底座的一端皆安装有第一轴承。本实用新型安装有第二轴承、移动板、伸缩弹簧、分离压辊和第一转杆,使用过程中,伸缩弹簧的弹性作用使其推动移动板,使得分离压辊能够与电子元件封装产品的外侧紧密贴合,从而可将不同厚度的电子元件封装产品夹持于分离压辊和分离转辊之间,装置能够适用于不同规格的电子元件封装产品,适用性较强,有利于装置的推广。
18
US2021134745A1
SEMICONDUCTOR CHIP AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME
Publication/Patent Number: US2021134745A1 Publication Date: 2021-05-06 Application Number: 16/922,828 Filing Date: 2020-07-07 Inventor: Jeong, Eunyoung   Lee, Juik   Han, Junghoon   Assignee: Samsung Electronics Co., Ltd.   IPC: H01L23/00 Abstract: Disclosed embodiments include a semiconductor chip including a semiconductor substrate having a top surface with a top connection pad disposed therein, and a protection insulation layer comprising an opening therein, the protection insulation layer not covering at least a portion of the top connection pad, on the semiconductor substrate. The protection insulation layer may include: a bottom protection insulation layer, a cover insulation layer comprising a side cover part that covers at least a portion of a side surface of the bottom protection insulation layer and a top cover part disposed apart from the side cover part to cover at least a portion of a top surface of the bottom protection insulation layer. The protection insulation layer may further include a top protection insulation layer on the top cover part.
19
US2021134750A1
CONDUCTIVE MEMBERS FOR DIE ATTACH IN FLIP CHIP PACKAGES
Publication/Patent Number: US2021134750A1 Publication Date: 2021-05-06 Application Number: 16/669,070 Filing Date: 2019-10-30 Inventor: Manack, Christopher Daniel   Pavone, Salvatore Frank   EscaÑo, Maricel Fabia   Guevara, Rafael Jose Lizares   Assignee: TEXAS INSTRUMENTS INCORPORATED   IPC: H01L23/00 Abstract: In examples, a semiconductor package comprises a semiconductor die having an active surface; a conductive layer coupled to the active surface; and a polyimide layer coupled to the conductive layer. The package also comprises a conductive pillar coupled to the conductive layer and to the polyimide layer; a flux adhesive material coupled to the conductive pillar; and a solder layer coupled to the flux adhesive material. The package further includes a conductive terminal coupled to the solder layer and exposed to a surface of the package, the active surface of the semiconductor die facing the conductive terminal.
20
US2021143123A1
Batch Diffusion Soldering and Electronic Devices Produced by Batch Diffusion Soldering
Publication/Patent Number: US2021143123A1 Publication Date: 2021-05-13 Application Number: 16/679,414 Filing Date: 2019-11-11 Inventor: Trunov, Kirill   Heinrich, Alexander   Roesl, Konrad   Unrau, Arthur   Assignee: Infineon Technologies Austria AG   IPC: H01L23/00 Abstract: A method of batch soldering includes: forming a soldered joint between a metal region of a first semiconductor die and a metal region of a substrate using a solder preform via a soldering process which does not apply pressure directly to the first semiconductor die, the solder preform having a maximum thickness of 30 μm and a lower melting point than the metal regions; setting a soldering temperature of the soldering process so that the solder preform melts and fully reacts with the metal region of the first semiconductor die and the metal region of the substrate to form one or more intermetallic phases throughout the entire soldered joint, each intermetallic phase having a melting point above the preform melting point and the soldering temperature; and soldering a second semiconductor die to the same or different metal region of the substrate, without applying pressure directly to the second semiconductor die.
Total 500 pages