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181
CN112542422A
半导体器件和形成半导体器件的方法
Substantial Examination
Publication/Patent Number: CN112542422A Publication Date: 2021-03-23 Application Number: 202010906289.9 Filing Date: 2020-09-01 Inventor: 陈彦羽   程仲良   Assignee: 台湾积体电路制造股份有限公司   IPC: H01L21/768 Abstract: 形成半导体器件的方法包括蚀刻介电层以在介电层中形成沟槽,沉积延伸至沟槽中的金属层,对金属层实施氮化工艺以将金属层的部分转换为金属氮化物层,对金属氮化物层实施氧化工艺以形成金属氮氧化物层,去除金属氮氧化物层,并且使用自底向上沉积工艺将金属材料填充至沟槽中以形成接触插塞。本申请的实施例还涉及半导体器件。
182
US2021098337A1
SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
Publication/Patent Number: US2021098337A1 Publication Date: 2021-04-01 Application Number: 16/583,290 Filing Date: 2019-09-26 Inventor: Chiu, Hsih-yang   Assignee: NANYA TECHNOLOGY CORPORATION   IPC: H01L23/48 Abstract: A semiconductor structure including a substrate, a dielectric layer, a conductive via, and a landing pad is provided. The dielectric layer is positioned on the substrate. The conductive via penetrates from a lower surface of the substrate to an upper surface of the dielectric layer. The landing pad is embedded in the conductive via.
183
US2021098297A1
METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE HAVING A DUMMY SECTION
Publication/Patent Number: US2021098297A1 Publication Date: 2021-04-01 Application Number: 17/117,727 Filing Date: 2020-12-10 Inventor: Koike, Osamu   Kadogawa, Yutaka   Assignee: LAPIS Semiconductor Co., Ltd.   IPC: H01L21/768 Abstract: There is provided a semiconductor device comprising a semiconductor substrate having an active area in which a plurality of active elements are formed, and a non-active area excepting the active area; at least one electrode pad electrically connected to any of the active elements. At least one Through Silicon VIA electrode is formed, being electrically connected to the electrode pad by way of the non-active area. The non-active area has an insulating region obtained by forming an insulating film on the semiconductor substrate, and a dummy section obtained by leaving a base material of the semiconductor substrate in the insulating region. The dummy section is provided in a position where an outer edge of the Through Silicon VIA electrode does not intersect with the boundary between the insulating region and the dummy section.
184
CN212967671U
半导体封装器件以及相应的电子装置
Grant
Publication/Patent Number: CN212967671U Publication Date: 2021-04-13 Application Number: 202021390629.9 Filing Date: 2020-07-15 Inventor: W·a·j·林   C·c·李   W·b·郑   M·丁克尔   Assignee: 英飞凌科技股份有限公司   IPC: H01L23/28 Abstract: 公开了一种半导体封装器件(10),所述半导体封装器件(10)包括:封装材料(1)、引脚(2)以及至少部分从封装材料(1)外露的互连夹(3),其中,所述互连夹(3)形成有在封装半导体封装器件(10)之前预先形成在互连夹(3)上的用于标识所述引脚(2)中的至少一个引脚的引脚标识(4)。还公开了一种相应的电子装置(100)。根据本公开,可以简单、低成本地形成不容易消失的引脚标识。
185
CN112655087A
功率半导体装置及其制造方法以及电力变换装置
Public
Publication/Patent Number: CN112655087A Publication Date: 2021-04-13 Application Number: 201980056495.0 Filing Date: 2019-09-04 Inventor: 岩井贵雅   藤野纯司   川岛裕史   Assignee: 三菱电机株式会社   IPC: H01L23/48 Abstract: 功率半导体装置(1)具备:引线部件(10)、半导体元件(20)和模制树脂(30)。引线部件(10)包括多个引线端子(11),多个引线端子(11)从模制树脂(30)的内侧延伸至外侧。多个引线端子(11)各自包括:根基部(11A),在模制树脂(30)的外侧,被配置于放置半导体元件(20)的区域侧并且在从模制树脂(30)突出的方向上延伸;以及末端部(11B),在与根基部(11A)不同的方向上延伸并且从根基部(11A)观察时被配置于放置半导体元件(20)的区域的相反侧。根基部(11A)延伸的长度在多个引线端子(11)中的彼此相邻的1对引线端子(11)之间互不相同。多个引线端子(11)的各个引线端子中的至少根基部(11A)的表面被涂敷树脂(40)覆盖。
186
CN112652593A
半导体结构及其形成方法
Public
Publication/Patent Number: CN112652593A Publication Date: 2021-04-13 Application Number: 201910958246.2 Filing Date: 2019-10-10 Inventor: 章中杰   Assignee: 长鑫存储技术有限公司   IPC: H01L23/48 Abstract: 本发明涉及半导体制造技术领域,尤其涉及一种半导体结构及其形成方法。所述半导体结构包括:基底;第一导电结构,位于所述基底表面;布线层,沿垂直于所述基底的方向嵌入所述基底与所述第一导电结构之间,且所述布线层沿平行于所述基底的方向延伸出所述第一导电结构;第一插塞,沿垂直于所述基底的方向延伸,所述第一插塞的一端与所述布线层延伸出所述第一导电结构的端部电连接、另一端用于与外部电路连接。本发明解决了切割道尺寸缩小而导致的绕线不易布局的问题,避免了结构布局易违反设计原则的问题,确保了半导体结构后续测试结果的可靠性和稳定性。
187
CN112652594A
半导体装置
Public
Publication/Patent Number: CN112652594A Publication Date: 2021-04-13 Application Number: 202010869563.X Filing Date: 2020-08-26 Inventor: 山本纱矢香   Assignee: 富士电机株式会社   IPC: H01L23/48 Abstract: 在半导体装置中优选能够抑制电压和电流中的振荡和噪声的发生。本发明提供一种半导体装置,包括:多个电路部;以及由板状的导电材料形成并连接于任一个电路部的第一连接部和第二连接部,第一连接部和第二连接部的各个主面相对而配置,第一连接部和第二连接部分别具有与电路部连接的电路连接端部和对主面的电流路径进行限制的路径限制部,在路径限制部和电路连接端部之间的电流路径流通的电流的方向在第一连接部和第二连接部不同。在路径限制部与电路连接端部之间的电流路径流通的电流的方向优选在第一连接部和第二连接部相反。
188
CN112216664A
半导体装置和其制造方法
Public
Publication/Patent Number: CN112216664A Publication Date: 2021-01-12 Application Number: 202010619571.9 Filing Date: 2020-07-01 Inventor: 黄文宏   钟燕雯   孙玮筑   Assignee: 日月光半导体制造股份有限公司   IPC: H01L23/48 Abstract: 提供一种半导体装置和其制造方法。所述半导体装置包含天线区和绕线区。所述绕线区安置于所述天线区上,其中所述天线区包含第一绝缘层和两个或更多个第二绝缘层,且所述第一绝缘层的厚度不同于所述第二绝缘层的厚度。
189
US10903174B2
Electronic chip
Publication/Patent Number: US10903174B2 Publication Date: 2021-01-26 Application Number: 16/043,289 Filing Date: 2018-07-24 Inventor: Petitdidier, Sebastien   Assignee: STMICROELECTRONICS (CROLLES 2) SAS   IPC: H01L23/00 Abstract: An electronic chip includes a substrate made of semiconductor material. Conductive pads are located on a front side of the substrate and cavities extend into the substrate from a back side of the substrate. Each cavity reaches an associated conductive pad. Protrusions are disposed on the back side of the substrate. A conductive layer covers the walls and bottoms of the cavities. The conductive layer includes portions on the back side, each portion partially located on an associated protrusion and electrically connecting two of the conductive pads.
190
EP3761361A1
SEMICONDUCTOR DEVICE, SEMICONDUCTOR MODULE AND VEHICLE
Publication/Patent Number: EP3761361A1 Publication Date: 2021-01-06 Application Number: 19868884.8 Filing Date: 2019-09-17 Inventor: Nakayama, Tomoya   Osawa, Akihiro   Assignee: FUJI ELECTRIC CO., LTD.   IPC: H01L25/07 Abstract: Provided is a semiconductor device including: a circuit board; a wiring pattern; a first semiconductor chip and a second semiconductor chip that are provided above the circuit board and that are provided along a first direction in a plane parallel to a board surface; a first lead frame for electrically connecting the first semiconductor chip and the wiring pattern; and a second lead frame for electrically connecting the second semiconductor chip and the wiring pattern; wherein the first lead frame and the second lead frame each comprises: a chip joining portion provided above at least a part of the semiconductor chip; a wiring joining portion provided above at least a part of the wiring pattern; and a bridging portion for connecting the chip joining portion and the wiring joining portion; and in the first direction, a space between the bridging portion of the first lead frame and the bridging portion of the second lead frame is smaller than a space between the chip joining portion of the first lead frame and the chip joining portion of the second lead frame.
191
CN112310588A
一种基于硅通孔的三维混合环耦合器
Public
Publication/Patent Number: CN112310588A Publication Date: 2021-02-02 Application Number: 201910705621.2 Filing Date: 2019-08-01 Inventor: 卢启军   刘阳   尹湘坤   Assignee: 西安电子科技大学昆山创新研究院   IPC: H01P5/12 Abstract: 本发明公开了一种基于硅通孔的三维混合环耦合器,所述三维混合环耦合器包括硅衬底层模块、顶层模块和底层模块,所述顶层模块设置在所述硅衬底层模块的上表面,所述底层模块设置在所述硅衬底层模块的下表面;所述硅衬底模块包括贯穿于硅衬底的接地屏蔽环和信号互连柱,所述信号互连柱设置在所述接地屏蔽环的中心区域,所述接地屏蔽环外周侧壁设置有第一介质层,所述接地屏蔽环的内周侧壁设置有第二介质层,所述信号互连柱的外周侧壁设置有第三介质层。本发明基于硅通孔技术,与其它硅基元件兼容性好,易于实现微波系统的三维集成化;采用接地层和接地屏蔽环将信号线和硅衬底隔离开,降低了信号传输损耗,提升了各个分支之间的电磁隔离特性。
192
US2021050281A1
Surface Treatment Method and Apparatus for Semiconductor Packaging
Publication/Patent Number: US2021050281A1 Publication Date: 2021-02-18 Application Number: 17/073,937 Filing Date: 2020-10-19 Inventor: Chang, Chih-horng   Deng, Jie-cheng   Kuo, Tin-hao   Chen, Ying-yu   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.   IPC: H01L23/48 Abstract: A surface treatment and an apparatus for semiconductor packaging are provided. A surface of a conductive layer is treated to create a roughened surface. In one example, nanowires are formed on a surface of the conductive layer. In the case of a copper conductive layer, the nanowires may include a CuO layer. In another example, a complex compound is formed on a surface of the conductive layer. The complex compound may be formed using, for example, thiol and trimethyl phosphite.
193
CN112435994A
半导体芯片堆叠结构、半导体封装件及其制造方法
Public
Publication/Patent Number: CN112435994A Publication Date: 2021-03-02 Application Number: 202010817356.X Filing Date: 2020-08-14 Inventor: 金庸镐   Assignee: 三星电子株式会社   IPC: H01L25/07 Abstract: 提供了一种半导体芯片堆叠件、半导体封装件及其制造方法。所述半导体芯片堆叠件包括第一半导体芯片和第二半导体芯片。第一芯片包括:第一半导体衬底,其具有有源表面和无源表面;第一绝缘层,其形成在无源表面上;以及第一焊盘,其形成在第一绝缘层中。第二半导体芯片包括:第二半导体衬底,其具有有源表面和无源表面;第二绝缘层,其形成在有源表面上;第二焊盘,其形成在第二绝缘层中;聚合物层,其形成在第二绝缘层上;凸块下金属化(UBM)图案,其埋置在聚合物层中;以及埋置焊料,其分别形成在UBM图案上,并埋置在聚合物层中。埋置焊料的下表面与聚合物层的下表面共面,埋置焊料分别在接触表面处接触第一焊盘,并且埋置焊料的截面面积在接触表面上最大。
194
EP2916349B1
SEMICONDUCTOR MODULE
Publication/Patent Number: EP2916349B1 Publication Date: 2021-03-03 Application Number: 13851225.6 Filing Date: 2013-10-25 Inventor: Sunaga, Takashi   Kaneko, Noboru   Miyoshi, Osamu   Assignee: NSK Ltd.   IPC: H01L21/60
195
US2021066228A1
PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
Publication/Patent Number: US2021066228A1 Publication Date: 2021-03-04 Application Number: 16/557,763 Filing Date: 2019-08-30 Inventor: Lu, Wen-long   Assignee: Advanced Semiconductor Engineering, Inc.   IPC: H01L23/00 Abstract: A package structure includes a base material, at least one electronic device, at least one encapsulant and a plurality of dummy pillars. The electronic device is electrically connected to the base material. The encapsulant covers the electronic device. The dummy pillars are embedded in the encapsulant. At least two of the dummy pillars have different heights.
196
CN112397486A
包括层叠的半导体芯片的半导体封装
Substantial Examination
Publication/Patent Number: CN112397486A Publication Date: 2021-02-23 Application Number: 202010155588.3 Filing Date: 2020-03-09 Inventor: 李硕源   Assignee: 爱思开海力士有限公司   IPC: H01L25/065 Abstract: 包括层叠的半导体芯片的半导体封装。一种半导体封装包括:基板;第一中介层,其设置在基板上方;第一芯片层叠物,其在第一中介层的一侧设置在基板上,其中,第一芯片层叠物包括以在第一方向上偏移的方式层叠的多个第一半导体芯片;第二芯片层叠物,其设置在第一芯片层叠物上,其中,第二芯片层叠物包括以在与第一方向相反的第二方向上偏移的方式层叠的多个第二半导体芯片;以及第三芯片层叠物,其在第一中介层的另一侧设置在基板上,其中,第三芯片层叠物包括以在第二方向上偏移的方式层叠的多个第三半导体芯片。
197
US10943852B2
Semiconductor device and method for manufacturing the same
Publication/Patent Number: US10943852B2 Publication Date: 2021-03-09 Application Number: 16/286,276 Filing Date: 2019-02-26 Inventor: Kume, Ippei   Matsuda, Taketo   Okuda, Shinya   Murano, Masahiko   Assignee: TOSHIBA MEMORY CORPORATION   IPC: H01L23/48 Abstract: According to some embodiments, a semiconductor device includes a semiconductor substrate, a metal portion, a first insulating film, and a second insulating film. The semiconductor substrate has a through-hole extending from a first surface of the semiconductor substrate to a second surface thereof opposite to the first surface. The metal portion is formed in the through-hole. The first insulating film is provided on the second surface of the semiconductor substrate and on a side surface of the through-hole. The second insulating film has a dielectric constant of not more than 6.5 and is provided on a metal portion-side surface of the first insulating film on the side surface of the through-hole of the semiconductor substrate.
198
CN212907715U
一种多功能功率组件
Grant
Publication/Patent Number: CN212907715U Publication Date: 2021-04-06 Application Number: 202022046899.4 Filing Date: 2020-09-17 Inventor: 刘节   陈凯   刘襄随   艾照逵   张栋   Assignee: 襄阳赛克斯电气股份有限公司   IPC: H01L23/44 Abstract: 本实用新型公开了一种多功能功率组件,包括密封油箱和可控硅组件,密封油箱包括箱体及箱盖,箱体内装有变压器油;可控硅组件包括可控硅模块、隔离组件、输入铜排、输入瓷瓶、输出铜排、输出瓷瓶、信号电缆和信号瓷瓶,可控硅模块浸在所述变压器油内并且具有输入端、输出端及控制端,可控硅模块的输入端通过输入铜排连接输入瓷瓶,可控硅模块的输出端通过输出铜排连接输出瓷瓶;隔离组件的输入端通过信号电缆连接信号瓷瓶,隔离组件的输出端连接可控硅模块的控制端。本实用新型通过将可控硅模块浸以变压器油内进行散热,变压器油纯净稳定、粘度小、绝缘性好、冷却性好,而且具有消弧作用,使得可控硅模块作为开关使用时安全可靠。
199
US2021098323A1
Integrated Circuit Package and Method
Publication/Patent Number: US2021098323A1 Publication Date: 2021-04-01 Application Number: 17/120,859 Filing Date: 2020-12-14 Inventor: Yu, Chen-hua   Yeh, Sung-feng   Chen, Ming-fa   Chen, Hsien-wei   Liu, Tzuan-horng   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L23/31 Abstract: A device package includes a first die directly bonded to a second die at an interface, wherein the interface comprises a conductor-to-conductor bond. The device package further includes an encapsulant surrounding the first die and the second die and a plurality of through vias extending through the encapsulant. The plurality of through vias are disposed adjacent the first die and the second die. The device package further includes a plurality of thermal vias extending through the encapsulant and a redistribution structure electrically connected to the first die, the second die, and the plurality of through vias. The plurality of thermal vias is disposed on a surface of the second die and adjacent the first die.