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No. Publication Number Title Publication/Patent Number Publication/Patent Number Publication Date Publication Date
Application Number Application Number Filing Date Filing Date
Inventor Inventor Assignee Assignee IPC IPC
1 EP3039716B1
ULTRA FINE PITCH AND SPACING INTERCONNECTS FOR SUBSTRATE
Publication/Patent Number: EP3039716B1 Publication Date: 2020-04-08 Application Number: 14762163.5 Filing Date: 2014-08-25 Inventor: Kim, Chin-kwan   Kumar, Rajneesh   Bchir, Omar James   Assignee: Qualcomm Incorporated   IPC: H01L23/498
2 EP1673808B1
ELECTRONIC DEVICE AND CARRIER SUBSTRATE
Publication/Patent Number: EP1673808B1 Publication Date: 2020-01-01 Application Number: 04770151.1 Filing Date: 2004-10-01 Inventor: Coenen, Martinus J.   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L23/498
3 EP2515332B1
Bondwireless Power Module with Three-Dimensional Current Routing
Publication/Patent Number: EP2515332B1 Publication Date: 2020-06-24 Application Number: 12159773.6 Filing Date: 2012-03-15 Inventor: Hauenstein, Henning M.   Gorgerino, Andrea   Assignee: Infineon Technologies Americas Corp.   IPC: H01L23/498
4 CN110720141A
具有适形目标焊盘的可变形电气触点
Under Examination
Title (English): Deformable electrical contacts with conformable target pads
Publication/Patent Number: CN110720141A Publication Date: 2020-01-21 Application Number: 201880037900.X Filing Date: 2018-05-22 Inventor: B·哈巴   G·z·格瓦拉   Assignee: 伊文萨思公司   IPC: H01L23/498 Abstract: 本发明提供了用于微电子组装和其他应用的具有适形目标焊盘的可变形电气触点。例如,在管芯级或晶片级的微电子组装期间,第一基板上的多个可变形电气触点可以被接合到第二基板上的多个适形焊盘。每个可变形触点变形至某个程度,该程度与第一基板和第二基板之间的接合压力的量相关。变形工艺还利用可变形电气触点擦拭每个相应的适形焊盘以形成新的金属与金属接触以便进行良好的传导。每个适形的焊盘在被可压缩材料加压时塌缩,以呈现电气触点的近似变形的形状,从而提供大导电表面积,同时还补偿水平不对准。可以升高温度以熔化电介质,该电介质封装电气连接、平衡两个基板之间的间隙和变化,并且将两个基板永久性地固定在一起。
5 CN109326575B
一种低成本重布线凸点封装结构的制造方法
Publication/Patent Number: CN109326575B Publication Date: 2020-03-31 Application Number: 201811124910.5 Filing Date: 2018-09-26 Inventor: 任玉龙   孙鹏   Assignee: 华进半导体封装先导技术研发中心有限公司   IPC: H01L23/498 Abstract: 本发明公开了一种低成本重布线凸点封装结构的制造方法,包括:在晶圆上形成PVD种子层;在PVD种子层表面形成RDL层光刻胶;对形成的RDL层光刻胶进行图形化曝光,形成RDL曝光区域;在曝光后的RDL层光刻胶上形成Bump层光刻胶;进行Bump层光刻胶的图像化曝光,形成Bump曝光区域;显影形成Bump和RDL电镀窗口;电镀形成RDL和Bump结构;以及去除光刻胶及外漏的PVD种子层。该方法将两次光刻工艺结合,通过一次电镀工艺即可以完成重布线和凸点两制程,减少了工艺步骤,缩短了工艺时间,可以节约设备、材料成本,提高产能。
6 US2020335433A1
WIRING SUBSTRATE, ELECTRONIC DEVICE, AND ELECTRONIC MODULE
Publication/Patent Number: US2020335433A1 Publication Date: 2020-10-22 Application Number: 16/957,616 Filing Date: 2018-12-27 Inventor: Kisaki, Takuo   Sasaki, Takahiro   Assignee: KYOCERA Corporation   IPC: H01L23/498 Abstract: To provide a wiring substrate, an electronic device, and an electronic module the size of which can be easily reduced and the strength of which can be maintained. A wiring substrate includes an insulation substrate and an electrical wiring structure. The insulation substrate includes a recess section in one surface. A frame portion of the insulation substrate that forms a side surface which connects an opened surface and a bottom surface of the recess section to each other includes a first conductive portion having a plate shape in the frame portion.
7 CN210516711U
基于电镀技术的3D成型陶瓷封装基板与软板的连接结构
Valid
Publication/Patent Number: CN210516711U Publication Date: 2020-05-12 Application Number: 201921675343.2 Filing Date: 2019-10-09 Inventor: 罗素扑   吴朝晖   袁广   孙瑞   彭少学   罗正权   Assignee: 西安柏芯创达电子科技有限公司   IPC: H01L23/498 Abstract: 本实用新型公开一种基于电镀技术的3D成型陶瓷封装基板与软板的连接结构,包括有陶瓷封装基板,该陶瓷封装基板的表面金属化形成有线路底层,进一步包括有软板,该软板包括有保护膜和设置于保护膜内的柔性线路,柔性线路的连接端外露于保护膜并与对应的线路底层贴合,且对应的线路底层上电镀形成有连接镀层,该连接镀层包覆住连接端并导通连接于连接端和线路底层之间。通过电镀形成有连接镀层,利用连接镀层包覆住连接端并导通连接于连接端和线路底层之间,取代了传统之采用导热胶的方式,连接镀层不易老化,使得软板与陶瓷封装基板之间的连接更加的稳固,从而也有效提高线路连接的稳定性和可靠性。
8 CN111816635A
薄膜覆晶封装结构
Under Examination
Publication/Patent Number: CN111816635A Publication Date: 2020-10-23 Application Number: 201910507450.2 Filing Date: 2019-06-12 Inventor: 林士熙   Assignee: 南茂科技股份有限公司   IPC: H01L23/498 Abstract: 本发明提供一种薄膜覆晶封装结构,其包括可挠性薄膜、至少二导电件、绝缘体、至少二第一上引脚、至少二下引脚及芯片。可挠性薄膜具有相对的第一表面与第二表面以及位于第一表面的芯片设置区内的至少一贯孔。第二表面具有与芯片设置区相重叠的投影区。此二导电件与绝缘体设置于贯孔内,且此二导电件被绝缘体分隔开而电性分离。此二第一上引脚设置于芯片设置区内,且分别连接此二导电件。此二下引脚自投影区内向外延伸,且分别通过此二导电件电性连接此二第一上引脚。芯片设置于芯片设置区内且包括至少二第一凸块,此二第一凸块接合于此二第一上引脚。
9 US2020135629A1
POWER MODULE OF DOUBLE-FACED COOLING
Publication/Patent Number: US2020135629A1 Publication Date: 2020-04-30 Application Number: 16/387,979 Filing Date: 2019-04-18 Inventor: Kim, Young Seok   Hong, Kyoung Kook   Assignee: HYUNDAI MOTOR COMPANY   KIA MOTORS CORPORATION   IPC: H01L23/498 Abstract: A power module of double-faced cooling includes: an upper substrate; a lower substrate on which a plurality of semiconductor chips are disposed; and a first spacer disposed between the upper substrate and the lower substrate, electrically connecting the upper substrate and the lower substrate to each other, and disposed on the lower substrate to be equally distanced from each of the semiconductor chips. Power is supplied to the semiconductor chips on the lower substrate through the upper substrate and the first spacer.
10 EP2828890B1
AN ASSEMBLY AND A CHIP PACKAGE
Publication/Patent Number: EP2828890B1 Publication Date: 2020-08-12 Application Number: 13712945.8 Filing Date: 2013-03-18 Inventor: Musk, Robert William   Assignee: EFFECT Photonics B.V.   IPC: H01L23/498
11 EP3516687B1
POWER SEMICONDUCTOR MODULE WITH DIMPLES IN METALLIZATION LAYER BELOW FOOT OF TERMINAL
Publication/Patent Number: EP3516687B1 Publication Date: 2020-02-19 Application Number: 18733874.4 Filing Date: 2018-06-27 Inventor: Maleki, Milad   Fischer, Fabian   TrÜssel, Dominik   Guillemin, Remi Alain   Schneider, Daniel   Assignee: ABB Power Grids Switzerland AG   IPC: H01L23/498
12 EP3718136A1
SEMICONDUCTOR ASSEMBLY AND METHOD OF PRODUCING THE SEMICONDUCTOR ASSEMBLY
Publication/Patent Number: EP3718136A1 Publication Date: 2020-10-07 Application Number: 19716805.7 Filing Date: 2019-03-26 Inventor: Ochs, Ewgenij   Pfefferlein, Stefan   Assignee: Siemens Aktiengesellschaft   IPC: H01L23/498
13 CN111048484A
半导体封装件
Publication/Patent Number: CN111048484A Publication Date: 2020-04-21 Application Number: 201910953921.2 Filing Date: 2019-10-09 Inventor: 金正守   韩平和   裴成桓   李镇洹   Assignee: 三星电子株式会社   IPC: H01L23/498 Abstract: 本发明提供一种半导体封装件,所述半导体封装件包括:连接结构,具有彼此背对的第一表面和第二表面,并包括重新分布层;半导体芯片,设置在所述连接结构的所述第一表面上,并具有连接到所述重新分布层的连接垫;包封剂,设置在所述连接结构的所述第一表面上并包封所述半导体芯片;钝化层,设置在所述连接结构的所述第二表面上,并具有分别使所述重新分布层的第一区域和第二区域暴露的多个第一开口和多个第二开口;以及多个凸块下金属凸块,分别通过所述多个第一开口连接到所述重新分布层的所述第一区域。
14 CN107887361B
扇出型半导体封装件
Valid
Publication/Patent Number: CN107887361B Publication Date: 2020-08-04 Application Number: 201710244624.1 Filing Date: 2017-04-14 Inventor: 金亨俊   李斗焕   Assignee: 三星电子株式会社   IPC: H01L23/498 Abstract: 提供一种扇出型半导体封装件。半导体芯片设置在第一连接构件的通孔中。半导体芯片的至少一部分被包封剂包封。包括重新分布层的第二连接构件形成在半导体芯片的有效表面上。具有优良的可靠性的外部连接端子形成在包封剂中。
15 EP3731269A1
SELF-EQUALIZED AND SELF-CROSSTALK-COMPENSATED 3D TRANSMISSION LINE ARCHITECTURE WITH ARRAY OF PERIODIC BUMPS FOR HIGH-SPEED SINGLE-ENDED SIGNAL TRANSMISSION
Publication/Patent Number: EP3731269A1 Publication Date: 2020-10-28 Application Number: 20163316.1 Filing Date: 2020-03-16 Inventor: Yong, Khang Choong   Ho, Ying Ern   Lim, Yun Rou   Song, Wil Choon   Hall, Stephen   Assignee: INTEL Corporation   IPC: H01L23/498 Abstract: Embodiments include package substrates and method of forming the package substrates. A package substrate includes a dielectric over a conductive layer, and a conductive line on the dielectric. The package substrate includes a plurality of conductive bumps on a surface of the conductive line, where the conductive bumps are conductively coupled to the conductive line, and a solder resist over the conductive line and the dielectric. The surface of the conductive line may be a bottom surface, where the conductive bumps are below the conductive line and conductively coupled to the bottom surface of the conductive line, and where the conductive bumps may be embedded in the dielectric. The surface of the conductive line may be a top surface, where the conductive bumps are above the conductive line and conductively coupled to the top surface of the conductive line, and wherein the conductive bumps are embedded in the solder resist.
16 EP3002785B1
SEMICONDUCTOR DEVICE
Publication/Patent Number: EP3002785B1 Publication Date: 2020-11-11 Application Number: 15187405.4 Filing Date: 2015-09-29 Inventor: Funatsu, Katsuhiko   Sato, Yukihiro   Kanazawa, Takamitsu   Koido, Masahiro   Taya, Hiroyoshi   Assignee: Renesas Electronics Corporation   IPC: H01L23/498
17 CN111919294A
汇流排、用于制造其的方法以及包括其的功率模块
Public
Publication/Patent Number: CN111919294A Publication Date: 2020-11-10 Application Number: 201980019984.9 Filing Date: 2019-03-18 Inventor: 迈克尔·滕纳斯   Assignee: 丹佛斯硅动力有限责任公司   IPC: H01L23/498 Abstract: 提供了一种适用于半导体功率模块(8)的导电汇流排(2,4)。该汇流排(2,4)包括:主板(210,410)、从该主板(210,410)延伸的一个或多个支腿(220,420)、以及在这些支腿(220,420)的自由端处形成的一个或多个支脚(230,430)。根据本发明,这些支腿(220,420)中的至少一个支腿与相关联的支脚(230,430)之间的相交线(L)相对于该主板(210,410)的纵向方向(X)形成偏移角(α)。
18 US2020258828A1
INTERPOSER AND ELECTRONIC DEVICE
Publication/Patent Number: US2020258828A1 Publication Date: 2020-08-13 Application Number: 16/861,731 Filing Date: 2020-04-29 Inventor: Iida, Kanto   Koyama, Hiromasa   Assignee: Murata Manufacturing Co., Ltd.   IPC: H01L23/498 Abstract: An interposer includes a stacked body including insulating base material layers that are stacked on one another, first and second electrodes, a conductor pattern, and an interlayer connection conductor. The stacked body includes a first mounting surface including a first electrode, and a second mounting surface facing the first mounting surface and including a second electrode. The first electrode is electrically connected to the second electrode through the conductor pattern and the interlayer connection conductor. A length of an electrical path including conductor patterns connecting the first electrode and the second electrode is larger than a total length of the interlayer connection conductor in a stacking direction.
19 CN110783305A
具有再分布线结构的扇出型半导体封装件
Public
Title (English): Fan-out semiconductor package with re-wiring structure
Publication/Patent Number: CN110783305A Publication Date: 2020-02-11 Application Number: 201910450006.1 Filing Date: 2019-05-28 Inventor: 金钟润   李锡贤   Assignee: 三星电子株式会社   IPC: H01L23/498 Abstract: 提供了一种包括再分布线结构的扇出型半导体封装件。扇出型半导体封装件包括:再分布线结构,所述再分布线结构包括多个再分布线绝缘层和多个再分布线图案,每一个所述再分布线图案位于所述多个再分布线绝缘层中的一个再分布线绝缘层的上表面和下表面之一上;至少一个半导体芯片,所述至少一个半导体芯片布置在所述再分布线结构上并且所占据的覆盖区域的水平宽度小于所述再分布线结构的水平宽度;以及模制构件,所述模制构件在所述再分布线结构上包围所述至少一个半导体芯片并且所述模制构件的水平宽度小于所述再分布线结构的水平宽度,其中,所述多个再分布线绝缘层具有阶梯结构。
20 CN110945651A
在端子的脚部下方的金属化层中具有凹陷的功率半导体模块
Under Examination
Publication/Patent Number: CN110945651A Publication Date: 2020-03-31 Application Number: 201880046301.4 Filing Date: 2018-06-27 Inventor: M.马莱基   F.菲舍尔   D.特吕泽尔   R-a.吉耶曼   D.施奈德   Assignee: ABB电网瑞士股份公司   IPC: H01L23/498 Abstract: 一种功率半导体模块(10)包括:绝缘衬底(14),所述绝缘衬底(14)具有顶部金属化层(22);半导体芯片(40),所述半导体芯片(40)接合到顶部金属化层(22);以及端子(12),所述端子(12)利用脚部(28)焊接到顶部金属化层(22)并且电互连到半导体芯片(40)。顶部金属化层(22)和衬底(14)的与顶部金属化层(22)相对设置的底部金属化层(44)中的至少一个包括多个凹陷(34),所述多个凹陷(34)在焊接脚部(28)下方和/或在焊接脚部(28)周围分布在连接区域(32)中。