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No. Publication Number Title Publication/Patent Number Publication/Patent Number Publication Date Publication Date
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1
CN112234046A
包括用于抵消磁通量的耦合器的电气组件
Public
Publication/Patent Number: CN112234046A Publication Date: 2021-01-15 Application Number: 202010679562.9 Filing Date: 2020-07-15 Inventor: J·崔   洪政先   黄韬   Assignee: 马克西姆综合产品公司   IPC: H01L23/522 Abstract: 一种电气组件包括:(a)第一电感器,该第一电感器包括围绕第一绕组轴缠绕的第一绕组;(b)第二电感器,该第二电感器在第一方向上与该第一电感器分离;以及(c)耦合器,该耦合器在该第一方向上至少部分地布置在该第一电感器与该第二电感器之间,该耦合器形成电路的至少一部分,从而使得电流能够流过该耦合器,并且该耦合器关于该第二电感器的划分轴是不对称的,该划分轴在与该第一方向正交的第二方向上延伸。
2
US2021074631A1
SEMICONDUCTOR DEVICE
Publication/Patent Number: US2021074631A1 Publication Date: 2021-03-11 Application Number: 17/084,854 Filing Date: 2020-10-30 Inventor: Takizawa, Shin   Noma, Seiji   Nonaka, Yusuke   Yanagi, Shinichirou   Kasahara, Atsushi   Ikeura, Shogo   Assignee: DENSO CORPORATION   IPC: H01L23/522 Abstract: On a substrate, a wiring layer is arranged by sequentially stacking a first insulation film, a lower electrode, a second insulation film, an intermediate electrode, a third insulation film, and an upper electrode in this order. A capacitor includes a first capacitor having the lower electrode and the intermediate electrode, and a second capacitor having the intermediate electrode and the upper electrode. The first capacitor and the second capacitor are connected in parallel to each other by electrically connecting the lower electrode and the upper electrode. Further, the intermediate electrode has a higher potential than the lower layer electrode and the upper electrode.
3
CN112368831A
一种集成电路
Public
Publication/Patent Number: CN112368831A Publication Date: 2021-02-12 Application Number: 201880095158.8 Filing Date: 2018-09-21 Inventor: 邹小卫   郑伟   吴春蕾   Assignee: 华为技术有限公司   IPC: H01L23/522 Abstract: 本申请公开了一种集成电路,该集成电路包括电容结构,所述电容结构包括设置在多层金属层上的多个金属条阵列,每金属条阵列中包括多个沿相同方向延伸的金属条(P1‑P5,V1‑V5),每个金属条阵列中的金属条(P1‑P5,V1‑V5)包括第一极金属条和第二极金属条,且第一极金属条和第二极金属条分别电连接不同的电极(E1,E2),如此,在同层金属层上可以形成横向电容。另外,每层金属层上的金属条阵列中的金属条的延伸方向与相邻金属层上的金属阵列中的金属条的延伸方向不同,因而,位于相邻两层金属层上的、在金属层所在平面上的投影有交叠的第一极金属条和第二极金属条之间也可以形成纵向电容。因而,该电容结构的电容密度较大,电容品质较高。
4
CN112510012A
一种沟槽式电容器件及制备方法
Substantial Examination
Publication/Patent Number: CN112510012A Publication Date: 2021-03-16 Application Number: 202011551017.8 Filing Date: 2020-12-24 Inventor: 顾学强   葛星晨   范春晖   Assignee: 上海集成电路装备材料产业创新中心有限公司   上海集成电路研发中心有限公司   成都微光集电科技有限公司   IPC: H01L23/522 Abstract: 本发明提供一种沟槽式电容器件及制备方法,所述沟槽式电容器件的沟槽电容结构位于沟槽介质层远离所述衬底的一侧,且填充贯穿所述沟槽介质层的第一沟槽,电连接所述第一金属互连层,电容侧墙覆盖所述沟槽电容结构的侧面,电极互连层填充贯穿所述沟槽介质层的第二沟槽,电连接所述第二金属互连层。所述电容侧墙避免了所述沟槽电容结构的上电极层和下电极层的短路,达到了提高器件性能和可靠性的目的,具有显著的意义。
5
EP3783646A2
SINGLE CHIP SIGNAL ISOLATOR
Publication/Patent Number: EP3783646A2 Publication Date: 2021-02-24 Application Number: 20188658.7 Filing Date: 2020-07-30 Inventor: Briano, Robert A.   Uberti, Bruno Luis   Milesi, Alejandro Gabriel   Monreal, Gerardo A.   Assignee: Allegro MicroSystems, LLC   IPC: H01L23/522 Abstract: Methods and apparatus for a signal isolator IC package including a die having a first die portion isolated from a second die portion. The first die portion is surrounded on six sides by first insulative material and the second die portion is surrounded on six sides by second insulative material. The first die portion provides a first voltage domain and the second die portion provides a second voltage domain. The signal isolator comprises a first signal path between the first die portion and the second die portion, wherein the first signal path is isolated with respect to the first and second die portions.
6
CN108231732B
集成电路的电源网
Grant
Publication/Patent Number: CN108231732B Publication Date: 2021-03-26 Application Number: 201710840586.6 Filing Date: 2017-09-18 Inventor: 希兰梅·毕斯沃斯   杨国男   王中兴   Assignee: 台湾积体电路制造股份有限公司   IPC: H01L23/522 Abstract: 本公开提供了一种集成电路的一电源网。上述电源网包括形成于一第一金属层的多个第一电源线与多个第二电源线,以及形成于一第二金属层的多个第三电源线与多个第四电源线。上述第二电源线是平行于上述第一电源线。上述第一与第二电源线是交错在上述第一金属层。上述第三电源线是垂直于上述第一电源线。上述第四电源线是平行于上述第三电源线。上述第三与第四电源线是交错在上述第二金属层。从个别的上述第一电源线至相邻的两个上述第二电源线的距离是相同的。从个别的上述第三电源线至相邻的两个上述第四电源线的距离是不同的。
7
CN112166501A
半导体器件中的片上电容器结构
Substantial Examination
Publication/Patent Number: CN112166501A Publication Date: 2021-01-01 Application Number: 202080002255.5 Filing Date: 2020-09-02 Inventor: 陈亮   Assignee: 长江存储科技有限责任公司   IPC: H01L23/522 Abstract: 公开了半导体器件以及用于形成半导体器件的方法的实施例。在示例中,一种半导体器件包括半导体层、与半导体层的第一侧接触的第一层间电介质(ILD)层、多个电介质切口、以及多个第一触点,每个电介质切口贯穿半导体层垂直地延伸以将半导体层分隔成多个半导体块,每个第一触点贯穿第一ILD层垂直地延伸并且分别与多个半导体块接触。
8
CN112635434A
半导体器件结构及其制备方法
Public
Publication/Patent Number: CN112635434A Publication Date: 2021-04-09 Application Number: 201910906125.3 Filing Date: 2019-09-24 Inventor: 王津洲   Assignee: 芯恩(青岛)集成电路有限公司   IPC: H01L23/522 Abstract: 本发明提供一种半导体器件结构及其制备方法。半导体器件结构包括基底、复合膜层和第一导电插塞;复合膜层位于基底表面,复合膜层由N层导体层与M层拓扑绝缘体层交错层叠构成,拓扑绝缘体层包括非导电区域及位于非导电区域外围的导电区域,其中,N与M均为大于等于2的整数且N与M差值的绝对值小于等于1;多个第一导电插塞将被单层导体层间隔开的两层拓扑绝缘体层的导电区域相连,第一导电插塞与导体层绝缘。本发明有利于增加器件电感,提高器件性能。且本发明还可以将拓扑绝缘体层的非导电区域作为电容的介电质并进一步实现多个电容的并联,从而在增加器件电容的同时降低器件的低频阻抗而使器件的高频共振维持不变,有利于器件性能的提升。
9
US2021028129A1
SEMICONDUCTOR DEVICE WITH GUARD RING
Publication/Patent Number: US2021028129A1 Publication Date: 2021-01-28 Application Number: 17/036,409 Filing Date: 2020-09-29 Inventor: Hara, Akio   Sawada, Toyoji   Okuno, Masaki   Ochimizu, Hirosato   Assignee: Socionext Inc.   IPC: H01L23/58 Abstract: A semiconductor device includes a substrate having a circuit region and a peripheral region disposed around and enclosing the circuit region in a plan view, a first interconnect layer formed on the substrate, a second interconnect layer formed on the first interconnect layer, a third interconnect layer formed on the second interconnect layer, and a guard ring formed in the peripheral region, wherein the guard ring includes a first interconnect formed in the first interconnect layer, and disposed around and enclosing the circuit region in a plan view, a second interconnect formed in the third interconnect layer, and disposed around and enclosing the circuit region in a plan view, and a first via connected to the first interconnect and to the second interconnect, and disposed in a groove shape along a perimeter edge of the substrate in a plan view.
10
US2021028165A1
Capacitor Structure
Publication/Patent Number: US2021028165A1 Publication Date: 2021-01-28 Application Number: 16/905,936 Filing Date: 2020-06-19 Inventor: Yu, Sz-ying   Chang, Jui-yu   Chen, Chien-wen   Assignee: Realtek Semiconductor Corp.   IPC: H01L27/06 Abstract: The present invention provides a capacitor structure including a metal oxide semiconductor (MOS) capacitor and a metal oxide metal (MOM) capacitor. A gate electrode, a source electrode and a drain electrode of the MOS capacitor have a first finger-shaped structure implemented by a first metal layer. The MOM capacitor comprises a second finger-shaped structure implemented by a second metal layer. The second metal layer is adjacent to the first metal layer in a vertical direction.
11
CN112201643A
一种半导体器件及形成方法
Substantial Examination
Publication/Patent Number: CN112201643A Publication Date: 2021-01-08 Application Number: 201910610914.2 Filing Date: 2019-07-08 Inventor: 殷原梓   Assignee: 中芯国际集成电路制造(北京)有限公司   中芯国际集成电路制造(上海)有限公司   IPC: H01L23/522 Abstract: 本发明实施例提供了一种半导体器件及形成方法。在本发明实施例中,在半导体器件的上层金属层上形成高强度的平坦化保护层,平坦化保护层在应力作用下,不易形成裂纹,在平坦化保护层上方的金属间隔离层中出现裂纹时,能够避免裂纹向下扩大延伸,由此,可以保护在平坦化保护层下方的结构,从而避免对平坦化保护层下方的结构的破坏,能够提高半导体器件的可靠性。
12
US2021098472A1
VERTICAL SEMICONDUCTOR DEVICES
Publication/Patent Number: US2021098472A1 Publication Date: 2021-04-01 Application Number: 16/892,563 Filing Date: 2020-06-04 Inventor: Kim, Manjoong   Assignee: Samsung Electronics Co., Ltd.   IPC: H01L27/115 Abstract: A vertical semiconductor device includes a substrate, a cell array region and a pad region formed on the substrate, and gate patterns and respective insulation layers. The gate patterns may be stacked in a vertical direction perpendicular to an upper surface of the substrate. Each of the gate patterns may extend in a first direction parallel to the upper surface of the substrate on the cell array region and the pad region of the substrate. The gate patterns may include pads, respectively, at edge portions thereof in the first direction. The respective insulation layers may be between adjacent gate patterns in the vertical direction. The gate patterns and the insulation layer on the pad region may serve as a pad structure, and the pad structure may include a first staircase structure having a stepped shape, a second staircase structure having a stepped shape and disposed below the first staircase structure, a flat surface portion between the first and second staircase structures, and a dummy staircase structure formed on the flat surface portion. The dummy staircase structure may be spaced apart from each of the first and second staircase structures.
13
US2021057330A1
SINGLE CHIP SIGNAL ISOLATOR
Publication/Patent Number: US2021057330A1 Publication Date: 2021-02-25 Application Number: 16/547,823 Filing Date: 2019-08-22 Inventor: Briano, Robert A.   Uberti, Bruno Luis   Milesi, Alejandro Gabriel   Monreal, Gerardo A.   Assignee: Allegro MicroSystems, LLC   IPC: H01L23/522 Abstract: Methods and apparatus for a signal isolator IC package including a die having a first die portion isolated from a second die portion. The first die portion is surrounded on six sides by first insulative material and the second die portion is surrounded on six sides by second insulative material. The first die portion provides a first voltage domain and the second die portion provides a second voltage domain. The signal isolator comprises a first signal path between the first die portion and the second die portion, wherein the first signal path is isolated with respect to the first and second die portions.
14
US10944402B1
Reconfigurable interconnect structure in integrated circuits
Publication/Patent Number: US10944402B1 Publication Date: 2021-03-09 Application Number: 16/791,559 Filing Date: 2020-02-14 Inventor: Kim, Seongjong   Anders, Mark A.   Kaul, Himanshu   Assignee: Intel Corporation   IPC: H03K19/17756 Abstract: Some embodiments include apparatuses having a first circuit path including drive units coupled in series between a first node and a first additional node, a second circuit path including drive units coupled in series between a second node and a second additional node, each drive unit of the driver units of the first circuit path and the second circuit path including an inverter, and a transmission gate circuit including an input node and an output node coupled to an input node and an output node, respectively, of the inverter; and control circuitry to provide control information to the transmission gate circuit of each of the driver units of the first circuit path and the second circuit path.
15
US2021090988A1
PATTERNED SHIELDING STRUCTURE
Publication/Patent Number: US2021090988A1 Publication Date: 2021-03-25 Application Number: 16/830,555 Filing Date: 2020-03-26 Inventor: Yen, Hsiao-tsung   Shih, Kuan-yu   Tsai, Chih-yu   Chan, Ka-un   Assignee: Realtek Semiconductor Corporation   IPC: H01L23/522 Abstract: A patterned shielding structure is disposed between an inductor structure and a substrate. The patterned shielding structure includes a shielding layer and a first stacked structure. The shielding layer extends along a plane. The first stacked structure is stacked, along a first direction, on the shielding layer. The first direction is perpendicular to the plane. The first stacked structure has a crossed shape and is configured to enhance a shielding effect.
16
US2021091089A1
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
Publication/Patent Number: US2021091089A1 Publication Date: 2021-03-25 Application Number: 16/578,782 Filing Date: 2019-09-23 Inventor: Ho, Jar-ming   Assignee: NANYA TECHNOLOGY CORPORATION   IPC: H01L27/108 Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a plurality of landing pads disposed over the substrate, at least one of the plurality of landing pads comprising a protruding portion of a capacitor plug and a first spacer over the protruding portion, wherein a width of the first spacer is larger than a width of the capacitor plug; a plurality of bit line contacts disposed over the substrate and a plurality of bit lines respectively disposed over the plurality of bit line contacts. The bit line is an undulating stripe extending between two adjacent capacitor contacts; and a plurality of capacitor structures respectively disposed over the plurality of landing pads.
17
CN112542443A
利用有色阻挡的自对准图案化以及由其形成的结构
Public
Publication/Patent Number: CN112542443A Publication Date: 2021-03-23 Application Number: 202010586924.X Filing Date: 2020-06-24 Inventor: M.k.哈兰   R.帕特尔   R.e.申克   C.h.华莱士   Assignee: 英特尔公司   IPC: H01L23/522 Abstract: 描述了利用有色阻挡的自对准图案化和所得到的结构。在一个示例中,集成电路结构包括衬底上方的层间电介质(ILD)层和该ILD层上的硬掩模层。多个导电互连线位于ILD层和硬掩模层中并且由该ILD层和硬掩模层间隔开。多个导电互连线包括具有第一宽度的第一互连线。第二互连线以第一距离紧邻第一互连线,第二互连线具有第一宽度。第三互连线以第一距离紧邻第二互连线,第三互连线具有第一宽度。第四互连线以大于第一距离的第二距离紧邻第三互连线,第四互连线具有大于第一宽度的第二宽度。
18
US2021050259A1
SELF-ALIGNED TOP VIA SCHEME
Publication/Patent Number: US2021050259A1 Publication Date: 2021-02-18 Application Number: 16/540,497 Filing Date: 2019-08-14 Inventor: Xie, Ruilong   Yang, Chih-chao   Radens, Carl   Li, Juntao   Cheng, Kangguo   Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION   IPC: H01L21/768 Abstract: A semiconductor device includes a base structure including a lower level via and a lower level dielectric layer, a conductive pillar including an upper level line and an upper level via disposed on the lower level via, and a protective structure disposed between the lower level via and the upper level line. The protective structure includes a material having an etch rate less than or equal to that of the lower level via.
19
CN112542455A
具有金属氧化物帽盖的接触部以抑制短接的有源栅极上方接触部
Public
Publication/Patent Number: CN112542455A Publication Date: 2021-03-23 Application Number: 202010582897.9 Filing Date: 2020-06-23 Inventor: R·胡拉尼   R·弗里兰   G·埃尔巴兹   M·昌德霍克   R·e·申克尔   G·辛格   F·格瑟特莱恩   N·卡比尔   T·a·特罗尼克   E·韩   Assignee: 英特尔公司   IPC: H01L27/088 Abstract: 描述了具有金属氧化物帽盖结构的有源栅极上方接触部。在示例中,一种集成电路结构包括衬底上方的多个栅极结构,栅极结构中的每个在其上包括栅极绝缘层。多个导电沟槽接触结构与多个栅极结构交替,导电沟槽接触结构中的每个在其上包括金属氧化物帽盖结构。层间电介质材料在多个栅极结构上方并且在多个导电沟槽接触结构上方。开口在层间电介质材料中并且在多个栅极结构中的对应的一个的栅极绝缘层中。导电过孔在开口中,导电过孔与多个栅极结构中的对应的一个直接接触,并且导电过孔在金属氧化物帽盖结构中的一个或多个的一部分上。
20
US2021074634A1
MODULE STRUCTURE AND METHOD FOR MANUFACTURING THE MODULE STRUCTURE
Publication/Patent Number: US2021074634A1 Publication Date: 2021-03-11 Application Number: 16/965,909 Filing Date: 2018-07-09 Inventor: Zuo, Chengjie   He, Jun   Assignee: ANHUI ANUKI TECHNOLOGIES CO., LTD.   IPC: H01L23/522 Abstract: The module structure includes a substrate, a passive element, metal columns and a chip. The passive element, the metal columns and the chip are located on a same side of the substrate. The passive element is located between the substrate and the film where the metal columns and the chip are located. The following applies: the vertical projection of the chip on the substrate overlaps a line segment or closed figure formed by endpoints constituted by the vertical projections of the metal columns on the substrate; the vertical projection of the passive element on the substrate overlaps the line segment or closed figure formed by the endpoints constituted by the vertical projections of the metal columns on the substrate; or the vertical projection of the passive element on the substrate overlaps the vertical projection of the chip on the substrate.